KR20220135499A - Printed circuit board and method for manufacturing the same - Google Patents

Printed circuit board and method for manufacturing the same Download PDF

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Publication number
KR20220135499A
KR20220135499A KR1020210041247A KR20210041247A KR20220135499A KR 20220135499 A KR20220135499 A KR 20220135499A KR 1020210041247 A KR1020210041247 A KR 1020210041247A KR 20210041247 A KR20210041247 A KR 20210041247A KR 20220135499 A KR20220135499 A KR 20220135499A
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KR
South Korea
Prior art keywords
chip
metal layer
circuit board
printed circuit
circuit pattern
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KR1020210041247A
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Korean (ko)
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정선미
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주식회사 세일티앤엔
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Priority to KR1020210041247A priority Critical patent/KR20220135499A/en
Publication of KR20220135499A publication Critical patent/KR20220135499A/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

An embodiment of the present invention provides a printed circuit board in which a chip and a circuit pattern is connected by a simple process, and a method for manufacturing the same. The method for manufacturing a printed circuit board according to an embodiment includes the steps of: preparing a carrier on which a first metal layer is formed; attaching a chip onto the first metal layer; connecting a connection terminal of the chip and the first metal layer with a connection wire; forming an insulating layer on the first metal layer and the chip, and forming a second metal layer on the insulating layer; removing the carrier; and selectively removing the first metal layer and the second metal layer, to form a first circuit pattern and a second circuit pattern including a connection circuit pattern.

Description

인쇄회로기판 제조 방법{PRINTED CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME}PRINTED CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME

최근 전자 제품이 미세화, 패키지화, 소형화되는 추세에 따라, 미세화, 패키지화, 소형화된 인쇄회로기판에 대한 수요도 증가하고 있다.With the recent trend of miniaturization, packaging, and miniaturization of electronic products, the demand for miniaturized, packaged, and miniaturized printed circuit boards is also increasing.

이에 따라, 인쇄회로기판에 칩을 내장한 내장형(Embedded) 인쇄회로기판에 대한 수요도 증가하고 있다.Accordingly, the demand for an embedded printed circuit board in which a chip is embedded in the printed circuit board is also increasing.

내장형 인쇄회로기판을 제조하는 공정에는, 상기 인쇄회로기판에 내장되는 칩과, 상기 인쇄회로기판의 회로 패턴들을 연결하는 공정이 포함된다.A process of manufacturing an embedded printed circuit board includes a process of connecting a chip embedded in the printed circuit board and circuit patterns of the printed circuit board.

칩에는 베어 칩(Bare Chip)과, 상기 베어 칩에 재배선층이 형성된 웨이퍼 레벨 패키지 단계의 칩(Wafer Level Package : WLP)이 있을 수 있다. 그런데 베어 칩의 경우, 외부 회로나 소자 등과 연결되기 위한 연결단자가 너무 작거나, 연결단자 간의 피치(Pitch)가 좁아서 회로 패턴과의 연결이 어려운 문제가 있다. 따라서, 상기 베The chip may include a bare chip and a wafer level package (WLP) chip in which a redistribution layer is formed on the bare chip. However, in the case of the bare chip, there is a problem in that the connection terminal for connection to an external circuit or device is too small or the pitch between the connection terminals is narrow, so that it is difficult to connect with the circuit pattern. Therefore, the

어 칩에 추가적으로 재배선층을 형성하여, 이러한 문제를 해결해왔으나, 상기 재배선층을 형성하는 추가적인공정이 필요하여, 제조 공정이 효율적이지 못하고 수율이 떨어지며, 제조 단가가 상승하는 문제가 있다.Although this problem has been solved by forming an additional redistribution layer on the chip, an additional process for forming the redistribution layer is required, so that the manufacturing process is not efficient, the yield is reduced, and the manufacturing cost is increased.

따라서, 상기 베어 칩을 사용하여 외부 회로나 소자를 연결할 수 있는 인쇄회로기판의 제조 방법이 개발될 필요가 있다.Accordingly, there is a need to develop a method for manufacturing a printed circuit board capable of connecting an external circuit or device using the bare chip.

실시예는 새로운 구조의 인쇄회로기판 및 그 제조방법을 제공한다.The embodiment provides a printed circuit board having a novel structure and a method for manufacturing the same.

실시예는 칩과 회로패턴을 간단한 공정에 의해 연결하는 인쇄회로기판 및 그 제조방법을 제공한다.The embodiment provides a printed circuit board for connecting a chip and a circuit pattern by a simple process and a method for manufacturing the same.

실시예는 새로운 구조의 인쇄회로기판 및 그 제조방법을 제공할 수 있다.The embodiment may provide a printed circuit board having a novel structure and a method for manufacturing the same.

실시예는 칩의 연결단자가 작거나, 회로패턴이 미세한 경우에도, 연결와이어에 의해 간단하고 효율적으로 칩과 회로패턴을 연결하는 인쇄회로기판 및 그 제조방법을 제공할 수 있다.The embodiment can provide a printed circuit board and a method of manufacturing the same for simply and efficiently connecting the chip and the circuit pattern by a connecting wire even when the connection terminal of the chip is small or the circuit pattern is fine.

본 발명에 따른 실시예의 설명에 있어서, 각 층(막), 영역, 패턴 또는 구조물들이 기판, 각 층(막), 영역, 패드 또는 패턴들의 "상/위(on)"에 또는 "하/아래(under)"에 형성되는 것으로 기재되는 경우에 있어, "상/위(on)"와 "하/아래(under)"는 "직접(directly)" 또는 "다른 층을 개재하여 (indirectly)" 형성되는 것을 모두In the description of embodiments according to the present invention, each layer (film), region, pattern or structure is placed “on” or “below/below” the substrate, each layer (film), region, pad or pattern. In the case of being described as being formed in "under", "on" and "under" are formed "directly" or "indirectly" through another layer. all that becomes

포함한다. 또한 각 층의 위 또는 아래에 대한 기준은 도면을 기준으로 설명한다.include In addition, the criteria for above or below each layer will be described with reference to the drawings.

도면에서 각층의 두께나 크기는 설명의 편의 및 명확성을 위하여 과장되거나 생략되거나 또는 개략적으로 도시되었다. 또한 각 구성요소의 크기는 실제크기를 전적으로 반영하는 것은 아니다.In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. Also, the size of each component does not fully reflect the actual size.

도 1 내지 도 11은 본 발명의 실시예에 따른 인쇄회로기판 및 그 제조방법을 설명한 도면이다.1 to 11 are views illustrating a printed circuit board and a method of manufacturing the same according to an embodiment of the present invention.

먼저, 도 11을 참조하면, 도 11에 도시된 인쇄회로기판은 본 발명의 바람직한 일 실시예에 따라 제조된 인쇄회로기판이다.First, referring to FIG. 11 , the printed circuit board shown in FIG. 11 is a printed circuit board manufactured according to a preferred embodiment of the present invention.

상기 인쇄회로기판은, 연결회로패턴(85)을 포함하는 제1 회로패턴(80); 상기 제1 회로패턴(80) 상에 부착된 칩(40); 상기 칩(40)의 연결단자(41)와 상기 연결회로패턴(85)을 연결하는 연결와이어(25); 상기 칩(40) 및 제1회로패턴(80) 상에 형성된 제1 절연층(50); 상기 제1 절연층(50) 상에 형성된 제2 회로패턴(81); 상기 제1, 제2회로패턴(80)(81) 및 제1 절연층(50)을 관통하는 제1 도전비아(70); 상기 제1, 제2 회로패턴(80)(81) 및 제1 도전비아(70)에 형성된 제2 절연층(90); 상기 제2 절연층(90) 상에 형성된 제3 회로패턴(120); 제1, 제2 회로패턴(80)(81)과 제3 회로패턴(120)을 연결하는 제2 도전비아(110)를 포함한다.The printed circuit board may include: a first circuit pattern 80 including a connection circuit pattern 85; a chip 40 attached to the first circuit pattern 80; a connection wire 25 connecting the connection terminal 41 of the chip 40 and the connection circuit pattern 85; a first insulating layer 50 formed on the chip 40 and the first circuit pattern 80; a second circuit pattern 81 formed on the first insulating layer 50; a first conductive via 70 penetrating the first and second circuit patterns 80 and 81 and the first insulating layer 50; a second insulating layer 90 formed on the first and second circuit patterns 80 and 81 and the first conductive via 70; a third circuit pattern 120 formed on the second insulating layer 90; and a second conductive via 110 connecting the first and second circuit patterns 80 and 81 and the third circuit pattern 120 .

이하, 도 1 내지 도 11을 참조하여, 실시예에 따른 인쇄회로기판 및 그 제조방법에 대해 보다 상세히 설명하도록 한다.Hereinafter, a printed circuit board and a method of manufacturing the same according to an embodiment will be described in more detail with reference to FIGS. 1 to 11 .

도 1을 참조하면, 제1 금속층(20)이 형성된 캐리어(10)가 준비된다.상기 제1 금속층(20)은 금속, 예를 들어, 구리(Cu), 주석(Sn), 알루미늄(Al), 니켈(Ni), 금(Au), 은(Ag) 중 적어도 어느 하나로 형성될 수 있다.Referring to FIG. 1 , the carrier 10 on which the first metal layer 20 is formed is prepared. The first metal layer 20 is made of a metal, for example, copper (Cu), tin (Sn), or aluminum (Al). , nickel (Ni), gold (Au), may be formed of at least one of silver (Ag).

상기 제1 금속층(20)은 상기 캐리어(10) 상에 전체적으로 형성되어 준비될 수 있다.The first metal layer 20 may be prepared by being entirely formed on the carrier 10 .

또는 상기 제1 금속층(20)은 상기 캐리어(10)가 준비된 후, 스퍼터링 공정, 도금 공정 및 적층 공정 등을 통해 형성될 수 있다.Alternatively, the first metal layer 20 may be formed through a sputtering process, a plating process, a lamination process, etc. after the carrier 10 is prepared.

상기 캐리어(10)는 금속 또는 수지 재질로 형성될 수 있다. 다만, 상기 캐리어(10)는 상기 제1 금속층(20)과 다른 재질로 형성된다.The carrier 10 may be formed of a metal or resin material. However, the carrier 10 is formed of a material different from that of the first metal layer 20 .

도 2를 참조하면, 상기 제1 금속층(20)을 선택적으로 제거하여, 위치결정홈(21)을 형성할 수 있다. 상기 위치결정홈(21)은 상기 인쇄회로기판에 형성될 제1 회로패턴(80) 및 연결회로패턴(85)을 형성하는 위치, 칩(40)을 부착하는 위치 등에 대한 기준이 될 수 있다. 더 상세한 내용은 해당 공정에서 후술한다.Referring to FIG. 2 , the first metal layer 20 may be selectively removed to form the positioning groove 21 . The positioning groove 21 may be a reference for a position for forming the first circuit pattern 80 and a connection circuit pattern 85 to be formed on the printed circuit board, a position for attaching the chip 40 , and the like. Further details will be described later in the corresponding process.

상기 위치결정홈(21)은 상기 제1 금속층(20) 상에 포토레지스트 패턴(미도시)을 형성한 후, 상기 포토레지스트패턴(미도시)을 마스크로 하여, 상기 제1 금속층(20)에 에칭을 실시하여 형성할 수 있다.The positioning groove 21 is formed on the first metal layer 20 with a photoresist pattern (not shown), and then formed on the first metal layer 20 using the photoresist pattern (not shown) as a mask. It can be formed by etching.

예를 들어, 상기 위치결정홈(21)은 상기 제1 금속층(20)의 가장자리에 형성될 수 있다. 즉, 상기위치결정홈(21)은 후에 형성될 제1 회로패턴(80)에 형성될 수 있으며, 바람직하게는 상기 제1 회로패턴(80)의 가장자리에 형성될 수 있다. 하지만 상기 위치결정홈(21)의 위치는 필요에 따라 다양하게 정해질 수 있다.For example, the positioning groove 21 may be formed at an edge of the first metal layer 20 . That is, the positioning groove 21 may be formed in the first circuit pattern 80 to be formed later, and preferably, may be formed at the edge of the first circuit pattern 80 . However, the position of the positioning groove 21 may be variously determined as needed.

도 3을 참조하면, 상기 제1 금속층(20) 상에 접착층(30)을 형성한 후, 상기 접착층(30) 상에 칩(40)을 부착한다.Referring to FIG. 3 , after the adhesive layer 30 is formed on the first metal layer 20 , the chip 40 is attached on the adhesive layer 30 .

상기 접착층(30)은 상기 칩(40)이 부착되는 위치에 국부적으로 형성된 것으로 도시되었으나, 필요에 따라, 상기 제1 금속층(20)에 전체적으로 도포될 수 있다.Although the adhesive layer 30 is illustrated as being locally formed at a position where the chip 40 is attached, it may be entirely applied to the first metal layer 20 if necessary.

상기 접착층(30)은 접착력을 가진 재질, 예를 들어, 에폭시 수지 또는 페놀 수지로 형성될 수 있다.The adhesive layer 30 may be formed of a material having an adhesive force, for example, an epoxy resin or a phenol resin.

상기 칩(40)은 베어 칩(Bare Chip) 이거나, 상기 베어 칩에 재배선층을 형성한 웨이퍼 레벨 패키지(WaferLevel Package : WLP) 단계의 칩 또는 와이어 본딩(Wire Bonding)에 의해 연결될 수 있는 칩을 모두 포함할 수 있다.The chip 40 is a bare chip, a chip of a wafer level package (WLP) stage in which a redistribution layer is formed on the bare chip, or a chip that can be connected by wire bonding. may include

상기 칩(40)은 상기 칩(40)을 외부 회로나 소자 등과 전기적으로 연결하는 연결단자(41)를 포함할 수 있다.The chip 40 may include a connection terminal 41 electrically connecting the chip 40 to an external circuit or device.

상기 칩(40)이 부착되는 위치는 상기 위치결정홈(21)에 의해 결정될 수 있다. 상세히 설명하면, 상기접착층(30)을 상기 위치결정홈(21)을 기준으로, 미리 설계되어 정해진 상기 칩(40)의 부착 위치에 형성하고,상기 접착층(30) 상에 상기 칩(40)을 부착할 수 있다.A position at which the chip 40 is attached may be determined by the positioning groove 21 . In detail, the adhesive layer 30 is formed at the attachment position of the chip 40 which is designed in advance based on the positioning groove 21 , and the chip 40 is formed on the adhesive layer 30 . can be attached

도 4를 참조하면, 상기 칩(40)의 연결단자(41)와 상기 제1 금속층(20)을 연결와이어(25)에 의해 연결할 수 있다.Referring to FIG. 4 , the connection terminal 41 of the chip 40 and the first metal layer 20 may be connected by a connection wire 25 .

상기 연결와이어(25)와 연결되는 상기 제1 금속층(20) 상의 위치는, 상기 위치결정홈(21)에 의해 결정될 수 있다.A position on the first metal layer 20 connected to the connection wire 25 may be determined by the positioning groove 21 .

상기 연결와이어(25)와 연결되는 상기 제1 금속층(20) 상의 위치에는 후에 연결회로패턴(85)이 형성된다. 더 자세한 내용은 후술한다.A connection circuit pattern 85 is later formed at a position on the first metal layer 20 connected to the connection wire 25 . More details will be described later.

종래에는 칩과 회로패턴을 연결할 때, 상기 칩과 회로패턴 사이의 절연층에 도전비아를 형성하여 연결하였다.Conventionally, when a chip and a circuit pattern are connected, a conductive via is formed in an insulating layer between the chip and the circuit pattern to be connected.

그런데, 상기한 대로, 상기 칩(40)은 베어 칩(Bare Chip) 이거나, 상기 베어 칩에 재배선층을 형성한 웨이퍼레벨 패키지(Wafer Level Package : WLP) 단계의 칩 또는 와이어 본딩으로 연결될 수 있는 모든 칩을 포함할 수 있는데, 상기 칩(40)이 베어 칩인 경우, 상기 칩(40)의 연결단자(41) 간의 간격(Pitch)이 좁고(150μm이하), 상기 연결단자(41)의 너비도 좁아서(100μm 이하), 상기 도전비아를 형성하여 외부 회로나 소자와 연결하기가 어려운 문제가 있다.However, as described above, the chip 40 is a bare chip, or a chip of a wafer level package (WLP) stage in which a redistribution layer is formed on the bare chip or any chip that can be connected by wire bonding. It may include a chip, and when the chip 40 is a bare chip, the pitch between the connection terminals 41 of the chip 40 is narrow (150 μm or less), and the width of the connection terminal 41 is also narrow. (100 μm or less), there is a problem in that it is difficult to form the conductive via and connect it to an external circuit or device.

Claims (1)

제1 금속층이 형성된 캐리어가 준비되는 단계;
상기 제1 금속층 상에 칩을 부착하는 단계;
상기 칩의 연결단자와 제1 금속층을 연결와이어에 의해 연결하는 단계;
상기 제1 금속층 및 상기 칩 상에 절연층을 형성하고, 상기 절연층 상에 제2 금속층을 형성하는 단계;
상기 캐리어를 제거하는 단계; 및 상기 제1 금속층 및 제2 금속층을 선택적으로 제거하여 연결회로패턴을 포함하는 제1 회로패턴 및 제2 회로패턴을 형성하는 단계를 포함하는 인쇄회로기판 제조 방법.Preparing a carrier on which the first metal layer is formed;
attaching a chip on the first metal layer;
connecting the connecting terminal of the chip and the first metal layer by a connecting wire;
forming an insulating layer on the first metal layer and the chip, and forming a second metal layer on the insulating layer;
removing the carrier; and forming a first circuit pattern and a second circuit pattern including a connection circuit pattern by selectively removing the first metal layer and the second metal layer.
KR1020210041247A 2021-03-30 2021-03-30 Printed circuit board and method for manufacturing the same KR20220135499A (en)

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