KR20220131486A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a semiconductor device with improved reliability and electrical characteristics and a method for manufacturing the same. The semiconductor device includes: a first active pattern on a substrate, the first active pattern comprising a pair of first source/drain patterns and a first channel pattern between the first source/drain patterns; a gate electrode on the first channel pattern; a first gate spacer on the first channel on a sidewall of the gate electrode, the first gate spacer comprising a first spacer and a second spacer, wherein an upper surface of the first spacer is lower than an upper surface of the second spacer; a first blocking pattern on the first spacer; and a gate contact connected to the gate electrode. The first blocking pattern is positioned between the gate contact and the second spacer.

Description

Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device including a field effect transistor and a method for manufacturing the same.

A semiconductor device includes an integrated circuit including MOS field effect transistors (MOS (Metal Oxide Semiconductor) FETs). As the size and design rule of semiconductor devices are gradually reduced, the scale down of the MOS field effect transistors is also accelerating. As the size of the MOS field effect transistors is reduced, the operating characteristics of the semiconductor device may be deteriorated. Accordingly, various methods for forming semiconductor devices with superior performance while overcoming limitations due to high integration of semiconductor devices are being studied.

An object of the present invention is to provide a semiconductor device having improved reliability and electrical characteristics.

An object of the present invention is to provide a method of manufacturing a semiconductor device having improved reliability and electrical characteristics.

According to a concept of the present invention, a semiconductor device includes: a first active pattern on a substrate, the first active pattern including a pair of first source/drain patterns and a first channel pattern therebetween; a gate electrode on the first channel pattern; a first gate spacer on a sidewall of the gate electrode, the first gate spacer comprising a first spacer and a second spacer, wherein an upper surface of the first spacer is lower than an upper surface of the second spacer; a first blocking pattern on the first spacer; and a gate contact connected to the gate electrode. The first blocking pattern may be interposed between the gate contact and the second spacer.

According to another concept of the present invention, a semiconductor device includes an active pattern on a substrate, the active pattern including a pair of source/drain patterns and a channel pattern therebetween; a gate electrode on the channel pattern; a gate spacer on a sidewall of the gate electrode; a gate capping pattern on the gate contact; a gate contact passing through the gate capping pattern and connecting to the gate electrode; and a blocking pattern between the gate contact and the gate spacer. The blocking pattern may extend along a sidewall of the gate contact and guide the gate contact not to pass over the gate spacer, and the blocking pattern may include a material having an etch selectivity to the gate spacer.

According to another concept of the present invention, a semiconductor device includes: a substrate including a PMOSFET region and an NMOSFET region spaced apart from each other in a first direction; a first active pattern on the PMOSFET region and a second active pattern on the NMOSFET region; a device isolation layer covering lower sidewalls of the first and second active patterns, an upper portion of each of the first and second active patterns protrude above the device isolation layer; a gate electrode crossing the first and second active patterns and extending in the first direction; A first source/drain pattern and a second source/drain pattern provided on the upper portions of the first and second active patterns, respectively, and each of the first and second source/drain patterns are adjacent to one side of the gate electrode do; a gate insulating layer interposed between the gate electrode and the first and second active patterns; a gate spacer on a sidewall of the gate electrode; a gate capping pattern on an upper surface of the gate electrode; a gate cutting pattern passing through the gate electrode; an interlayer insulating layer on the gate capping pattern and the gate cutting pattern; an active contact electrically connected to at least one of the first and second source/drain patterns through the interlayer insulating layer; a gate contact passing through the interlayer insulating layer and the gate capping pattern and electrically connected to the gate electrode; an upper insulating pattern provided on the active contact adjacent to the gate contact; a blocking pattern between the gate contact and the gate spacer; a first metal layer on the interlayer insulating layer, the first metal layer including a power wiring vertically overlapping the gate cutting pattern, and first wirings electrically connected to the active contact and the gate contact, respectively; and a second metal layer on the first metal layer. The second metal layer includes second wirings electrically connected to the first metal layer, the blocking pattern is positioned between the gate contact and the upper insulating pattern, and the gate contact includes the blocking pattern and the upper insulating pattern. It may be spaced apart from the active contact with an insulating pattern interposed therebetween.

According to another concept of the present invention, a method of manufacturing a semiconductor device includes: forming an active pattern on a substrate; forming a sacrificial pattern crossing the active pattern; forming a gate spacer including a first spacer and a second spacer on a sidewall of the sacrificial pattern; forming a source/drain pattern adjacent to the sacrificial pattern on the active pattern; removing the sacrificial pattern to form an empty space; forming a gate insulating layer and a gate electrode in the empty space; recessing the first spacer; forming a blocking pattern on the recessed first spacer; forming a gate capping pattern covering the blocking pattern on the gate electrode; and forming a gate contact connected to the gate electrode through the gate capping pattern.

The semiconductor device according to the present invention may include a blocking pattern between the gate contact and the gate spacer for guiding the gate contact. The blocking pattern may prevent generation of an extension in the gate contact, thereby preventing a short circuit between the gate contact and an active contact adjacent thereto or a source/drain pattern. As a result, the reliability of the semiconductor device can be improved.

1 to 3 are conceptual views for explaining logic cells of a semiconductor device according to embodiments of the present invention.
4 is a plan view illustrating a semiconductor device according to embodiments of the present invention.
5A to 5E are cross-sectional views taken along line A-A', line B-B', line C-C', line D-D', and line E-E' of FIG. 4, respectively.
FIG. 6 is an enlarged cross-sectional view of region M of FIG. 5A .
FIG. 7 is an enlarged cross-sectional view of region N of FIG. 5E .
8 is an enlarged cross-sectional view of region M of FIG. 5A according to a comparative example of the present invention.
9A and 9B are enlarged cross-sectional views of region M of FIG. 5A according to another exemplary embodiment of the present invention.
10, 12, 14, and 16 are plan views for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention.
11A, 13A, 15A, and 17A are cross-sectional views taken along line A-A' of FIGS. 10, 12, 14 and 16, respectively.
11B, 13B, 15B, and 17B are cross-sectional views taken along line B-B' of FIGS. 10, 12, 14 and 16, respectively.
11C, 13C, 15C, and 17C are cross-sectional views taken along line C-C' of FIGS. 10, 12, 14 and 16, respectively.
11D, 13D, 15D, and 17D are cross-sectional views taken along line D-D' of FIGS. 10, 12, 14 and 16, respectively.
13E, 15E, and 17E are cross-sectional views taken along line E-E' of FIGS. 12, 14, and 16, respectively.
18A, 19A, 20A, 21A, 22A, and 23A are enlarged views for explaining a method in which region M of FIG. 17A is formed.
18B, 19B, 20B, 21B, 22B, and 23B are enlarged views for explaining a method in which the N region of FIG. 17E is formed.
24A to 24E are for explaining a semiconductor device according to embodiments of the present invention, and are, respectively, lines A-A', B-B', C-C', D-D' and They are cross-sectional views taken along line E-E'.

1 to 3 are conceptual views for explaining logic cells of a semiconductor device according to embodiments of the present invention.

Referring to FIG. 1 , a single height cell (SHC) may be provided. Specifically, the first power line M1_R1 and the second power line M1_R2 may be provided on the substrate 100 . The first power line M1_R1 may be a passage through which a drain voltage VDD, for example, a power voltage is provided. The second power line M1_R2 may be a path through which a source voltage VSS, for example, a ground voltage is provided.

A single height cell SHC may be defined between the first power line M1_R1 and the second power line M1_R2 . The single height cell SHC may include one PMOSFET region PR and one NMOSFET region NR. In other words, the single height cell SHC may have a CMOS structure provided between the first power line M1_R1 and the second power line M1_R2 .

Each of the PMOSFET region PR and the NMOSFET region NR may have a first width W1 in the first direction D1 . A length of the single height cell SHC in the first direction D1 may be defined as the first height HE1 . The first height HE1 may be substantially equal to a distance (eg, a pitch) between the first power line M1_R1 and the second power line M1_R2 .

A single height cell (SHC) may constitute one logic cell. In this specification, a logic cell may mean a logic element (eg, AND, OR, XOR, XNOR, inverter, etc.) that performs a specific function. That is, the logic cell may include transistors constituting a logic element and wirings connecting the transistors to each other.

Referring to FIG. 2 , a double height cell (DHC) may be provided. Specifically, a first power line M1_R1 , a second power line M1_R2 , and a third power line M1_R3 may be provided on the substrate 100 . The first power line M1_R1 may be disposed between the second power line M1_R2 and the third power line M1_R3 . The third power line M1_R3 may be a passage through which the drain voltage VDD is provided.

A double height cell DHC may be defined between the second power line M1_R2 and the third power line M1_R3 . The double height cell DHC may include a first PMOSFET region PR1 , a second PMOSFET region PR2 , a first NMOSFET region NR1 , and a second NMOSFET region NR2 .

The first NMOSFET region NR1 may be adjacent to the second power line M1_R2 . The second NMOSFET region NR2 may be adjacent to the third power line M1_R3 . The first and second PMOSFET regions PR1 and PR2 may be adjacent to the first power line M1_R1 . In a plan view, the first power line M1_R1 may be disposed between the first and second PMOSFET regions PR1 and PR2 .

A length of the double height cell DHC in the first direction D1 may be defined as a second height HE2 . The second height HE2 may be about twice the first height HE1 of FIG. 1 . The first and second PMOSFET regions PR1 and PR2 of the double height cell DHC may be bundled to operate as one PMOSFET region.

Accordingly, the channel size of the PMOS transistor of the double height cell DHC may be larger than the channel size of the PMOS transistor of the single height cell SHC of FIG. 1 . For example, the channel size of the PMOS transistor of the double height cell DHC may be about twice the size of the channel size of the PMOS transistor of the single height cell SHC. As a result, the double height cell DHC may operate at a higher speed than the single height cell SHC. In the present invention, the double height cell (DHC) shown in FIG. 2 may be defined as a multi-height cell. Although not shown, the multi-height cell may include a triple-height cell whose cell height is about three times that of a single height cell (SHC).

Referring to FIG. 3 , a first single height cell SHC1 , a second single height cell SHC2 , and a double height cell DHC may be two-dimensionally disposed on a substrate 100 . The first single height cell SHC1 may be disposed between the first and second power lines M1_R1 and M1_R2 . The second single height cell SHC2 may be disposed between the first and third power lines M1_R1 and M1_R3 . The second single height cell SHC2 may be adjacent to the first single height cell SHC1 in the first direction D1 .

The double height cell DHC may be disposed between the second and third power lines M1_R2 and M1_R3. The double height cell DHC may be adjacent to the first and second single height cells SHC1 and SHC2 in the second direction D2 .

A separation structure DB may be provided between the first single height cell SHC1 and the double height cell DHC and between the second single height cell SHC2 and the double height cell DHC. The active region of the double height cell DHC may be electrically separated from the active region of each of the first and second single height cells SHC1 and SHC2 by the isolation structure DB.

4 is a plan view illustrating a semiconductor device according to embodiments of the present invention. 5A to 5E are cross-sectional views taken along line A-A', line B-B', line C-C', line D-D', and line E-E' of FIG. 4, respectively. FIG. 6 is an enlarged cross-sectional view of region M of FIG. 5A . FIG. 7 is an enlarged cross-sectional view of region N of FIG. 5E .

4 and 5A to 5E , a substrate 100 including a first region RG1 and a second region RG2 may be provided. The substrate 100 may be a semiconductor substrate including silicon, germanium, silicon-germanium, or the like, or a compound semiconductor substrate. For example, the substrate 100 may be a silicon substrate.

The first region RG1 may be a logic cell region. First and second single height cells SHC1 and SHC2 may be provided on the first region RG1 . Logic transistors constituting a logic circuit may be disposed on each of the first and second single height cells SHC1 and SHC2 . The first and second single height cells SHC1 and SHC2 according to the present embodiment are an example of the first and second single height cells SHC1 and SHC2 of FIG. 3 in more detail.

The second region RG2 may be a peripheral region. The second region RG2 may include a long gate transistor having a relatively long gate length (ie, a channel length). The transistor of the second region RG2 may be operated with a higher power than the transistor of the first region RG1 . Hereinafter, the transistor of the first region RG1 will be described in detail with reference to FIGS. 4 and 5A to 5D .

The first region RG1 may include a first PMOSFET region PR1 , a second PMOSFET region PR2 , a first NMOSFET region NR1 , and a second NMOSFET region NR2 . Each of the first PMOSFET region PR1 , the second PMOSFET region PR2 , the first NMOSFET region NR1 , and the second NMOSFET region NR2 may extend in the second direction D2 .

A first PMOSFET region PR1 , a second PMOSFET region PR2 , a first NMOSFET region NR1 , and a second NMOSFET region NR2 may be defined by the second trench TR2 formed on the substrate 100 . can For example, the second trench TR2 may be positioned between the first NMOSFET region NR1 and the first PMOSFET region PR1 . A second trench TR2 may be positioned between the first PMOSFET region PR1 and the second PMOSFET region PR2 . A second trench TR2 may be positioned between the second PMOSFET region PR2 and the second NMOSFET region NR2 .

First active patterns AP1 may be provided on each of the first and second PMOSFET regions PR1 and PR2 . Second active patterns AP2 may be provided on each of the first and second NMOSFET regions NR1 and NR2 .

The first and second active patterns AP1 and AP2 may extend parallel to each other in the second direction D2 . The first and second active patterns AP1 and AP2 are a part of the substrate 100 and may be vertically protruding portions. A first trench TR1 may be defined between the first active patterns AP1 adjacent to each other and between the second active patterns AP2 adjacent to each other. The first trench TR1 may be shallower than the second trench TR2 .

The device isolation layer ST may fill the first and second trenches TR1 and TR2. The device isolation layer ST may include a silicon oxide layer. An upper portion of each of the first and second active patterns AP1 and AP2 may protrude vertically above the device isolation layer ST (refer to FIG. 5D ). An upper portion of each of the first and second active patterns AP1 and AP2 may have a fin shape. The device isolation layer ST may not cover an upper portion of each of the first and second active patterns AP1 and AP2 . The device isolation layer ST may cover lower sidewalls of each of the first and second active patterns AP1 and AP2 .

First source/drain patterns SD1 may be provided on each of the first and second PMOSFET regions PR1 and PR2 . First source/drain patterns SD1 may be provided on each of the first active patterns AP1 . The first source/drain patterns SD1 may be impurity regions of the first conductivity type (eg, p-type). A first channel pattern CH1 may be interposed between a pair of first source/drain patterns SD1 adjacent in the second direction D2 .

Second source/drain patterns SD2 may be provided on each of the first and second NMOSFET regions NR1 and NR2 . Second source/drain patterns SD2 may be provided on each of the second active patterns AP2 . The second source/drain patterns SD2 may be impurity regions of the second conductivity type (eg, n-type). A second channel pattern CH2 may be interposed between a pair of second source/drain patterns SD2 adjacent in the second direction D2 .

The first and second source/drain patterns SD1 and SD2 may be epitaxial patterns formed by a selective epitaxial growth process. For example, top surfaces of the first and second source/drain patterns SD1 and SD2 may be coplanar with top surfaces of the first and second channel patterns CH1 and CH2. As another example, upper surfaces of the first and second source/drain patterns SD1 and SD2 may be higher than upper surfaces of the first and second channel patterns CH1 and CH2.

The first source/drain pattern SD1 may include a semiconductor element (eg, SiGe) having a lattice constant greater than a lattice constant of the semiconductor element of the substrate 100 . Accordingly, the pair of first source/drain patterns SD1 may provide compressive stress to the first channel pattern CH1 therebetween. For example, the second source/drain pattern SD2 may include the same semiconductor element (eg, Si) as the substrate 100 .

Gate electrodes GE crossing the first and second active patterns AP1 and AP2 and extending in the first direction D1 may be provided. The gate electrodes GE may be arranged in the second direction D2 at the first pitch. The gate electrodes GE may vertically overlap the first and second channel patterns CH1 and CH2. Each of the gate electrodes GE may surround a top surface and both sidewalls of each of the first and second channel patterns CH1 and CH2 .

Referring back to FIG. 5D , the gate electrode GE may be provided on the first upper surface TS1 of the channel pattern CH1 or CH2 and at least one first sidewall SW1 of the channel pattern CH1 or CH2. have. In other words, the transistor according to the present embodiment may be a three-dimensional field effect transistor (eg, FinFET) in which the gate electrode GE surrounds the channels CH1 and CH2 three-dimensionally.

Referring back to FIGS. 4 and 5A to 5D , the first single height cell SHC1 may have a first boundary BD1 and a second boundary BD2 facing each other in the second direction D2 . The first and second boundaries BD1 and BD2 may extend in the first direction D1 . The first single height cell SHC1 may have a third boundary BD3 and a fourth boundary BD4 facing each other in the first direction D1 . The third and fourth boundaries BD3 and BD4 may extend in the second direction D2 .

The gate cutting patterns CT may be disposed on a boundary parallel to the second direction D2 of each of the first and second single height cells SHC1 and SHC2 . For example, the gate cutting patterns CT may be disposed on the third and fourth boundaries BD3 and BD4 of the first single height cell SHC1 . The gate cutting patterns CT may be arranged at the first pitch along the third boundary BD3 . The gate cutting patterns CT may be arranged at the first pitch along the fourth boundary BD4 . In a plan view, the gate cutting patterns CT on the third and fourth boundaries BD3 and BD4 may be disposed to overlap the gate electrodes GE, respectively.

Referring to FIG. 5D , the gate cutting pattern CT may extend from the device isolation layer ST to the second interlayer insulating layer 120 in the third direction D3 . A top surface of the gate cutting pattern CT may be higher than a top surface of the gate electrode GE. The top surface of the gate cutting pattern CT may be substantially coplanar with the top surface of the gate capping pattern GP. The gate cutting pattern CT may include an insulating material such as a silicon nitride layer, a silicon oxide layer, or a combination thereof.

The gate electrode GE on the first single height cell SHC1 may be separated from each other by the gate electrode GE on the second single height cell SHC2 and the gate cutting pattern CT. A gate cutting pattern CT is interposed between the gate electrode GE on the first single height cell SHC1 and the gate electrode GE on the second single height cell SHC2 aligned with the gate electrode GE in the first direction D1. can be In other words, the gate electrode GE extending in the first direction D1 may be divided into a plurality of gate electrodes GE by the gate cutting patterns CT.

A pair of gate spacers GS may be disposed on both sidewalls of each of the gate electrodes GE. The gate spacers GS may extend in the first direction D1 along the gate electrodes GE. A top surface of the gate spacer GS may be higher than a top surface of the gate electrode GE adjacent thereto. A top surface of the gate spacer GS may be lower than a top surface of the gate capping pattern GP, which will be described later. A top surface of the gate spacer GS may be lower than a top surface of the gate cutting pattern CT.

The gate spacer GS may include at least one of SiCN, SiOCN, and SiN. As an embodiment of the present invention, referring to FIG. 6 , the gate spacer GS may have a multi-layer structure including the first spacer GS1 and the second spacer GS2 . The first spacer GS1 and the second spacer GS2 may include different materials. For example, the first spacer GS1 may include SiOCN, which is a low-k material containing Si, and the second spacer GS2 may include an insulating material containing Si having excellent etching resistance, for example, SiN. have. The dielectric constant of the first spacer GS1 may be smaller than the dielectric constant of the second spacer GS2 .

Referring back to FIGS. 4 and 5A to 5D , a gate capping pattern GP may be provided on each of the gate electrodes GE. The gate capping pattern GP may extend in the first direction D1 along the gate electrode GE. The gate capping pattern GP may include a material having etch selectivity with respect to the first and second interlayer insulating layers 110 and 120 to be described later. Specifically, the gate capping pattern GP may include at least one of SiON, SiCN, SiOCN, and SiN.

A gate insulating layer GI may be interposed between the gate electrode GE and the first active pattern AP1 and between the gate electrode GE and the second active pattern AP2 . The gate insulating layer GI may extend along the bottom surface of the gate electrode GE thereon. For example, the gate insulating layer GI may cover the first upper surface TS1 and the first sidewall SW1 of the channel pattern CH1 or CH2. The gate insulating layer GI may cover the upper surface of the device isolation layer ST under the gate electrode GE (refer to FIG. 5D ).

In an embodiment of the present invention, the gate insulating layer GI may include a high-k material having a higher dielectric constant than that of the silicon oxide layer. For example, the high-k material may include hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide. It may include at least one of oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

In another embodiment, the semiconductor device of the present invention may include a negative capacitance (NC) FET using a negative capacitor. For example, the gate insulating layer GI may include a ferroelectric material layer having ferroelectric properties and a paraelectric material layer having paraelectric properties.

The ferroelectric material layer may have a negative capacitance, and the paraelectric material layer may have a positive capacitance. For example, when two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the total capacitance is decreased than the capacitance of each individual capacitor. On the other hand, when at least one of the capacitances of two or more capacitors connected in series has a negative value, the total capacitance may have a positive value and be greater than the absolute value of each individual capacitance.

When the ferroelectric material film having a negative capacitance and the paraelectric material film having a positive capacitance are connected in series, the total capacitance of the serially connected ferroelectric material film and the paraelectric material film may increase. By using the increase in the overall capacitance value, the transistor including the ferroelectric material layer may have a subthreshold swing (SS) of less than 60 mV/decade at room temperature.

The ferroelectric material layer may have ferroelectric properties. The ferroelectric material film is, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium oxide. titanium oxide). Here, for example, hafnium zirconium oxide may be a material in which hafnium oxide is doped with zirconium (Zr). As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

The ferroelectric material layer may further include a doped dopant. For example, dopants are aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce) ), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). Depending on which ferroelectric material the ferroelectric material layer includes, the type of dopant included in the ferroelectric material layer may vary.

When the ferroelectric material layer includes hafnium oxide, the dopant included in the ferroelectric material layer includes, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y). may include

When the dopant is aluminum (Al), the ferroelectric material layer may include 3 to 8 at% (atomic %) of aluminum. Here, the ratio of the dopant may be a ratio of aluminum to the sum of hafnium and aluminum.

When the dopant is silicon (Si), the ferroelectric material layer may contain 2 to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material layer may include 2 to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material layer may contain 1 to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material layer may include 50 to 80 at% of zirconium.

The paraelectric material layer may have paraelectric properties. The paraelectric material layer may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material layer may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

The ferroelectric material layer and the paraelectric material layer may include the same material. The ferroelectric material film may have ferroelectric properties, but the paraelectric material film may not have ferroelectric properties. For example, when the ferroelectric material layer and the paraelectric material layer include hafnium oxide, the crystal structure of hafnium oxide included in the ferroelectric material layer is different from the crystal structure of hafnium oxide included in the paraelectric material layer.

The ferroelectric material layer may have a thickness having ferroelectric properties. The thickness of the ferroelectric material layer may be, for example, 0.5 to 10 nm, but is not limited thereto. Since the critical thickness representing the ferroelectric properties may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

For example, the gate insulating layer GI may include one ferroelectric material layer. As another example, the gate insulating layer GI may include a plurality of ferroelectric material layers spaced apart from each other. The gate insulating layer GI may have a stacked structure in which a plurality of ferroelectric material layers and a plurality of paraelectric material layers are alternately stacked.

Referring to FIG. 6 , the gate electrode GE may include a first metal pattern MEP1 and a second metal pattern MEP2 on the first metal pattern. The first metal pattern MEP1 may be provided on the gate insulating layer GI. For example, the gate insulating layer GI may be interposed between the first metal pattern MEP1 and the first channel pattern CH1 .

The first metal pattern MEP1 may include a metal nitride having a relatively high work function. In other words, the first metal pattern MEP1 may include a P-type work function metal. For example, the first metal pattern MEP1 may include titanium nitride (TiN), tantalum nitride (TaN), titanium oxynitride (TiON), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), and tungsten carbon nitride (WCN). ) or molybdenum nitride (MoN).

A second metal pattern MEP2 may be provided on the first metal pattern MEP1 . The second metal pattern MEP2 may include metal carbide having a relatively low work function. In other words, the second metal pattern MEP2 may include an N-type work function metal. The second metal pattern MEP2 may include metal carbide doped with (or containing) silicon and/or aluminum. For example, the second metal pattern MEP2 may include aluminum doped titanium carbide (TiAlC), aluminum doped tantalum carbide (TaAlC), aluminum doped vanadium carbide (VAIC), and silicon doped titanium carbide (TiSiC). , or silicon-doped tantalum carbide (TaSiC). As another example, the second metal pattern MEP2 may include titanium carbide (TiAlSiC) doped with aluminum and silicon, or tantalum carbide (TaAlSiC) doped with aluminum and silicon. As another example, the second metal pattern MEP2 may include titanium (TiAl) doped with aluminum.

In the second metal pattern MEP2 , the work function of the second metal pattern MEP2 may be adjusted by adjusting a doping concentration of silicon or aluminum as a dopant. For example, the concentration of impurities (silicon or aluminum) in the second metal pattern MEP2 may be 0.1 at% to 25 at%.

According to embodiments of the present invention, the first and second metal patterns MEP1 and MEP2 may be adjacent to the first channel pattern CH1 . The first and second metal patterns MEP1 and MEP2 may function as a work function metal for controlling a threshold voltage of a transistor. In other words, a desired threshold voltage may be achieved by adjusting the thickness and composition of each of the first and second metal patterns MEP1 and MEP2 .

Although not shown, the gate electrode GE on the second channel pattern CH2 may also include the first and second metal patterns MEP1 and MEP2 . However, the thickness and composition of each of the first and second metal patterns MEP1 and MEP2 of the gate electrode GE on the second channel pattern CH2 are the same as the above-described gate electrode GE on the first channel pattern CH1. ) may be different from the thickness and composition of each of the first and second metal patterns MEP1 and MEP2 .

A first interlayer insulating layer 110 may be provided on the substrate 100 . The first interlayer insulating layer 110 may cover the gate spacers GS and the first and second source/drain patterns SD1 and SD2 . A top surface of the first interlayer insulating layer 110 may be substantially coplanar with top surfaces of the gate capping patterns GP. A top surface of the first interlayer insulating layer 110 may be substantially coplanar with top surfaces of the gate cutting patterns CT.

A second interlayer insulating layer 120 covering the gate capping patterns GP and the gate cutting patterns CT may be provided on the first interlayer insulating layer 110 . A third interlayer insulating layer 130 may be provided on the second interlayer insulating layer 120 . A fourth interlayer insulating layer 140 may be provided on the third interlayer insulating layer 130 . For example, the first to fourth interlayer insulating layers 110 to 140 may include a silicon oxide layer.

A pair of separation structures DB facing each other in the second direction D2 may be provided on both sides of each of the first and second single height cells SHC1 and SHC2 . For example, the pair of separation structures DB may be provided on the first and second boundaries BD1 and BD2 of the first single height cell SHC1 , respectively. The separation structure DB may extend parallel to the gate electrodes GE in the first direction D1 . A pitch between the isolation structure DB and the gate electrode GE adjacent thereto may be the same as the first pitch.

The separation structure DB may extend into the first and second active patterns AP1 and AP2 through the first and second interlayer insulating layers 110 and 120 . The separation structure DB may pass through each of the first and second active patterns AP1 and AP2 . The isolation structure DB may electrically isolate an active region of each of the first and second single height cells SHC1 and SHC2 from an active region of another adjacent cell.

Active contacts AC may be provided through the first and second interlayer insulating layers 110 and 120 to be electrically connected to the first and second source/drain patterns SD1 and SD2 , respectively. Each of the active contacts AC may be provided between a pair of gate electrodes GE. In a plan view, each of the active contacts AC may have a bar shape or a line shape extending in the first direction D1 .

The active contact AC may be a self-aligned contact. In other words, the active contact AC may be formed in a self-aligned manner using the gate capping pattern GP and the gate spacer GS. For example, the active contact AC may cover at least a portion of a sidewall of the gate spacer GS. Although not shown, the active contact AC may partially cover the upper surface of the gate capping pattern GP.

The silicide patterns SC may be respectively interposed between the active contacts AC and the first and second source/drain patterns SD1 and SD2 . The active contacts AC may be electrically connected to the first and second source/drain patterns SD1 and SD2 through the silicide patterns SC, respectively. The silicide pattern SC may include metal-silicide, and for example, may include at least one of titanium-silicide, tantalum-silicide, tungsten-silicide, nickel-silicide, and cobalt-silicide. .

Referring back to FIG. 5C , the at least one active contact AC on the first single height cell SHC1 includes the first source/drain pattern SD1 of the first PMOSFET region PR1 and the first NMOSFET region NR1 . ) of the second source/drain patterns SD2 may be electrically connected to each other. The active contact AC extends from the second source/drain pattern SD2 of the first NMOSFET region NR1 to the first source/drain pattern SD1 of the first PMOSFET region PR1 in the first direction D1. can be extended The active contact AC may include a first body part BP1 on the first source/drain pattern SD1 and a second body part BP2 on the second source/drain pattern SD2 . The first body part BP1 may be connected to the upper surface of the first source/drain pattern SD1 through the silicide pattern SC, and the second body part BP2 may be connected to the second source/drain pattern SD1 through the silicide pattern SC. It may be connected to the upper surface of the drain pattern SD2 . The first active contact AC1 may further include a protrusion PRP interposed between the first body part BP1 and the second body part BP2 . The protrusion PRP may be provided on the device isolation layer ST between the first PMOSFET region PR1 and the first NMOSFET region NR1 .

The protrusion PRP may extend from the first body BP1 toward the device isolation layer ST along the inclined sidewall of the first source/drain pattern SD1 . The protrusion PRP may extend from the second body part BP2 toward the device isolation layer ST along the inclined sidewall of the second source/drain pattern SD2 . A bottom surface of the protrusion PRP may be lower than a bottom surface of each of the first body part BP1 and the second body part BP2. A bottom surface of the protrusion PRP may be positioned higher than the device isolation layer ST. In other words, the protrusion PRP may be spaced apart from the device isolation layer ST with the first interlayer insulating layer 110 interposed therebetween.

According to an embodiment of the present invention, the active contact AC is connected to the upper surface of the first source/drain pattern SD1 through the first body portion BP1 as well as the first source/drain pattern SD1 through the protrusion PRP. It may also be connected to the inclined sidewall of the drain pattern SD1 . In other words, the protrusion PRP may increase the contact area between the active contact AC and the first source/drain pattern SD1 . Accordingly, the resistance between the active contact AC and the first source/drain pattern SD1 may be reduced. Similarly, the protrusion PRP may reduce resistance between the active contact AC and the second source/drain pattern SD2 . As a result, the operating speed of the semiconductor device according to the embodiments of the present invention may be improved.

Gate contacts GC may be provided through the second interlayer insulating layer 120 and the gate capping pattern GP to be electrically connected to the gate electrodes GE, respectively. In a plan view, the gate contacts GC on the first single height cell SHC1 may be disposed to overlap the first PMOSFET region PR1 . In other words, the gate contacts GC on the first single height cell SHC1 may be provided on the first active pattern AP1 (refer to FIG. 5A ).

The gate contact GC may be freely disposed on the gate electrode GE without limitation of a position thereof. For example, the gate contacts GC on the second single height cell SHC2 may include a device isolation layer ST filling the second PMOSFET region PR2 , the second NMOSFET region NR2 , and the second trench TR2 . can be respectively disposed on the phase (see FIG. 4 ).

As an embodiment of the present invention, referring to FIGS. 5A and 5C , an upper portion of the active contact AC adjacent to the gate contact GC may be filled with the upper insulating pattern UIP. A bottom surface of the upper insulating pattern UIP may be lower than a bottom surface of the gate contact GC. In other words, the top surface of the active contact AC adjacent to the gate contact GC may descend lower than the bottom surface of the gate contact GC by the upper insulating pattern UIP. Accordingly, it is possible to prevent a problem in that the gate contact GC comes into contact with the active contact AC adjacent thereto and a short circuit occurs.

Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may include at least one of aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM may cover sidewalls and a bottom surface of the conductive pattern FM. The barrier pattern BM may include a metal layer/metal nitride layer. The metal layer may include at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may include at least one of a titanium nitride layer (TiN), a tantalum nitride layer (TaN), a tungsten nitride layer (WN), a nickel nitride layer (NiN), a cobalt nitride layer (CoN), and a platinum nitride layer (PtN).

A blocking pattern BLP may be interposed between the gate contact GC and the gate spacer GS. The blocking pattern BLP may directly contact the lower sidewall of the gate contact GC. The blocking pattern BLP may prevent the gate contact GC from extending beyond the gate spacer GS toward the active contact AC and/or the source/drain patterns SD1 and SD2 adjacent thereto. . The blocking pattern BLP may include a material having an etch selectivity to the gate spacer GS. For example, the blocking pattern BLP may include polysilicon, silicon oxide, or a combination thereof.

A first metal layer M1 may be provided in the third interlayer insulating layer 130 . For example, the first metal layer M1 may include a first power line M1_R1 , a second power line M1_R2 , a third power line M1_R3 , and first lines M1_I. Each of the interconnections M1_R1 , M1_R2 , M1_R3 , and M1_I of the first metal layer M1 may extend parallel to each other in the second direction D2 .

In detail, the first and second power lines M1_R1 and M1_R2 may be provided on the third and fourth boundaries BD3 and BD4 of the first single height cell SHC1 , respectively. The first power line M1_R1 may extend in the second direction D2 along the third boundary BD3 . The second power line M1_R2 may extend in the second direction D2 along the fourth boundary BD4 .

The first interconnections M1_I of the first metal layer M1 may be arranged in the first direction D1 at a second pitch. The second pitch may be smaller than the first pitch. A line width of each of the first lines M1_I may be smaller than a line width of each of the first to third power lines M1_R1 , M1_R2 , and M1_R3 .

The first metal layer M1 may further include first vias VI1 . The first vias VI1 may be respectively provided under the interconnections M1_R1 , M1_R2 , M1_R3 , and M1_I of the first metal layer M1 . The active contact AC and the wiring of the first metal layer M1 may be electrically connected to each other through the first via VI1 . The gate contact GC and the wiring of the first metal layer M1 may be electrically connected to each other through the first via VI1 .

The wiring of the first metal layer M1 and the first via VI1 below it may be formed through separate processes. In other words, each of the wiring and the first via VI1 of the first metal layer M1 may be formed by a single damascene process. The semiconductor device according to the present embodiment may be formed using a process of less than 20 nm.

A second metal layer M2 may be provided in the fourth interlayer insulating layer 140 . The second metal layer M2 may include a plurality of second interconnections M2_I. Each of the second interconnections M2_I of the second metal layer M2 may have a line shape or a bar shape extending in the first direction D1 . In other words, the second interconnections M2_I may extend parallel to each other in the first direction D1 .

The second metal layer M2 may further include second vias VI2 respectively provided under the second interconnections M2_I. The wiring of the first metal layer M1 and the wiring of the second metal layer M2 may be electrically connected to each other through the second via VI2 . The wiring of the second metal layer M2 and the second via VI2 below it may be formed together by a dual damascene process.

The wiring of the first metal layer M1 and the wiring of the second metal layer M2 may include the same or different conductive materials. For example, the wiring of the first metal layer M1 and the wiring of the second metal layer M2 may include at least one metal material selected from aluminum, copper, tungsten, molybdenum, and cobalt. Although not shown, metal layers (eg, M3, M4, M5...) stacked on the fourth interlayer insulating layer 140 may be additionally disposed. Each of the stacked metal layers may include wirings for routing between cells.

The transistor of the second region RG2 will first be described in detail with reference to FIGS. 4 and 5E . The second region RG2 may include, for example, a third PMOSFET region PR3 and a fourth PMOSFET region PR4 . A third active pattern AP3 may be provided on each of the third and fourth PMOSFET regions PR3 and PR4 .

Third source/drain patterns SD3 may be provided on the third active pattern AP3 . The third source/drain patterns SD3 may be impurity regions of the first conductivity type (eg, p-type). A third channel pattern CH3 may be interposed between the pair of third source/drain patterns SD3 . A width of the third channel pattern CH3 in the second direction D2 may be greater than a width of each of the first and second channel patterns CH1 and CH2 described above.

A long gate electrode LGE may be provided that crosses the third active pattern AP3 and extends in the first direction D1 . A width of the long gate electrode LGE in the second direction D2 may be greater than a width of the gate electrode GE on the first region RG1 described above. A gate insulating layer GI may be interposed between the long gate electrode LGE and the third active pattern AP3 .

Referring to FIG. 7 , the long gate electrode LGE includes a first metal pattern MEP1 , a second metal pattern MEP2 on the first metal pattern, and a third metal pattern MEP3 on the second metal pattern MEP2 . may include The first and second metal patterns MEP1 and MEP2 of the long gate electrode LGE may be the same as or similar to the first and second metal patterns MEP1 and MEP2 of the gate electrode GE described above. .

The resistance of the third metal pattern MEP3 may be lower than that of the first and second metal patterns MEP1 and MEP2 . For example, the third metal pattern MEP3 may include at least one low-resistance metal selected from among aluminum (Al), tungsten (W), titanium (Ti), and tantalum (Ta). In another embodiment of the present invention, the third metal pattern MEP3 may be omitted.

A blocking pattern BLP may be provided on the long gate electrode LGE. The blocking pattern BLP may be interposed between the gate spacer GS and the gate capping pattern GP.

Active contacts AC may be provided through the first and second interlayer insulating layers 110 and 120 to be electrically connected to the third source/drain patterns SD3 , respectively. At least one gate contact GC may be provided through the second interlayer insulating layer 120 and the gate capping pattern GP to be electrically connected to the long gate electrode LGE. A first metal layer M1 and a second metal layer M2 may be provided on the active contacts AC and the gate contact GC.

The structures of the gate electrode GE, the gate spacer GS, the blocking pattern BLP, and the gate contact GC according to embodiments of the present invention will be described in more detail with reference to FIG. 6 . The gate spacer GS may include a first spacer GS1 and a second spacer GS2 arranged side by side in the second direction D2 . The first spacer GS1 may have a third upper surface TOS3 , and the second spacer GS2 may have a second upper surface TOS2 . The second upper surface TOS2 may be higher than the third upper surface TOS3 . The third upper surface TOS3 may be positioned at substantially the same height as the upper surface of the gate electrode GE or may be lower than the upper surface of the gate electrode GE.

The bottom surface BOS2 of the gate contact GC may contact the top surface of the gate electrode GE. The bottom surface BOS2 of the gate contact GC may be positioned substantially at the same height or higher than the third top surface TOS3 of the first spacer GS1 .

A blocking pattern BLP may be interposed between the gate contact GC and the second spacer GS2 . The blocking pattern BLP may include a pair of blocking patterns BLP, and the pair of blocking patterns BLP may be provided on both lower sidewalls of the gate contact GC, respectively.

The blocking pattern BLP may extend in a vertical direction (ie, the third direction D3 ) from the third upper surface TOS3 of the first spacer GS1 . The blocking pattern BLP may extend vertically from the third upper surface TOS3 along the inner wall ISW1 of the second spacer GS2 . The bottom surface BOS1 of the blocking pattern BLP may directly contact the third top surface TOS3 . The blocking pattern BLP may have a first upper surface TOS1 . The first upper surface TOS1 may be lower than the second upper surface TOS2 of the second spacer GS2 . The bottom surface BOS1 of the blocking pattern BLP may be located at the same height as or lower than the bottom surface BOS2 of the gate contact GC.

The thickness T1 of the blocking pattern BLP in the second direction D2 may decrease in the third direction D3 . In other words, the thickness of the blocking pattern BLP may decrease in a direction from the first spacer GS1 toward the gate capping pattern GP.

The maximum thickness of the blocking pattern BLP may be the first thickness T1 . The first thickness T1 may be 1 nm to 4 nm. The first spacer GS1 may have a second thickness T2 in the second direction D2 . The second thickness T2 may be greater than the first thickness T1 .

A gate capping pattern GP may be disposed on the gate electrode GE and the gate spacer GS. The gate capping pattern GP may directly cover the first upper surface TOS1 of the blocking pattern BLP and the second upper surface TOS2 of the second spacer GS2 .

The structures of the long gate electrode LGE, the gate spacer GS, and the blocking pattern BLP according to embodiments of the present invention will be described in more detail with reference to FIG. 7 . The gate spacer GS on the second region RG2 may include a first spacer GS1 and a second spacer GS2 arranged side by side in the second direction D2 . The top surface of the first spacer GS1 , the top surface of the second spacer GS2 , and the top surface of the gate capping pattern GP may be coplanar with each other.

A blocking pattern BLP may be interposed between the inner wall ISW2 of the first spacer GS1 and the gate capping pattern GP. The blocking pattern BLP on the second region RG2 may be formed together with the blocking pattern BLP on the first region RG1 .

The blocking pattern BLP may extend vertically from the top surface of the long gate electrode LGE (or the top surface of the gate insulating layer GI) along the inner wall ISW2 of the first spacer GS1 . The upper surface TOS1 of the blocking pattern BLP may be covered by the gate capping pattern GP.

8 is an enlarged cross-sectional view of region M of FIG. 5A according to a comparative example of the present invention. Referring to FIG. 8 , according to the comparative example of the present invention, the blocking pattern BLP may be omitted. When the blocking pattern BLP is omitted, the extension EXP may be formed in the gate contact GC. Specifically, if over-etching occurs while forming the gate contact GC, the gate spacer GS may be omitted to form the extension EXP. The extension EXP may extend downward along the sidewall of the gate electrode GE to contact the active contact AC or the source/drain patterns SD1 and SD2 . For example, the short region STR in which the extension EXP of the gate contact GC and the active contact AC contact each other may be formed. The short region STR is a process defect and may seriously deteriorate the reliability of the semiconductor device.

On the other hand, according to the embodiment of the present invention of FIG. 6 , the blocking pattern BLP may include polysilicon, and thus, in the process of forming the gate contact GC, the blocking pattern BLP is formed between the first and second spacers ( It may have stronger etching resistance than GS1 and GS2). Accordingly, the blocking pattern BLP may prevent the aforementioned extension EXP from being formed in the gate contact GC. In other words, the pair of blocking patterns BLP may guide the gate contact GC not to depart from them, so that the gate contact GC may contact only the upper surface of the gate electrode GE. As a result, the blocking pattern BLP of the present invention may prevent a short circuit between the gate contact GC and the active contact AC and improve the reliability of the semiconductor device.

Referring back to FIG. 5D , the gate electrode GE may include a vertical extension portion VEP extending in the third direction D3 along the sidewall of the gate cutting pattern CT. According to embodiments of the present invention, since the gate electrode GE is formed after the gate cutting pattern CT is formed, it extends vertically along the sidewall of the gate cutting pattern CT while the gate electrode GE is formed. A vertical extension VEP may be formed together. The vertical extension VEP may be exposed over the gate capping pattern GP, and the exposed vertical extension VEP may cause a short-circuit defect in contact with the adjacent active contact AC.

Meanwhile, according to an embodiment of the present invention, the blocking pattern BLP may be provided on the vertical extension portion VEP of the gate electrode GE. The blocking pattern BLP may cover an upper surface of the vertical extension VEP and an upper sidewall of the gate cutting pattern CT. Since the blocking pattern BLP is provided on the upper surface of the vertical extension VEP, it is possible to prevent the vertical extension VEP from being exposed. As a result, the blocking pattern BLP according to the present invention may prevent a short circuit between the vertical extension VEP of the gate electrode GE and the adjacent active contact AC, thereby improving the reliability of the semiconductor device.

9A and 9B are enlarged cross-sectional views of region M of FIG. 5A according to another exemplary embodiment of the present invention. In the present embodiments, detailed descriptions of technical features overlapping with those previously described with reference to FIGS. 4 and 5A to 5E will be omitted, and differences will be described in detail.

Referring to FIG. 9A , the bottom surface BOS1 of the blocking pattern BLP may be lower than the bottom surface BOS2 of the gate contact GC. As the bottom surface BOS1 of the blocking pattern BLP is lowered, the upper surface TOS3 of the first spacer GS1 may be lowered together. The top surface TOS3 of the first spacer GS1 may be lower than the top surface of the gate electrode GE.

The blocking pattern BLP may be interposed between the gate contact GC and the second spacer GS2 as well as between the gate electrode GE and the second spacer GS2 . The blocking pattern BLP may be interposed between the gate electrode GE and the active contact AC.

According to the present exemplary embodiment, since the blocking pattern BLP is also interposed between the gate electrode GE and the active contact AC, the gate contact GC has an extension EXP in contact with the active contact AC; see FIG. 8 . ) can be more reliably prevented from forming. As a result, the reliability of the semiconductor device may be further improved.

Referring to FIG. 9B , the bottom surface BOS1 of the blocking pattern BLP may be higher than the bottom surface BOS2 of the gate contact GC. The bottom surface BOS1 of the blocking pattern BLP may be higher than the top surface of the gate electrode GE. As the bottom surface BOS1 of the blocking pattern BLP increases, the top surface TOS3 of the first spacer GS1 may also increase. The top surface TOS3 of the first spacer GS1 may be higher than the top surface of the gate electrode GE.

The first spacer GS1 may be positioned between the gate contact GC and the active contact AC. Since the first spacer GS1 including the low-k material is disposed between the gate contact GC and the active contact AC, parasitic capacitance generated between the gate contact GC and the active contact AC may be reduced. have. As a result, electrical characteristics of the semiconductor device may be improved.

10, 12, 14, and 16 are plan views for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention. 11A, 13A, 15A, and 17A are cross-sectional views taken along line A-A' of FIGS. 10, 12, 14 and 16, respectively. 11B, 13B, 15B, and 17B are cross-sectional views taken along line B-B' of FIGS. 10, 12, 14 and 16, respectively. 11C, 13C, 15C, and 17C are cross-sectional views taken along line C-C' of FIGS. 10, 12, 14 and 16, respectively. 11D, 13D, 15D, and 17D are cross-sectional views taken along line D-D' of FIGS. 10, 12, 14 and 16, respectively. 13E, 15E, and 17E are cross-sectional views taken along line E-E' of FIGS. 12, 14, and 16, respectively.

10 and 11A to 11D , a substrate 100 including a first region RG1 and a second region RG2 may be provided. The first region RG1 may include a first PMOSFET region PR1 , a second PMOSFET region PR2 , a first NMOSFET region NR1 , and a second NMOSFET region NR2 . The first NMOSFET region NR1 and the first PMOSFET region PR1 may define a first single height cell SHC1 , and the second NMOSFET region NR2 and the second PMOSFET region PR2 may define a second single height cell SHC1 . A height cell SHC2 may be defined. The second region RG2 may include a third PMOSFET region PR3 and a fourth PMOSFET region PR4 .

By patterning the substrate 100 , first to third active patterns AP1 , AP2 , and AP3 may be formed. First active patterns AP1 may be formed on each of the first and second PMOSFET regions PR1 and PR2 . Second active patterns AP2 may be formed on each of the first and second NMOSFET regions NR1 and NR2 . Third active patterns AP3 may be formed on each of the third and fourth PMOSFET regions PR3 and PR4 .

A device isolation layer ST may be formed on the substrate 100 . The device isolation layer ST may include an insulating material such as a silicon oxide layer. The device isolation layer ST may be recessed until an upper portion of each of the first to third active patterns AP1 , AP2 , and AP3 is exposed. Accordingly, an upper portion of each of the first to third active patterns AP1 , AP2 , and AP3 may vertically protrude above the device isolation layer ST.

Sacrificial patterns PP crossing the first and second active patterns AP1 and AP2 may be formed. A long sacrificial pattern LPP crossing the third active pattern AP3 may be formed. Each of the sacrificial patterns PP and the long sacrificial pattern LPP may be formed in a line shape or a bar shape extending in the first direction D1 .

Specifically, forming the sacrificial patterns PP and the long sacrificial pattern LPP includes forming the first sacrificial layer on the entire surface of the substrate 100 and forming the mask patterns MA on the first sacrificial layer. and patterning the first sacrificial layer using the mask patterns MA as an etch mask. The first sacrificial layer may include polysilicon.

According to an embodiment of the present invention, the patterning process for forming the sacrificial patterns PP may include a lithography process using Extreme Ultraviolet (EUV). In the present specification, EUV may refer to ultraviolet rays having a wavelength of 4 nm and 124 nm, specifically, a wavelength of 4 nm and 20 nm, and more specifically, a wavelength of 13.5 nm. EUV may refer to light having an energy of 6.21 eV to 124 eV, specifically, 90 eV to 95 eV.

The lithography process using EUV may include exposure and development processes using EUV irradiated onto the photoresist layer. For example, the photoresist layer may be an organic photoresist containing an organic polymer such as polyhydroxystyrene. The organic photoresist may further include a photosensitive compound that responds to EUV. The organic photoresist may further include a material having a high EUV absorption rate, for example, an organometallic material, an iodine-containing material, or a fluorine-containing material. . As another example, the photoresist layer may be an inorganic photoresist containing an inorganic material such as tin oxide.

The photoresist layer may be formed to a relatively thin thickness. Photoresist patterns may be formed by developing the photoresist layer exposed to EUV. In a plan view, the photoresist patterns may have a line shape extending in one direction, an island shape, a zigzag shape, a honeycomb shape, or a circular shape, but are not limited thereto.

The above-described hard mask patterns MP may be formed by patterning the photoresist patterns as an etch mask and one or more mask layers stacked thereunder. By patterning the sacrificial layer as a target layer using the hard mask patterns MP as an etch mask, desired patterns, that is, sacrificial patterns PP, may be formed on the wafer.

As a comparative example of the present invention, a multi-patterning technique (MPT) using two or more photomasks is required to form patterns having a fine pitch on a wafer. On the other hand, when the EUV lithography process according to the embodiment of the present invention is performed, the sacrificial patterns PP having a fine pitch may be formed using a single photomask.

For example, the minimum pitch between the sacrificial patterns PP implemented by the EUV lithography process of the present embodiment may be 45 nm or less. That is, by performing the EUV lithography process, sophisticated and fine sacrificial patterns PP may be implemented without a multi-patterning technique.

According to embodiments of the present invention, the above-described lithography process using EUV may be used in the patterning process for forming the above-described first and second active patterns AP1 and AP2 as well as the sacrificial patterns PP. and is not particularly limited.

A pair of gate spacers GS may be formed on both sidewalls of each of the sacrificial patterns PP and the long sacrificial pattern LPP. Forming the gate spacers GS may include conformally forming a gate spacer layer on the entire surface of the substrate 100 and anisotropically etching the gate spacer layer. The gate spacer layer may include at least one of SiCN, SiOCN, and SiN.

The gate spacer GS may have a multilayer structure including the first spacer GS1 and the second spacer GS2 as described above with reference to FIGS. 6 and 7 . The first spacer GS1 may be formed of SiOCN, which is a low-k material. The second spacer GS2 may be formed of SiN having excellent etch resistance. The first spacer GS1 may be formed to be thicker than the second spacer GS2 .

12 and 13A to 13E , first source/drain patterns SD1 may be formed on each of the first active patterns AP1 . A pair of first source/drain patterns SD1 may be formed on both sides of each of the sacrificial patterns PP.

In detail, the upper portions of the first active pattern AP1 may be etched using the mask patterns MA and the gate spacers GS as an etch mask to form first recesses. While the upper portion of the first active pattern AP1 is being etched, the device isolation layer ST between the first active patterns AP1 may be recessed (refer to FIG. 13C ).

A first source/drain pattern SD1 may be formed by performing a selective epitaxial growth process using an inner wall of the first recess of the first active pattern AP1 as a seed layer. As the first source/drain patterns SD1 are formed, a first channel pattern CH1 may be defined between the pair of first source/drain patterns SD1 . For example, the selective epitaxial growth process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process. The first source/drain patterns SD1 may include a semiconductor element (eg, SiGe) having a lattice constant greater than a lattice constant of the semiconductor element of the substrate 100 . Each of the first source/drain patterns SD1 may be formed of multi-layered semiconductor layers.

For example, impurities may be implanted in-situ during a selective epitaxial growth process for forming the first source/drain patterns SD1 . As another example, after the first source/drain patterns SD1 are formed, impurities may be implanted into the first source/drain patterns SD1 . The first source/drain patterns SD1 may be doped to have a first conductivity type (eg, p-type).

Second source/drain patterns SD2 may be formed on the second active pattern AP2 . A pair of second source/drain patterns SD2 may be formed on both sides of each of the sacrificial patterns PP.

In detail, an upper portion of the second active pattern AP2 may be etched using the mask patterns MA and the gate spacers GS as an etch mask to form second recesses. A second source/drain pattern SD2 may be formed by performing a selective epitaxial growth process using an inner wall of the second recess of the second active pattern AP2 as a seed layer. As the second source/drain patterns SD2 are formed, a second channel pattern CH2 may be defined between the pair of second source/drain patterns SD2 . For example, the second source/drain patterns SD2 may include the same semiconductor element (eg, Si) as the substrate 100 . The second source/drain patterns SD2 may be doped to have a second conductivity type (eg, n-type).

The first source/drain patterns SD1 and the second source/drain patterns SD2 may be sequentially formed through different processes. In other words, the first source/drain patterns SD1 and the second source/drain patterns SD2 may not be formed at the same time.

Third source/drain patterns SD3 may be formed on the third active pattern AP3 . A pair of third source/drain patterns SD3 may be respectively formed on both sides of the long sacrificial pattern LPP. For example, the third source/drain patterns SD3 may be formed together with the above-described first source/drain patterns SD1 .

14 and 15A to 15E , the first interlayer insulating layer 110 covering the first and second source/drain patterns SD1 and SD2, the mask patterns MA, and the gate spacers GS. can be formed. For example, the first interlayer insulating layer 110 may include a silicon oxide layer.

The first interlayer insulating layer 110 may be planarized until top surfaces of the sacrificial patterns PP and the long sacrificial pattern LPP are exposed. The planarization of the first interlayer insulating layer 110 may be performed using an etch back process or a chemical mechanical polishing (CMP) process. During the planarization process, all of the mask patterns MA may be removed. As a result, a top surface of the first interlayer insulating layer 110 may be coplanar with top surfaces of the sacrificial patterns PP, a top surface of the long sacrificial pattern LPP, and top surfaces of the gate spacers GS.

Gate cutting patterns CT may be formed on a boundary parallel to each of the first and second single height cells SHC1 and SHC2 in the second direction D2 . Specifically, a mask layer including an opening defining a position where the gate cutting patterns CT is to be formed may be formed using a photolithography process. The sacrificial pattern PP exposed by the opening may be selectively removed using an etching process. The gate cutting pattern CT may be formed by filling the region from which the sacrificial pattern PP is removed with an insulating material. Meanwhile, the sacrificial patterns PP covered by the mask layer may remain without being removed. Subsequently, the mask film may be selectively removed.

16 and 17A to 17E , the remaining sacrificial patterns PP may be replaced with the gate electrodes GE. The long sacrificial pattern LPP may be replaced with the long gate electrode LGE. Specifically, the exposed sacrificial pattern PP may be selectively removed. An empty space may be formed by removing the sacrificial pattern PP. A gate insulating layer GI and a gate electrode GE may be formed in the empty space. The long gate electrode LGE may also be formed in the same manner as the gate electrode GE.

18A, 19A, 20A, 21A, 22A, and 23A are enlarged views for explaining a method in which region M of FIG. 17A is formed. 18B, 19B, 20B, 21B, 22B, and 23B are enlarged views for explaining a method in which the N region of FIG. 17E is formed.

18A and 18B , the first empty space ETS1 may be defined by selectively removing the sacrificial pattern PP. The second empty space ETS2 may be defined by selectively removing the long sacrificial pattern LPP.

A gate insulating layer GI, a first metal pattern MEP1, and a second metal pattern MEP2 may be sequentially formed in each of the first and second empty spaces ETS1 and ETS2. A third metal pattern MEP3 may be further formed in the second empty space ETS2 . The first to third metal patterns MEP1 , MEP2 , and MEP3 may be formed using an atomic layer deposition process, a chemical vapor deposition process, and/or a physical vapor deposition process.

The gate insulating layer GI may include a silicon oxide layer, a high-k layer, or a combination thereof. The first metal pattern MEP1 may include a metal nitride having a relatively high work function. The second metal pattern MEP2 may include metal carbide having a relatively low work function. The third metal pattern MEP3 may include a low-resistance metal.

19A and 19B , the gate insulating layer GI, the first metal pattern MEP1, and the second metal pattern MEP2 in each of the first and second empty spaces ETS1 and ETS2 are selectively formed. can be recessed. However, an upper portion of the third metal pattern MEP3 may be slightly recessed.

Since the width of the second empty space ETS2 is greater than the width of the first empty space ETS1 , the first and second metal patterns MEP1 and MEP2 in the second empty space ETS2 are formed in the first empty space ETS2 . More recesses than the first and second metal patterns MEP1 and MEP2 in the space ETS1 may be formed.

20A and 20B , a mask layer MAL may be formed to fill the second empty space ETS2 and expose the first empty space ETS1 . The first spacer GS1 on the first region RG1 exposed by the mask layer MAL may be selectively recessed. A top surface of the first spacer GS1 may be positioned substantially at the same height or lower than the top surfaces of the first and second metal patterns MEP1 and MEP2 . While the first spacer GS1 is recessed, the second spacer GS2 on the first region RG1 may also be slightly recessed.

Meanwhile, the first and second spacers GS1 and GS2 on the second region RG2 may be protected by the mask layer MAL and remain without being recessed.

21A and 21B , the mask layer MAL may be selectively removed. A blocking layer BLL may be conformally formed in each of the first and second empty spaces ETS1 and ETS2 . The blocking layer BLL may be formed using an atomic layer deposition process or a chemical vapor deposition process. The blocking layer BLL may be formed to a thickness of 1 nm to 4 nm. The blocking layer BLL may include polysilicon.

22A and 22B , a spacer-shaped blocking pattern BLP may be formed by performing a chamfering process and/or an anisotropic etching process on the blocking layer BLL. In the first empty space ETS1 , the blocking pattern BLP may be formed to extend vertically from the top surface of the first spacer GS1 along the inner wall of the second spacer GS2 . In the second empty space ETS2 , the blocking pattern BLP may be formed to extend vertically from the top surface of the first metal pattern MEP1 along the inner wall of the first spacer GS1 .

23A and 23B , a gate capping pattern GP may be formed in each of the first and second empty spaces ETS1 and ETS2 . In the first empty space ETS1 , the gate capping pattern GP may be formed to cover the upper surface of the second spacer GS2 and the upper surface of the blocking pattern BLP. In the second empty space ETS2 , the gate capping pattern GP may be formed to cover the upper surface of the blocking pattern BLP and the third metal pattern MEP3 .

Referring again to Figures 4 and 5a to 5e,

A second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110 . The second interlayer insulating layer 120 may include a silicon oxide layer. A pair of separation structures DB may be respectively formed on both sides of the first single height cell SHC1 . The isolation structures DB may be formed to overlap the gate electrodes GE respectively formed on both sides of the first single height cell SHC1 . Specifically, the formation of the isolation structures DB penetrates the first and second interlayer insulating layers 110 and 120 and the gate electrode GE to form the first and second active patterns AP1 and AP2 . It may include forming a hole extending inward, and filling the hole with an insulating film.

Active contacts AC electrically connected to the first to third source/drain patterns SD1 , SD2 , and SD3 may be formed through the second interlayer insulating layer 120 and the first interlayer insulating layer 110 . have. An upper insulating pattern UIP may be formed by replacing a portion of an upper portion of each of the active contacts AC with an insulating material. A gate contact GC electrically connected to each of the gate electrode GE and the long gate electrode LGE may be formed through the second interlayer insulating layer 120 and the gate capping pattern GP.

While forming the gate contact GC on the gate electrode GE, as described above with reference to FIG. 8 , a problem in which the extension EXP is formed by over-etching may occur. However, according to embodiments of the present invention, the pair of blocking patterns BLP made of polysilicon may prevent a defect in which the extension portion EXP is formed in the gate contact GC. Accordingly, the manufacturing method according to the present invention can prevent a short circuit between the gate contact GC and the source/drain patterns SD1 and SD2 from occurring and improve device reliability.

A third interlayer insulating layer 130 may be formed on the second interlayer insulating layer 120 . A first metal layer M1 may be formed in the third interlayer insulating layer 130 . Forming the first metal layer M1 may include forming the first power wiring M1_R1, the second power wiring M1_R2, the third power wiring M1_R3, and the first wirings M1_I. have.

A fourth interlayer insulating layer 140 may be formed on the first metal layer M1 . A second metal layer M2 may be formed in the fourth interlayer insulating layer 140 . Forming the second metal layer M2 may include forming the second interconnections M2_I. For example, the second interconnections M2_I may be formed through a dual damascene process.

According to an embodiment of the present invention, forming the wirings in the first metal layer M1 and/or the second metal layer M2 may include a lithography process using EUV. A detailed description of the EUV lithography used in the wiring forming process, that is, the BEOL process, may be substantially the same as that described in the method of forming the sacrificial patterns PP. For example, the minimum pitch between the first interconnections M1_I implemented by the EUV lithography process of the present embodiment may be 45 nm or less.

24A to 24E are for explaining a semiconductor device according to embodiments of the present invention, and are, respectively, lines A-A', B-B', C-C', D-D' and They are cross-sectional views taken along line E-E'. In the present embodiment, detailed descriptions of technical features overlapping with those previously described with reference to FIGS. 4 and 5A to 5E will be omitted, and differences will be described in detail.

4 and 24A to 24E , the device isolation layer ST defines a first active pattern AP1 , a second active pattern AP2 , and a third active pattern AP3 on the substrate 100 . can do. The first active pattern AP1 may be defined on each of the first PMOSFET region PR1 and the second PMOSFET region PR2 , and the second active pattern AP2 includes each of the first NMOSFET region NR1 and It may be defined on the second NMOSFET region NR2 , and the third active pattern AP3 may be defined on each of the third PMOSFET region PR3 and the fourth PMOSFET region PR4 .

The first active pattern AP1 may include a first channel pattern CH1 thereon. The second active pattern AP2 may include a second channel pattern CH2 on the second active pattern AP2 . The third active pattern AP3 may include a third channel pattern CH3 disposed thereon.

Each of the first to third channel patterns CH1 , CH2 , and CH3 may include a first semiconductor pattern SP1 , a second semiconductor pattern SP2 , and a third semiconductor pattern SP3 sequentially stacked. . The first to third semiconductor patterns SP1 , SP2 , and SP3 may be spaced apart from each other in a vertical direction (ie, the third direction D3 ). Since the first to third semiconductor patterns SP1 , SP2 , and SP3 of the third channel pattern CH3 have a relatively long length in the second direction D2 , they may be bent upward or downward.

Each of the first to third semiconductor patterns SP1 , SP2 , and SP3 may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). Preferably, each of the first to third semiconductor patterns SP1 , SP2 , and SP3 may include crystalline silicon.

The first active pattern AP1 may further include first source/drain patterns SD1 . The stacked first to third semiconductor patterns SP1 , SP2 , and SP3 of the first channel pattern CH1 may be interposed between a pair of adjacent first source/drain patterns SD1 . The stacked first to third semiconductor patterns SP1 , SP2 , and SP3 may connect a pair of adjacent first source/drain patterns SD1 to each other.

The second active pattern AP2 may further include second source/drain patterns SD2 . The stacked first to third semiconductor patterns SP1 , SP2 , and SP3 of the second channel pattern CH2 may be interposed between a pair of adjacent second source/drain patterns SD2 . The stacked first to third semiconductor patterns SP1 , SP2 , and SP3 may connect a pair of adjacent second source/drain patterns SD2 to each other.

The third active pattern AP3 may further include third source/drain patterns SD3 . The stacked first to third semiconductor patterns SP1 , SP2 , and SP3 of the third channel pattern CH3 may be interposed between a pair of third source/drain patterns SD3 adjacent to each other. The stacked first to third semiconductor patterns SP1 , SP2 , and SP3 may connect a pair of adjacent third source/drain patterns SD3 to each other.

Gate electrodes GE crossing the first and second channel patterns CH1 and CH2 and extending in the first direction D1 may be provided. The gate electrode GE may vertically overlap the first and second channel patterns CH1 and CH2. A pair of gate spacers GS may be disposed on both sidewalls of the gate electrode GE. A gate capping pattern GP may be provided on the gate electrode GE. A long gate electrode LGE may be provided that crosses the third channel pattern CH3 and extends in the first direction D1 .

Referring back to FIG. 24D , the gate electrode GE may surround the first to third semiconductor patterns SP1 , SP2 , and SP3 of each of the first and second channel patterns CH1 and CH2 . The transistor according to the present embodiment may be a three-dimensional field effect transistor (eg, MBCFET or GAAFET) in which the gate electrode GE surrounds the channels CH1 and CH2 three-dimensionally. In detail, each of the first to third semiconductor patterns SP1 , SP2 , and SP3 may include a second top surface TS2 , second sidewalls SW2 facing each other, and a bottom surface BS. The gate electrode GE may cover the second top surface TS2 , the second sidewalls SW2 , and the bottom surface BS. A gate insulating layer GI may be provided between each of the first to third semiconductor patterns SP1 , SP2 , and SP3 and the gate electrode GE. The gate insulating layer GI may surround each of the first and second channel patterns CH1 and CH2.

An inner spacer IP may be interposed between the gate insulating layer GI and the second source/drain pattern SD2 in the first and second NMOSFET regions NR1 and NR2 . The gate electrode GE may be spaced apart from the second source/drain pattern SD2 by the gate insulating layer GI and the inner spacer IP. On the other hand, in the first and second PMOSFET regions PR1 and PR2 , the inner spacer IP may be omitted.

According to embodiments of the present invention, a pair of blocking patterns BLP may be provided on each of the gate electrode GE and the long gate electrode LGE. The pair of blocking patterns BLP may prevent the gate contact GC from extending beyond the gate spacer GS.

A first interlayer insulating layer 110 and a second interlayer insulating layer 120 may be provided on the entire surface of the substrate 100 . Active contacts AC may be provided through the first and second interlayer insulating layers 110 and 120 and respectively connected to the first and second source/drain patterns SD1 and SD2 . Gate contacts GC may be provided through the second interlayer insulating layer 120 and the gate capping pattern GP and respectively connected to the gate electrode GE and the long gate electrode LGE. Detailed descriptions of the active contacts AC and the gate contacts GC may be substantially the same as those described with reference to FIGS. 4 and 5A to 5E .

A third interlayer insulating layer 130 may be provided on the second interlayer insulating layer 120 . A fourth interlayer insulating layer 140 may be provided on the third interlayer insulating layer 130 . A first metal layer M1 may be provided in the third interlayer insulating layer 130 . A second metal layer M2 may be provided in the fourth interlayer insulating layer 140 . Detailed descriptions of the first metal layer M1 and the second metal layer M2 may be substantially the same as those described above with reference to FIGS. 4 and 5A to 5E .

As described above, embodiments of the present invention have been described with reference to the accompanying drawings, but the present invention may be embodied in other specific forms without changing the technical spirit or essential features thereof. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims (20)

a first active pattern on a substrate, the first active pattern including a pair of first source/drain patterns and a first channel pattern therebetween;
a gate electrode on the first channel pattern;
a first gate spacer on a sidewall of the gate electrode, the first gate spacer comprising a first spacer and a second spacer, wherein an upper surface of the first spacer is lower than an upper surface of the second spacer;
a first blocking pattern on the first spacer; and
a gate contact connected to the gate electrode;
The first blocking pattern is interposed between the gate contact and the second spacer. According to claim 1,
The first blocking pattern extends vertically from the top surface of the first spacer along an inner wall of the second spacer. According to claim 1,
A bottom surface of the first blocking pattern is positioned at the same height or lower than a bottom surface of the gate contact. According to claim 1,
The first blocking pattern directly covers a sidewall of the gate contact. According to claim 1,
Further comprising an active contact connected to at least one of the first source / drain patterns,
The first blocking pattern is disposed between the gate contact and the active contact. According to claim 1,
The first spacer comprises a low-k material containing Si,
The second spacer comprises an insulating material containing Si,
The first blocking pattern is a semiconductor device including polysilicon. According to claim 1,
Further comprising a gate cutting pattern penetrating the gate electrode,
The gate electrode includes a vertical extension extending vertically along a sidewall of the gate cutting pattern,
The first blocking pattern is a semiconductor device provided on the vertical extension. According to claim 1,
Further comprising a gate capping pattern on the gate electrode,
The gate capping pattern may cover the upper surface of the second spacer and the upper surface of the first blocking pattern. According to claim 1,
The first blocking pattern has a thickness of 1 nm to 4 nm. According to claim 1,
A second active pattern on the substrate and the second active pattern include a pair of second source/drain patterns and a second channel pattern therebetween, and the length of the second channel pattern is equal to that of the first channel pattern. longer than the length;
a long gate electrode on the second channel pattern;
a second gate spacer on a sidewall of the long gate electrode;
a gate capping pattern on the long gate electrode; and
A semiconductor device further comprising a second blocking pattern between the gate capping pattern and the second gate spacer. an active pattern on a substrate, the active pattern including a pair of source/drain patterns and a channel pattern therebetween;
a gate electrode on the channel pattern;
a gate spacer on a sidewall of the gate electrode;
a gate capping pattern on the gate contact;
a gate contact passing through the gate capping pattern and connecting to the gate electrode; and
a blocking pattern between the gate contact and the gate spacer;
the blocking pattern extends along sidewalls of the gate contact and guides the gate contact not to cross the gate spacer;
The blocking pattern may include a material having an etch selectivity to the gate spacer. 12. The method of claim 11,
The gate spacer includes a first spacer and a second spacer,
The upper surface of the first spacer is lower than the upper surface of the second spacer,
The blocking pattern extends vertically from the top surface of the first spacer along an inner wall of the second spacer. 12. The method of claim 11,
The gate capping pattern may cover an upper surface of the gate spacer and an upper surface of the blocking pattern. 12. The method of claim 11,
Further comprising a gate cutting pattern penetrating the gate electrode,
The gate electrode includes a vertical extension extending vertically along a sidewall of the gate cutting pattern,
The blocking pattern is a semiconductor device provided on the vertical extension. 12. The method of claim 11,
Further comprising an active contact connected to at least one of the source/drain patterns,
The blocking pattern is disposed between the gate contact and the active contact. a substrate comprising a PMOSFET region and an NMOSFET region spaced apart from each other in a first direction;
a first active pattern on the PMOSFET region and a second active pattern on the NMOSFET region;
a device isolation layer covering lower sidewalls of the first and second active patterns, an upper portion of each of the first and second active patterns protrude above the device isolation layer;
a gate electrode crossing the first and second active patterns and extending in the first direction;
A first source/drain pattern and a second source/drain pattern provided on the upper portions of the first and second active patterns, respectively, and each of the first and second source/drain patterns are adjacent to one side of the gate electrode do;
a gate insulating layer interposed between the gate electrode and the first and second active patterns;
a gate spacer on a sidewall of the gate electrode;
a gate capping pattern on an upper surface of the gate electrode;
a gate cutting pattern passing through the gate electrode;
an interlayer insulating layer on the gate capping pattern and the gate cutting pattern;
an active contact electrically connected to at least one of the first and second source/drain patterns through the interlayer insulating layer;
a gate contact passing through the interlayer insulating layer and the gate capping pattern and electrically connected to the gate electrode;
an upper insulating pattern provided on the active contact adjacent to the gate contact;
a blocking pattern between the gate contact and the gate spacer;
a first metal layer on the interlayer insulating layer, the first metal layer including a power wiring vertically overlapping the gate cutting pattern, and first wirings electrically connected to the active contact and the gate contact, respectively; and
a second metal layer on the first metal layer;
The second metal layer includes second wirings electrically connected to the first metal layer,
the blocking pattern is positioned between the gate contact and the upper insulating pattern;
The gate contact may be spaced apart from the active contact with the blocking pattern and the upper insulating pattern interposed therebetween. 17. The method of claim 16,
The gate spacer includes a first spacer and a second spacer,
The upper surface of the first spacer is lower than the upper surface of the second spacer,
The blocking pattern extends vertically from the top surface of the first spacer along an inner wall of the second spacer. 18. The method of claim 17,
The first spacer comprises a low-k material containing Si,
The second spacer comprises an insulating material containing Si,
The blocking pattern is a semiconductor device including polysilicon. 17. The method of claim 16,
The gate electrode includes a vertical extension extending vertically along a sidewall of the gate cutting pattern,
The blocking pattern is a semiconductor device provided on the vertical extension. 17. The method of claim 16,
A bottom surface of the blocking pattern is positioned at the same height or higher than the top surface of the gate electrode.

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