KR20210079787A - Display Panel with Touch Sensing element therein - Google Patents

Abstract

The present invention relates to an in-cell touch type display panel that can prevent a disconnection of the link line due to a scratch even in an 8-mask structure by dualizing a non-display area of a display panel into a pad part and a bezel part and composing a metal line of the pad part in multiple layers to sufficiently secure a thickness of an upper layer of a link line. The in-cell touch type display panel comprises: an array substrate divided into a display area, a bezel area, and a pad area; a gate line, a data line, and a touch line disposed in the display area of the array substrate; first and second link line parts each formed on the array substrate of the bezel area and the pad area, and formed on a same layer as the gate line with the same material as the gate line; and a floating line formed on an upper side of the second link line part of the pad area.

Description

In-cell touch type display panel {Display Panel with Touch Sensing element therein}

The present invention relates to a display panel, and more particularly, to an in-cell touch type display panel.

As the information society develops and various portable electronic devices such as mobile communication terminals and notebook computers develop, the demand for a flat panel display device that can be applied thereto is gradually increasing.

As such a flat panel display, a liquid crystal display (LCD) using liquid crystal and an OLED display using an organic light emitting diode (OLED) are used.

Such flat panel displays include a display panel having a plurality of gate lines and a plurality of data lines to display an image, and a driving circuit for driving the display panel.

Among the display devices, the display panel of the liquid crystal display includes a thin film transistor array substrate on which a thin film transistor array is formed on a glass substrate, a color filter array substrate on which a color filter array is formed on the glass substrate, and the thin film transistor A liquid crystal layer filled between the array substrate and the color filter array substrate is provided.

The thin film transistor array substrate includes a plurality of gate lines GL extending in a first direction and a plurality of data lines DL extending in a second direction perpendicular to the first direction, and each gate line and one sub-pixel area (Pixel; P) is defined by each data line. One thin film transistor and a pixel electrode are formed in one sub-pixel area P.

The display panel of the liquid crystal display generates an electric field in the liquid crystal layer by applying a voltage to an electric field generating electrode (a pixel electrode and a common electrode), and adjusts an arrangement state of liquid crystal molecules of the liquid crystal layer by the electric field to reduce incident light. Display an image by controlling the polarization.

In addition, in the display panel of the OLED display among the display devices, the plurality of gate lines and the plurality of data lines cross to define sub-pixels, and each sub-pixel includes an anode and a cathode and the anode and the cathode An OLED composed of an organic light emitting layer therebetween, and a pixel circuit independently driving the OLED are provided.

The pixel circuit may be configured in various ways, but includes at least one switching TFT, a capacitor, and a driving TFT.

The at least one switching TFT charges the capacitor with a data voltage in response to a scan pulse. The driving TFT controls the amount of light emitted by the OLED by controlling the amount of current supplied to the OLED according to the data voltage charged in the capacitor.

Such flat panel display devices are used in various application products such as TVs, projectors, mobile phones, and PDAs, and these application products do not have a separate input device and are basically equipped with a touch function so that data can be input by touching the screen. It is becoming. A display device having such a touch function is generally referred to as an in-cell touch type display device.

In the array substrate for an in-cell touch type display device, a plurality of touch blocks that detect a user's touch in addition to a gate and a data line as an example of general components of a display device as described above for performing a touch sensing function, and a touch line connected thereto This is more needed.

Accordingly, an array substrate for an in-cell touch type display panel having such a configuration generally includes a thin film transistor using low-temperature polycrystalline silicon (LTPS) as a semiconductor layer having even-numbered mobility characteristics, and the LTPS array The substrate is usually manufactured in 11 mask processes.

In such an array substrate for an in-cell touch type display panel, a gate insulating film, an interlayer insulating film, an auxiliary insulating layer, and first to fourth protective layers are provided as insulating layers.

Some of these insulating layers are omitted, and manufacturing is attempted by eight mask processes.

However, since some of the insulating layers are omitted, the thickness of the upper layer of the link line is reduced, thereby causing a problem in that the link line is disconnected due to a scratch.

The present invention is to solve the above problems, and the present invention divides the non-display area of the display panel into a pad part and a bezel part so that the metal line of the pad part is formed in multiple layers to sufficiently secure the thickness of the upper layer of the link line, An object of the present invention is to provide an in-cell touch type display panel capable of preventing disconnection of link lines due to scratches even in an 8-mask structure.

An in-cell touch type display panel according to the present invention for achieving the above object includes: an array substrate divided into a display area, a bezel area, and a pad area; a gate line, a data line, and a touch line disposed in the display area of the array substrate; first and second link line portions formed on the array substrate of the bezel region and the pad region, respectively, and formed of the same material as the gate line and on the same layer as the gate line; and a floating line formed above the second link line part of the pad area.

Here, a buffer layer and a gate insulating layer are sequentially stacked on the entire surface of the array substrate, the second link line part is formed on the gate insulating layer in the pad region, and the second link line part is formed on the entire surface of the gate insulating layer including the second link line part, the second An interlayer insulating layer having a contact hole through which a predetermined region of the link line portion is exposed is formed, the data line or the touch line is formed on the interlayer insulating layer of the display region, the interlayer insulating layer of the bezel region, the It is connected to the second link line unit through a contact hole, the first link line unit is formed integrally with the data line or the touch line, and the data line or the touch line is formed on the interlayer insulating layer of the pad area. The floating line may be formed of the same material.

In addition, an in-cell touch type display panel according to the present invention for achieving the above object includes an array substrate divided into a display area, a bezel area, and a pad area; a gate line, a data line, and a touch line disposed in the display area of the array substrate; a first link line portion formed on the array substrate in the bezel area and formed of the same material as the data line or the touch line on the same layer as the data line or the touch line; a second link line portion formed on the array substrate in the pad region to be electrically connected to the first link line portion, and formed of the same material as the gate line and on the same layer as the gate line; and a floating line formed above the second link line part of the pad area.

Here, a buffer layer and a gate insulating layer are sequentially stacked on the entire surface of the array substrate, and the first and second link line portions are formed of the same material as the gate line on the gate insulating layer of the bezel region and the pad region, An interlayer insulating layer having a contact hole through which a predetermined region of the first link line part is exposed is formed on the entire surface of the gate insulating layer including the first and second link line parts, and the contact hole is formed on the interlayer insulating layer of the display area. The data line or the touch line may be formed to be connected to the first link line part through the floating line, and the floating line may be formed of the same material as the data line or the touch line on the interlayer insulating layer of the pad area. .

The display area and the bezel area are areas covered by another substrate.

The first and second link line units may be a line connecting the data line and a data pad.

The first and second link line units may be lines connecting the touch line and the touch pad.

The in-cell touch type display panel according to the present invention having the above characteristics has the following effects.

In the pad region, a link line is formed on the same layer as the gate line using the same material as the gate line, and a floating line is formed on the interlayer insulating film of the pad region using the same material as the data line or the touch line. Even if the in-cell touch type display panel is manufactured by 8 mask processes by omitting , disconnection of link lines due to scratches can be prevented.

That is, in the prior art, when an in-cell touch type display panel is manufactured through an eight-time mask process, only the first protective layer and the second protective layer exist on the link line of the pad area, so that the thickness of the protective layer on the link line is reduced due to scratches. The link line may be disconnected.

However, in the present invention, since the link line of the pad region is formed on the same layer as the gate line with the same material as the gate line, and the floating line is formed with the same material as the data line or the touch line on the interlayer insulating film of the pad region, In addition to the first and second passivation layers, the interlayer insulating layer and the data line material are further formed on the link line of the pad region. Therefore, in the present invention, since the thickness of the protective film on the link line is increased, even when the in-cell touch type display panel is manufactured by 8 mask processes, it is possible to prevent disconnection of the link line due to a scratch.

1 is an explanatory view of an in-cell touch type display device according to an embodiment of the present invention;
2 is a configuration diagram for explaining a display driving of a display panel according to an embodiment of the present invention;
3 is a configuration diagram illustrating touch driving of a display panel according to an embodiment of the present invention;
4 is a block diagram of a display panel having a DRD structure according to an embodiment of the present invention;
5 is a cross-sectional view of one sub-pixel SP including a portion in which a thin film transistor, which is a switching element, is formed in an array substrate for an in-cell touch type display panel according to an embodiment of the present invention;
6 is a plan view of a data link line or a touch link line and a floating line according to an embodiment of the present invention;
7 is a cross-sectional view of a data link line or a touch link line and a floating line according to the first embodiment of the present invention;
8 is a cross-sectional view of a data link line or a touch link line and a floating line according to a second embodiment of the present invention;

Hereinafter, the in-cell touch display panel according to the present invention having the above characteristics will be described in more detail with reference to the accompanying drawings.

In adding reference numerals to components in each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms. When it is described that a component is “connected”, “coupled” or “connected” to another component, the component may be directly connected or connected to the other component, but other components may be interposed between each component. It will be understood that each component may be “interposed” or “connected”, “coupled” or “connected” through another component.

In addition, the display panel according to the present invention may include a liquid crystal display panel or an organic light emitting display panel.

1 illustrates a system of an in-cell touch type display device according to an embodiment of the present invention.

As shown in FIG. 1 , the in-cell touch type display device 100 according to the present invention may include a display panel 110 and various circuits.

The in-cell touch type display device 100 according to the present invention may perform a display function for displaying an image and a touch function for sensing a touch by a pointer such as a finger or a pen.

The in-cell touch type display device 100 according to the present invention may operate in the display mode during the display mode period for the display function, or may operate in the touch mode during the touch mode period for the touch function. The display mode section and the touch mode section may be temporally separated or may be temporally the same.

That is, the display mode operation for image display and the touch mode operation for touch sensing may be performed separately, or the display mode operation for image display and the touch mode operation for touch sensing may be performed together.

In the display panel 110 of the in-cell touch type display device 100 according to the present invention, a plurality of data lines DL and a plurality of gate lines GL for displaying an image are disposed, and these data lines ( DL) and a plurality of subpixels SP defined by the gate lines GL may be arranged.

In addition, a plurality of touch electrodes TE serving as a touch sensor for touch sensing may be disposed on the display panel 110 .

The in-cell touch type display device 100 according to the present invention includes a data driving circuit (DDC), a gate driving circuit (GDC), etc. to drive the display panel 110 during a display mode section. may further include at least one controller for controlling operation timing or power supply of the data driving circuit DDC and the gate driving circuit GDC.

In-cell touch type display device 100 according to the present invention, a touch driving circuit (TDC) for driving a plurality of touch electrodes TE of the display panel 110 during a touch mode section, and a touch mode section It may include a touch processor (TP) that determines the presence or absence of a touch and/or a touch position based on signals received from the touch electrodes TE to which the touch driving signal TDS is applied.

The touch driving circuit TDC may supply a touch driving signal (TDS) to the plurality of touch electrodes TE in order to drive the plurality of touch electrodes TE, and the touch driving signal TDS may A touch sensing signal (TSS) may be received from each supplied touch electrode TE.

The touch driving signal TDC transfers the received touch sensing signal TSS or sensing data obtained by signal processing the same to the touch processor TP. The touch processor TP may execute a touch algorithm by using the touch sensing signal TSS or the sensed data, and may determine the presence or absence of a touch and/or a touch position through this.

2 is a diagram illustrating configurations for driving a display of the display panel 110 according to an embodiment of the present invention, and FIG. 3 is a diagram showing configurations for driving a touch of the display panel 110 according to an embodiment of the present invention. .

Referring to FIG. 2 , a plurality of data lines DL and a plurality of gate lines GL are disposed on the display panel 110 according to an embodiment of the present invention for display driving, and are defined by these data lines DL and gate lines GL. A plurality of sub-pixels SP are arranged.

Each data line DL receives an image data voltage VDATA for image display from the data driving circuit DDC. Accordingly, a configuration for electrically connecting each data line DL and a corresponding data channel (a point at which a corresponding data voltage is output) in the data driving circuit DDC is required. Accordingly, the data driving circuit DDC may be of a chip on film (COF) type or a chip on glass (COG) type, and may be electrically connected to a pad portion in a non-display area of the display panel 110 .

Accordingly, a plurality of data pads DP are disposed in the pad portion of the non-display area of the display panel 110 , and the data pads DP are electrically connected to the data lines DL and are electrically connected thereto. It is electrically connected to the data channels of the data driving circuit DDC.

Of course, although not shown in FIG. 2 , gate pads for electrically connecting the gate lines GL and the gate driving circuit GDC may also be formed in the non-display area of the display panel 110 .

Meanwhile, in the display panel 110 according to the embodiment of the present invention, for touch driving, as shown in FIG. 3 , a plurality of touch electrodes TE are disposed, and the plurality of touch electrodes TE and A plurality of touch lines TL for transferring signals between the touch driving circuits TDC are disposed.

In order to electrically connect the plurality of touch lines TL and the touch driving circuit TDC, a plurality of touch pads TP corresponding to the number of touch lines are disposed in the non-display area of the display panel 110 . .

Lines formed in the non-display area to connect the plurality of data pads DP and the plurality of data lines DL described above are referred to as data link lines, and the plurality of touch pads DP and Lines formed in the non-display area to connect the plurality of touch lines DL are referred to as touch link lines.

2 and 3 , the plurality of data lines DL and the plurality of touch lines TL are disposed in the same direction, and the plurality of data pads DP and the plurality of touch lines TL are disposed in the same direction. The touch pads TP are disposed on the same side of the non-display area of the display panel 110 .

4 is a block diagram of a display panel having a DRD structure according to an embodiment of the present invention.

As shown in FIG. 4 , when the display panel has a double rate driving (DRD) structure, two horizontally adjacent pixels are connected to one data line DL1, DL2, and DL3, and the horizontally adjacent pixels are connected to each other. One or two pixels are connected to different gate lines GL1, GL2, GL3, GL4. In addition, pixels in the horizontal direction connected to the same gate line are connected to different data lines. In addition, the pixels in the vertical direction are connected to the same data line, and when one of the two vertically adjacent pixels is connected to the odd-numbered gate line, the other is connected to the even-numbered gate line, or two vertically adjacent pixels are connected to the even-numbered gate line. If one of the pixels is connected to the even-numbered gate line, the other is connected to the odd-numbered gate line.

In addition, in such a DRD structure, touch lines TL1 , TL2 , and TL3 are disposed between two horizontally adjacent pixels connected to different data lines.

That is, as described with reference to FIG. 4 , the plurality of data lines DL1 , DL2 , and DL3 and the plurality of touch lines TL1 , TL2 , and TL3 are parallel to each other and disposed in the same direction.

5 is a cross-sectional view of one sub-pixel SP including a portion in which a thin film transistor, which is a switching element, is formed in an array substrate for an in-cell touch type display panel according to an embodiment of the present invention. 5 illustrates an example of a thin film transistor array substrate of an in-cell touch-type liquid crystal display panel among in-cell touch-type display panels. Therefore, the in-cell touch type display panel according to the embodiment of the present invention is not limited to the liquid crystal display panel, but may also be applied to the OLED display panel.

As shown in FIG. 5, the thin film transistor array substrate of the in-cell touch type liquid crystal display panel according to the present invention is made of an inorganic insulating material, for example, silicon oxide (SiO2) or silicon nitride (SiNx) on a transparent substrate 101. A buffer layer 105 made of is formed. At this time, when the transparent substrate 101 is made of a glass material, the buffer layer 105 is a polysilicon semiconductor layer 110 affected by alkali ions emitted from the glass substrate 101 during a high temperature process of 500° C. or higher. Since the deterioration of the operating characteristics of the thin film transistor Tr may occur, the formation may be omitted to prevent this.

Also, although not shown in the drawings, a light blocking layer may be further formed as a metal layer in a portion corresponding to the thin film transistor Tr before the buffer layer 105 is formed.

A device region TrA in each sub-pixel SP above the buffer layer 105 is made of low-temperature polysilicon, and the central portion thereof is formed by a first semiconductor region 113a forming a channel and both sides of the first semiconductor region 113a. A semiconductor layer 113 including a second semiconductor region 113b doped with a high concentration of impurities is formed.

A gate insulating layer 116 made of an inorganic insulating material is formed on the entire surface of the transparent substrate 101 including the semiconductor layer 113 .

On the gate insulating layer 116 , a metal material, for example, any one or two of aluminum (Al), aluminum-neodymium alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo), and molybdenum-titanium (MoTi) As the above material, a gate line (not shown) having a single-layer or multi-layer structure and connected to the boundary of each sub-pixel SP and extending in one direction is formed.

At this time, on the gate insulating layer 116 above the first semiconductor region 113a, the gate electrode 120 has the same structure as the gate line (not shown) and has the same structure as the gate line (not shown) and protrudes from the gate line (not shown). this is being formed

An interlayer insulating layer 123 made of an inorganic insulating material is formed on the entire surface of the substrate 101 including the gate electrode 120 and the gate line (not shown). Here, in the interlayer insulating film 123 and the gate insulating film 116 positioned thereunder, a semiconductor layer contact hole exposing each of the second semiconductor regions 113b positioned on both sides of the first semiconductor region 113a, respectively ( 125) is provided.

A metal material, for example, aluminum (Al), aluminum-neodymium alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo), molybdenum is formed on the upper portion of the interlayer insulating layer 123 including the semiconductor layer contact hole 125 . - Any one or two or more materials of titanium (MoTi), a single-layer or multi-layer structure, disposed in a direction perpendicular to the gate line (not shown) to form a data line DL defining a sub-pixel SP; have. In this case, when the data line DL has a multi-layer structure, a first layer made of molybdenum (Mo) or molybdenum-titanium (MoTi), aluminum (Al), an aluminum-neodymium alloy (AlNd), copper (Cu), It is preferable to have a triple layer structure of a second layer made of any one of copper alloys and a third layer made of molybdenum (Mo) or molybdenum-titanium (MoTi). In the drawing, the data line DL has a single-layer structure as an example.

The device region TrA over the interlayer insulating layer 123 has the same structure as that of the data line DL and is in contact with the second semiconductor region 113b exposed through the semiconductor layer contact hole 125 , respectively. and source and drain electrodes 133 and 136 spaced apart from each other are formed. The source electrode 133 is electrically connected to the data line DL.

In addition, a touch line TL is formed on the interlayer insulating layer 123 in a direction parallel to the data line DL using the same material and the same structure as the data line DL (refer to FIG. 4 ).

Here, the semiconductor layer 113, the gate insulating layer 116, the gate electrode 120, the interlayer insulating layer 123, and the source and drain electrodes 133 and 136 sequentially stacked in the device region TrA. constitutes a thin film transistor (Tr) which is a switching element.

The thin film transistor Tr is electrically connected to the gate line (not shown) and the data line DL, as shown in FIG. 4 . That is, the gate electrode 120 is connected to the gate lines GL1 , GL2 , GL3 , and GL4 in FIG. 4 , and the source electrode 133 is connected to the data lines DL1 , DL2 and DL3 .

The entire surface of the substrate including the data line DL, the source and drain electrodes 133 and 136 and the touch line TL is made of an organic insulating material, for example, photoacrylic or benzocyclobutene, so that the surface thereof is flat. A first protective layer 145 is formed. Here, the first passivation layer 145 is provided with a drain contact hole 147 exposing the drain electrode 136 of the thin film transistor Tr.

On the first passivation layer 145 of the sub-pixel SP region, indium-tin-oxide (ITO) or indium-zinc-oxide (IZO), which is a transparent conductive material, is formed, and the drain contact hole 147 is formed. ) through which the pixel electrode 150 is electrically connected to the drain electrode 136 is formed. When a driving voltage is applied, the pixel electrode 150 generates a fringe field together with the common electrode 160 to be formed next.

A second protective layer 155 is formed of an inorganic insulating material, for example, silicon oxide (SiO2) or silicon nitride (SiNx), on the entire surface of the substrate including the pixel electrode 150 .

In addition, a common electrode 160 is formed on the second protective layer 155 . The common electrode 160 has a plurality of openings in a region overlapping the pixel electrode 150 , and is formed over a plurality of sub-pixel SP regions to constitute one touch electrode (TE in FIG. 3 ). do.

Although not shown in FIG. 5 , as shown in FIG. 3 , a touch contact hole (not shown) is formed in the first and second protective layers 145 and 155 to expose the touch line TL, and the The common electrode 160 is electrically connected to the touch line TL through the touch contact hole (not shown).

Although FIG. 5 illustrates that the pixel electrode 150 is formed on the first passivation layer 145 and the common electrode 160 is formed on the second passivation layer 155, the present invention is not limited thereto. The positions of the pixel electrode 150 and the common electrode 160 may be changed.

That is, a touch contact hole (not shown) is formed in the first protective layer 145 to expose the touch line TL, and the first protective layer is connected to the touch line TL through the touch contact hole. The common electrode 160 may be formed on the layer 145 , and a second protective layer 155 may be formed on the entire surface of the substrate including the common electrode 160 .

A drain contact hole 147 exposing the drain electrode 136 of the thin film transistor is provided in the first to second protective layers 145 and 155 .

A pixel electrode 150 may be formed on the second passivation layer 155 to be electrically connected to the drain electrode 136 through the drain contact hole 147 . In this case, the pixel electrode 150 may have a plurality of openings.

Meanwhile, FIG. 6 is a plan view of a data link line or a touch link line and a floating line according to an embodiment of the present invention.

The array substrate 101 of the liquid crystal display panel is divided into a display area AA and a non-display area NA, and the non-display area NA is divided into a bezel area and a pad area. The display area AA is an area in which the thin film transistor array substrate 101 and the color filter array substrate are bonded to display an image, and the non-display area NA is an area in which an image is not displayed. The bezel area is adjacent to the display area AA and is covered by the color filter array substrate, and the pad area Pad is an area not covered by the color filter array substrate.

In addition, a data link line or a touch link line disposed in the bezel area is referred to as a first link line unit Link1, and a data link line or a touch link line disposed in the pad area Pad is referred to as a second link. It is called a line part Link2.

In the display area AA, the data line DL and the touch line TL are formed on the same layer with the same material, and the pad area Pad has the same material as the gate line described with reference to FIG. 5 and the same as the gate line. A second link line portion Link2 is formed on the layer.

The first link line portions Link1 formed in the bezel area are alternately formed of the same material as the gate line described with reference to FIG. 5 and formed on the same layer as the gate line, and the data line DL (or touch It is formed in the same layer of the same material as line TL).

In addition, at the boundary between the display area AA and the bezel area, the first link line part Link1 and the data line DL or touch line TL formed of the same material as the gate line are connected to each other. They are electrically connected through the first contact hole C/H1.

In addition, the first link line part Link1 and the second link line part Link1 formed of the same material as the data line DL (or touch line TL) at a boundary between the bezel region and the pad region Pad. The second link line part Link2 is electrically connected through the second contact hole C/H2.

7 is a cross-sectional view of a data link line or a touch link line according to the first embodiment of the present invention. That is, in FIG. 6 , it is a cross-sectional view in the direction of the first link line part Link1 and the second link line part Link2 formed on the same layer with the same material as the data line DL (or touch line TL).

As described in FIG. 6 , the array substrate 101 of the liquid crystal display panel is divided into a display area AA and a non-display area NA, and the non-display area NA is divided into a bezel area and a pad area ( pad). The display area AA is an area in which the thin film transistor array substrate 101 and the color filter array substrate are bonded to display an image, and the non-display area NA is an area in which an image is not displayed. The bezel area is adjacent to the display area AA and is covered by the color filter array substrate, and the pad area Pad is an area not covered by the color filter array substrate.

In addition, a data link line or a touch link line disposed in the bezel area is referred to as a first link line unit Link1, and a data link line or a touch link line disposed in the pad area Pad is referred to as a second link. It is called a line part Link2.

5 , in the display area AA, the data line DL and the touch line TL are formed of the same material and on the same layer. In addition, in the pad area Pad, a floating line F/L is formed on the same layer as the data line DL or touch line TL with the same material as the data line DL or touch line TL. is formed

Here, the floating line F/L may completely overlap the second link line part Link2. The floating line F/L may partially overlap the second link line part Link2. The floating line F/L may be disposed between adjacent second link line parts Link2 so as not to overlap the second link line part Link2.

In addition, as shown in FIGS. 6 and 7 , the first link line part Link1 of the data link line or the touch link line formed in the bezel area is the data line DL or the touch line. It extends from TL and may be formed of the same material as the data line DL or the touch line TL on the same layer as the data line DL or the touch line TL.

On the other hand, as shown in FIGS. 6 and 7 , the second link line part Link2 of the data link line or the touch link line formed in the pad area Pad is made of the same material as the gate line described in FIG. 5 . It may be formed on the same layer as the gate line.

This will be described in detail as follows.

A buffer layer 105 made of an inorganic insulating material, for example, silicon oxide (SiO2) or silicon nitride (SiNx), on the entire surface of the transparent substrate 101 divided into the display area AA, the bezel area, and the pad area. ) and a gate insulating film 116 made of an inorganic insulating material are sequentially stacked.

A second link line part Link2 is formed on the gate insulating layer 116 of the pad region Pad using the same material as the gate line.

An interlayer insulating layer 123 made of an inorganic insulating material is formed on the entire surface of the gate insulating layer 116 including the second link line part Link2 . Here, a second contact hole 149 (see C/H2 of FIG. 6 ) is formed in the interlayer insulating layer 123 to expose a predetermined region of the second link line part Link2 .

In addition, the data line DL and the first link line unit Link1 or the touch line TL and the first link line on the interlayer insulating layer 123 over the display area AA and the bezel area Bezel. A section Link1 is formed. Here, the first link line part Link1 is electrically connected to the second link line part Link2 through the second contact hole 149 . The data line DL and the first link line part Link1 are integrally formed of the same material, and the touch line TL and the first link line part Link1 are also integrally formed of the same material.

In addition, floating lines F/L are formed on the interlayer insulating layer 123 of the pad region Pad using the same material as the data line DL or the touch line TL. An electric signal is not applied to the floating line F/L, and serves to protect the second link line part Link2 formed below.

The interlayer insulating layer 123 including the floating line F/L and the data line DL and the first link line part Link1 or the touch line TL and the first link line part Link1 A first protective layer 145 made of an organic insulating material, for example, photoacrylic or benzocyclobutene, having a flat surface is formed on the entire surface, and an inorganic insulating material, for example, on the entire surface of the first protective layer 145 The second passivation layer 155 is formed of silicon oxide (SiO2) or silicon nitride (SiNx).

Meanwhile, FIG. 8 is a cross-sectional view of a data link line or a touch link line according to a second embodiment of the present invention. That is, in FIG. 6 , it is a cross-sectional view in the direction of the first link line part Link1 and the second link line part Link2 formed on the same layer with the same material as the gate line.

As described in FIG. 6 , the array substrate 101 of the liquid crystal display panel is divided into a display area AA and a non-display area NA, and the non-display area NA is divided into a bezel area and a pad area ( pad). The display area AA is an area in which the thin film transistor array substrate 101 and the color filter array substrate are bonded to display an image, and the non-display area NA is an area in which an image is not displayed. The bezel area is adjacent to the display area AA and covered by the color filter array substrate, and the pad area Pad is an area not covered by the color filter array substrate.

In addition, a data link line or a touch link line disposed in the bezel area is referred to as a first link line unit Link1, and a data link line or a touch link line disposed in the pad area Pad is referred to as a second link. It is called a line part Link2.

5 , in the display area AA, the data line DL and the touch line TL are formed of the same material and on the same layer. In addition, in the pad area Pad, a floating line F/L is formed on the same layer as the data line DL or touch line TL with the same material as the data line DL or touch line TL. is formed

Similarly, the floating line F/L may completely overlap the second link line part Link2. The floating line F/L may partially overlap the second link line part Link2. The floating line F/L may be disposed between adjacent second link line parts Link2 so as not to overlap the second link line part Link2.

On the other hand, as shown in FIG. 8 , the first link line part Link1 of the data link line or the touch link line formed in the bezel region is made of the same material as the gate line described in FIG. 5 . It is formed on the same layer as the gate line.

In addition, as shown in FIG. 8 , the second link line part Link2 of the data link line or the touch link line formed in the pad area Pad is made of the same material as the gate line described in FIG. 5 . formed on the same layer as

This will be described in detail as follows.

A buffer layer 105 made of an inorganic insulating material, for example, silicon oxide (SiO2) or silicon nitride (SiNx), on the entire surface of the transparent substrate 101 divided into the display area AA, the bezel area, and the pad area. ) and a gate insulating film 116 made of an inorganic insulating material are sequentially stacked.

In addition, a first link line part Link1 and a second link line part Link2 are formed on the gate insulating layer 116 over the bezel region and the pad region using the same material as the gate line. do. The first link line part Link1 and the second link line part Link2 are integrally formed of the same material as the gate line.

An interlayer insulating layer 123 made of an inorganic insulating material is formed on the entire surface of the gate insulating layer 116 including the first and second link line portions Link1 and Link2 . Here, a first contact hole 148 (refer to C/H1 of FIG. 6 ) is formed in the interlayer insulating layer 123 to expose a predetermined region of the first link line part Link1 .

A data line DL or a touch line TL is formed on the interlayer insulating layer 123 of the display area AA. Here, the data line DL or the touch line TL is electrically connected to the first link line part Link1 through the first contact hole 148 .

In addition, floating lines F/L are formed on the interlayer insulating layer 123 of the pad region Pad using the same material as the data line DL or the touch line TL. An electric signal is not applied to the floating line F/L, and serves to protect the second link line part Link2 formed below.

The interlayer insulating layer 123 including the floating line F/L and the data line DL and the first link line part Link1 or the touch line TL and the first link line part Link1 A first protective layer 145 made of an organic insulating material, for example, photoacrylic or benzocyclobutene, having a flat surface is formed on the entire surface, and an inorganic insulating material, for example, on the entire surface of the first protective layer 145 The second passivation layer 155 is formed of silicon oxide (SiO2) or silicon nitride (SiNx).

As described above, since the floating line F/L is formed of the same material as the data line DL or the touch line TL on the interlayer insulating layer 123 of the pad region Pad, the insulating layer Even if some of these are omitted and the in-cell touch type display panel is manufactured through eight mask processes, disconnection of link lines due to scratches can be prevented.

The above description is merely illustrative of the present invention, and various modifications may be made by those of ordinary skill in the art to which the present invention pertains without departing from the technical spirit of the present invention. Therefore, the embodiments disclosed in the specification of the present invention do not limit the present invention. The scope of the present invention should be construed by the following claims, and all technologies within the scope equivalent thereto should be construed as being included in the scope of the present invention.

AA: display area NA: non-display area
Bezel: bezel area Pad: .pad area
DL: data line TL: touch line
Link1, Link2: Link line part F/L: Floating line

Claims (10)

a first substrate divided into a display area, a bezel area, and a pad area;
a gate line, a data line, and a touch line disposed in the display area of the first substrate;
a first link line portion formed on the first substrate in the bezel area and formed of the same material as the data line or the touch line on the same layer as the data line or the touch line;
a second link line portion formed on the first substrate in the pad region to be electrically connected to the first link line portion, and formed of the same material as the gate line and on the same layer as the gate line; and
An in-cell touch type display panel having a floating line formed above the second link line portion of the pad area. The method of claim 1,
The floating line at least partially overlaps the second link line part in an in-cell touch type display panel. The method of claim 1,
The in-cell touch type display panel, characterized in that the first and second link line units are lines connecting the data line and the data pad. The method of claim 1,
The in-cell touch type display panel, wherein the first and second link line portions are lines connecting the touch line and the touch pad. The method of claim 1,
A buffer layer and a gate insulating film are sequentially stacked on the entire surface of the first substrate,
the second link line portion is formed on the gate insulating film in the pad region;
An interlayer insulating film having a contact hole through which a predetermined region of the second link line portion is exposed is formed on the entire surface of the gate insulating film including the second link line portion;
the data line or the touch line is formed on the interlayer insulating film of the display area;
The first link line part is formed on the interlayer insulating film in the bezel area, the first link line part being connected to the second link line part through the contact hole, and integrally with the data line or the touch line;
The in-cell touch type display panel, wherein the floating line is formed of the same material as the data line or the touch line on the interlayer insulating layer in the pad area. a first substrate divided into a display area, a bezel area, and a pad area;
a gate line, a data line, and a touch line disposed in the display area of the first substrate;
first and second link line portions formed on the first substrate in the bezel area and the pad area, respectively, and formed on the same layer as the gate line using the same material as the gate line; and
An in-cell touch type display panel having a floating line formed above the second link line portion of the pad area. 7. The method of claim 6,
The floating line at least partially overlaps the second link line part in an in-cell touch type display panel. 7. The method of claim 6,
The in-cell touch type display panel, characterized in that the first and second link line units are lines connecting the data line and the data pad. 7. The method of claim 6,
The in-cell touch type display panel, wherein the first and second link line portions are lines connecting the touch line and the touch pad. 7. The method of claim 6,
A buffer layer and a gate insulating film are sequentially stacked on the entire surface of the first substrate,
The first and second link line portions are formed of the same material as the gate line on the gate insulating layer of the bezel area and the pad area,
an interlayer insulating film having a contact hole through which a predetermined region of the first link line portion is exposed is formed on the entire surface of the gate insulating film including the first and second link line portions;
the data line or the touch line is formed on the interlayer insulating film of the display area to be connected to the first link line part through the contact hole;
The in-cell touch type display panel, wherein the floating line is formed of the same material as the data line or the touch line on the interlayer insulating layer in the pad area.

Images