KR20210075553A - Surface treatment method for through hole of printed circuit board - Google Patents

Surface treatment method for through hole of printed circuit board Download PDF

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KR20210075553A
KR20210075553A KR1020190166775A KR20190166775A KR20210075553A KR 20210075553 A KR20210075553 A KR 20210075553A KR 1020190166775 A KR1020190166775 A KR 1020190166775A KR 20190166775 A KR20190166775 A KR 20190166775A KR 20210075553 A KR20210075553 A KR 20210075553A
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graphene oxide
circuit board
printed circuit
hole
reduced graphene
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KR1020190166775A
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Korean (ko)
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양우석
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한국전자기술연구원
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Priority to KR1020190166775A priority Critical patent/KR20210075553A/en
Priority to PCT/KR2020/016714 priority patent/WO2021118108A1/en
Publication of KR20210075553A publication Critical patent/KR20210075553A/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/31—Coating with metals
    • C23C18/32—Coating with nickel, cobalt or mixtures thereof with phosphorus or boron
    • C23C18/34—Coating with nickel, cobalt or mixtures thereof with phosphorus or boron using reducing agents
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Carbon And Carbon Compounds (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

Proposed are a method for treating a printed circuit board through-hole surface capable of forming a high-quality plating layer by forming a highly reliable surface treatment layer at low costs, and a manufacturing method thereof. The method for treating the printed circuit board through-hole surface according to the present invention comprises: a step of forming a charged and reduced graphene oxide layer inside the through-hole by immersing the printed circuit board having the through-hole in a solution including the charged and reduced graphene oxide; and a step of cleaning the printed circuit board.

Description

인쇄회로기판 관통홀 표면처리방법 및 그의 제조방법{Surface treatment method for through hole of printed circuit board}Printed circuit board through-hole surface treatment method and manufacturing method thereof {Surface treatment method for through hole of printed circuit board}

본 발명은 인쇄회로기판 관통홀 표면처리방법 및 그의 제조방법에 관한 것으로, 보다 상세하게는 저비용으로 신뢰성 높은 표면처리층 형성이 가능하여 고품질 도금층 형성이 가능한 인쇄회로기판 관통홀 표면처리방법 및 그의 제조방법에 관한 것이다.The present invention relates to a printed circuit board through-hole surface treatment method and a method for manufacturing the same, and more particularly, to a printed circuit board through-hole surface treatment method capable of forming a high-quality plating layer by forming a highly reliable surface treatment layer at low cost and manufacturing the same it's about how

최근에 이르러, 전자산업의 급속한 발달과 전자제품의 디지털화 및 박형화로 인하여 전자제품에 사용되는 다양한 형태의 전자부품들이 실장되는 기판도 회로패턴의 집적화가 급속히 이루어지고 있다. 또한, 전자제품의 박형화에 따라 기판의 두께가 점차적으로 얇아짐과 아울러 박형화의 조건을 만족하기 위하여 기판에 부품이 실장된 상태에서 초소형의 패키지 패턴이 구현되어야 한다.In recent years, due to the rapid development of the electronic industry and the digitalization and thinning of electronic products, the integration of circuit patterns on the boards on which various types of electronic components used in electronic products are mounted is also rapidly being achieved. In addition, the thickness of the substrate is gradually reduced according to the reduction in the thickness of electronic products, and in order to satisfy the conditions of thinning, an ultra-small package pattern must be implemented in a state in which the components are mounted on the substrate.

기판에 부품을 실장하거나 상하부 회로패턴간 연결시 관통홀이 도금되어 도금층에 의한 배선연결이 가능하다. 그러나, 인쇄회로기판의 박형화 및 소형화 추세로 인하여 관통홀의 크기가 매우 작아지게 되어 관통홀 내부의 도금공정에 어려움이 있다. 또한, 관통홀의 도금시, 일반적으로 구리 또는 구리-니켈 도금층을 형성하는데, 이를 위한 도금촉매로 사용되는 팔라듐은 고가이므로 도금공정의 비용을 높여 전체 공정의 비용이 높아지는 문제가 있다. When parts are mounted on a board or when connecting between upper and lower circuit patterns, the through-holes are plated to enable wiring through the plating layer. However, due to the thinning and miniaturization of the printed circuit board, the size of the through-hole becomes very small, and there is a difficulty in the plating process inside the through-hole. In addition, when plating through-holes, a copper or copper-nickel plating layer is generally formed. Since palladium used as a plating catalyst for this is expensive, there is a problem in that the cost of the plating process is increased, thereby increasing the cost of the entire process.

아울러, 작은 사이즈의 관통홀을 형성하기 위하여 레이저 또는 기계적 펀칭 등의 방법으로 관통홀이 형성되는데, 생성된 관통홀 내부가 매끄럽지 않아 촉매층의 탈락을 유도하고, 이는 곧 도금층의 불량을 야기하여 전체 인쇄회로기판 제품의 불량율 상승의 주요원인이 되고 있다. In addition, the through-hole is formed by a method such as laser or mechanical punching to form a small-sized through-hole, and the inside of the generated through-hole is not smooth, which induces the catalytic layer to fall off, which in turn causes defects in the plating layer and thus the entire printed circuit. It is the main cause of the rise in the defect rate of substrate products.

본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서, 본 발명의 목적은, 저비용으로 신뢰성 높은 표면처리층 형성이 가능하여 고품질 도금층 형성이 가능한 인쇄회로기판 관통홀 표면처리방법 및 그의 제조방법을 제공함에 있다.The present invention has been devised to solve the above problems, and an object of the present invention is to provide a method for surface treatment of a printed circuit board through-hole surface treatment capable of forming a high-quality plating layer by forming a reliable surface treatment layer at low cost and a method for manufacturing the same. is in providing.

본 발명의 일 측면에 따르는 인쇄회로기판 관통홀 표면처리방법은, 관통홀을 갖는 인쇄회로기판을 하전되고 환원된 산화그래핀을 포함하는 용액에 침지시켜 관통홀 내부에 하전되고 환원된 산화그래핀층을 형성하는 단계; 및 인쇄회로기판을 세척하는 단계;를 포함한다. A printed circuit board through-hole surface treatment method according to an aspect of the present invention comprises immersing a printed circuit board having through-holes in a solution containing charged and reduced graphene oxide to form a charged and reduced graphene oxide layer inside the through-holes. forming a; and cleaning the printed circuit board.

하전되고 환원된 산화그래핀은 양으로 하전된 환원된 산화그래핀 및 음으로 하전된 환원된 산화그래핀 중 어느 하나일 수 있다. The charged reduced graphene oxide may be any one of positively charged reduced graphene oxide and negatively charged reduced graphene oxide.

양으로 하전된 환원된 산화그래핀은 표면전하가 NH3 +관능기에 의해 나타나는 것일 수 있다. The positively charged reduced graphene oxide may have a surface charge represented by an NH 3 + functional group.

양으로 하전된 환원된 산화그래핀은 산화그래핀을 1-(3-디메틸아미노프로필)-3-에틸카르보디이미드 메티오디드(1-(3-dimethylaminopropyl)-3-ethylcarbodiimide methiodide) 및 에틸렌디아민으로 처리하여 양으로 하전된 산화그래핀을 얻는 단계; 및 히드라진으로 환원시키는 단계;를 수행하여 얻을 수 있다.The positively charged reduced graphene oxide converts graphene oxide into 1-(3-dimethylaminopropyl)-3-ethylcarbodiimide methiodide (1-(3-dimethylaminopropyl)-3-ethylcarbodiimide methiodide) and ethylenediamine. processing to obtain positively charged graphene oxide; and reducing with hydrazine;

음으로 하전된 환원된 산화그래핀은 표면전하가 COO-관능기에 의해 나타나는 것일 수 있다. The negatively charged reduced graphene oxide may have a surface charge represented by a COO - functional group.

음으로 하전된 산화그래핀은 산화그래핀이 NH4OH분위기 하에서 히드라진에 의해 환원된 것일 수 있다. Negatively charged graphene oxide may be graphene oxide reduced by hydrazine under NH 4 OH atmosphere.

본 발명의 다른 측면에 따르면, 관통홀을 갖는 인쇄회로기판을 하전되고 환원된 산화그래핀을 포함하는 용액에 침지시켜 관통홀 내부에 하전되고 환원된 산화그래핀층을 형성하는 단계; 및 인쇄회로기판을 세척하는 단계;를 포함하는 인쇄회로기판 관통홀 표면처리방법에 의해 관통홀 내부에 하전되고 환원된 산화그래핀층이 형성되어 표면처리된 인쇄회로기판이 제공된다.According to another aspect of the present invention, the method comprising: immersing a printed circuit board having a through hole in a solution containing charged and reduced graphene oxide to form a charged and reduced graphene oxide layer inside the through hole; and washing the printed circuit board; a charged and reduced graphene oxide layer is formed in the through-hole by the printed circuit board through-hole surface treatment method comprising a surface-treated printed circuit board is provided.

관통홀은 내측면에 요철이 형성된 것일 수 있다. The through-hole may have irregularities formed on its inner surface.

관통홀은 내측면에 경사를 갖는 돌출부가 형성된 것일 수 있다. The through hole may be formed with a protrusion having a slope on the inner surface.

하전되고 환원된 산화그래핀층은 환원된 산화그래핀이 10층 이하일 수 있다. The charged and reduced graphene oxide layer may have 10 or less reduced graphene oxide layers.

본 발명의 또다른 측면에 따르면, 관통홀을 갖는 인쇄회로기판을 하전되고 환원된 산화그래핀을 포함하는 용액에 침지시켜 관통홀 내부에 하전되고 환원된 산화그래핀층을 형성하는 단계; 및 인쇄회로기판을 세척하는 단계;를 포함하는 인쇄회로기판 관통홀 표면처리방법에 의해 관통홀의 표면이 처리된 인쇄회로기판을 준비하는 단계; 및 인쇄회로기판을 도금액이 침지시켜 무전해도금하는 단계;를 포함하는 인쇄회로기판 도금방법이 제공된다.According to another aspect of the present invention, the method comprising: immersing a printed circuit board having a through hole in a solution containing charged and reduced graphene oxide to form a charged and reduced graphene oxide layer inside the through hole; and washing the printed circuit board; preparing a printed circuit board in which the surface of the through hole is treated by a printed circuit board through hole surface treatment method comprising; and electroless plating by immersing the printed circuit board in a plating solution.

본 발명의 또다른 측면에 따르면, 관통홀을 갖는 인쇄회로기판을 하전되고 환원된 산화그래핀을 포함하는 용액에 침지시켜 관통홀 내부에 하전되고 환원된 산화그래핀층을 형성하는 단계; 및 인쇄회로기판을 세척하는 단계;를 포함하는 인쇄회로기판 관통홀 표면처리방법에 의해 관통홀의 표면이 처리된 인쇄회로기판을 준비하는 단계; 및 인쇄회로기판을 도금액이 침지시켜 무전해도금하는 단계;를 포함하는 인쇄회로기판 도금방법에 의해 도금층이 형성된 다층 인쇄회로기판이 제공된다.According to another aspect of the present invention, the method comprising: immersing a printed circuit board having a through hole in a solution containing charged and reduced graphene oxide to form a charged and reduced graphene oxide layer inside the through hole; and washing the printed circuit board; preparing a printed circuit board in which the surface of the through hole is treated by a printed circuit board through hole surface treatment method comprising; and electroless plating by immersing the printed circuit board in a plating solution. There is provided a multilayer printed circuit board having a plating layer formed thereon by a printed circuit board plating method comprising a.

본 발명의 실시예들에 따른 인회로기판 관통홀 표면처리방법에 따르면, 하전되고 환원된 산화그래핀층을 이용하므로 그래핀의 유연성으로 인하여 매끄럽지 않은 관통홀 내부를 공극 등이 발생하지 않도록 표면처리가 가능하여 우수한 품질의 도금층 형성이 가능하다. According to the printed circuit board through-hole surface treatment method according to the embodiments of the present invention, since a charged and reduced graphene oxide layer is used, the surface treatment is performed so that voids do not occur inside the non-smooth through-hole due to the flexibility of graphene. It is possible to form a plating layer of excellent quality.

또한, 고가의 귀금속 촉매를 사용하지 않고도 높은 전기전도성의 환원된 산화그래핀층을 도금촉매로 사용하여 전체 인쇄회로기판 제조비용을 낮추는 효과가 있다. In addition, there is an effect of lowering the overall printed circuit board manufacturing cost by using the reduced graphene oxide layer with high electrical conductivity as a plating catalyst without using an expensive noble metal catalyst.

도 1은 본 발명의 일실시예에 따른 인쇄회로기판 관통홀 표면처리방법에 따라 관통홀에 하전되고 환원된 산화그래핀층이 형성된 인쇄회로기판의 단면도이고, 도2는 관통홀에 도금층이 형성된 인쇄회로기판의 단면도이며, 도 3은 본 발명의 다른 실시예에 따른 인쇄회로기판의 관통홀의 단면도이고, 도 4는 본 발명의 또다른 실시예에 따른 인쇄회로기판의 관통홀의 단면도이다.
도 5는 본 발명의 일실시예에 따른 인쇄회로기판 관통홀 표면처리방법에 있어서 하전되고 환원된 산화그래핀을 합성하기 위한 산화그래핀을 도시한 도면이고, 도 6은 음으로 하전되고 환원된 산화그래핀을 도시한 도면이며, 도 7 및 도 8은 각각 산화그래핀을 양이온 관능기 처리한 산화그래핀 중간산물 및 중간산물을 환원시켜 얻은 양으로 하전되고 환원된 산화그래핀을 도시한 도면이다.
도 9a는 폴리스티렌 입자 표면에 양으로 하전되고 환원된 산화그래핀을 적층한 이미지이고, 도 9b는 양으로 하전되고 환원된 산화그래핀이 적층된 폴리스티렌 입자 표면에 음으로 하전되고 환원된 산화그래핀을 적층한 이미지이고, 도 9c는 음으로 하전되고 환원된 산화그래핀이 적층된 폴리스티렌 입자 표면에 양으로 하전되고 환원된 산화그래핀을 적층한 이미지이고, 9d는 양으로 하전되고 환원된 산화그래핀이 적층된 폴리스티렌 입자 표면에 음으로 하전되고 환원된 산화그래핀을 적층한 이미지이고, 도 10은 폴리스티렌 입자 표면에 각각 양으로 하전되고 환원된 산화그래핀 및 음으로 하전되고 환원된 산화그래핀을 적층한 후의 전위특성을 도시한 그래프이다. 1 is a cross-sectional view of a printed circuit board in which a charged and reduced graphene oxide layer is formed in a through hole according to a printed circuit board through hole surface treatment method according to an embodiment of the present invention, and FIG. 2 is a printed circuit board in which a plating layer is formed in the through hole. It is a cross-sectional view of a circuit board, FIG. 3 is a cross-sectional view of a through hole of a printed circuit board according to another embodiment of the present invention, and FIG. 4 is a cross-sectional view of a through hole of a printed circuit board according to another embodiment of the present invention.
5 is a view showing graphene oxide for synthesizing charged and reduced graphene oxide in a method for surface treatment of a through hole in a printed circuit board according to an embodiment of the present invention, and FIG. 6 is a negatively charged and reduced graphene oxide. It is a view showing graphene oxide, and FIGS. 7 and 8 are diagrams showing positively charged and reduced graphene oxide obtained by reducing the graphene oxide intermediate product and the intermediate product in which the graphene oxide is treated with a cationic functional group, respectively .
Figure 9a is an image of stacking positively charged and reduced graphene oxide on the surface of polystyrene particles, Figure 9b is negatively charged and reduced graphene oxide on the surface of polystyrene particles on which the positively charged and reduced graphene oxide is stacked. 9c is an image of stacking positively charged and reduced graphene oxide on the surface of polystyrene particles on which negatively charged and reduced graphene oxide is stacked, 9d is positively charged and reduced graphene oxide It is an image of stacking negatively charged and reduced graphene oxide on the surface of polystyrene particles on which fins are stacked, and FIG. 10 is positively charged and reduced graphene oxide and negatively charged and reduced graphene oxide on the surface of polystyrene particles, respectively. It is a graph showing the potential characteristics after stacking.

이하, 첨부된 도면을 참조하여 본 발명의 실시형태를 설명한다. 그러나, 본 발명의 실시형태는 여러가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 이하 설명하는 실시형태로 한정되는 것은 아니다. 본 발명의 실시형태는 당업계에서 통상의 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위해서 제공되는 것이다. 첨부된 도면에서 특정 패턴을 갖도록 도시되거나 소정두께를 갖는 구성요소가 있을 수 있으나, 이는 설명 또는 구별의 편의를 위한 것이므로 특정패턴 및 소정두께를 갖는다고 하여도 본 발명이 도시된 구성요소에 대한 특징만으로 한정되는 것은 아니다.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, the embodiment of the present invention may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. Embodiments of the present invention are provided in order to more completely explain the present invention to those of ordinary skill in the art. Although there may be components shown to have a specific pattern or a predetermined thickness in the accompanying drawings, this is for convenience of explanation or distinction, so even if the present invention has a specific pattern and a predetermined thickness, the characteristics of the components shown in the present invention It is not limited to

도 1은 본 발명의 일실시예에 따른 인쇄회로기판 관통홀 표면처리방법에 따라 관통홀에 하전되고 환원된 산화그래핀층이 형성된 인쇄회로기판의 단면도이고, 도2는 관통홀에 도금층이 형성된 인쇄회로기판의 단면도이며, 도 3은 본 발명의 다른 실시예에 따른 인쇄회로기판의 관통홀의 단면도이고, 도 4는 본 발명의 또다른 실시예에 따른 인쇄회로기판의 관통홀의 단면도이다. 1 is a cross-sectional view of a printed circuit board in which a charged and reduced graphene oxide layer is formed in a through hole according to a printed circuit board through hole surface treatment method according to an embodiment of the present invention, and FIG. 2 is a printed circuit board in which a plating layer is formed in the through hole. It is a cross-sectional view of a circuit board, FIG. 3 is a cross-sectional view of a through hole of a printed circuit board according to another embodiment of the present invention, and FIG. 4 is a cross-sectional view of a through hole of a printed circuit board according to another embodiment of the present invention.

본 발명에 따른 인쇄회로기판 관통홀 표면처리방법은, 관통홀을 갖는 인쇄회로기판을 하전되고 환원된 산화그래핀을 포함하는 용액에 침지시켜 관통홀 내부에 하전되고 환원된 산화그래핀층을 형성하는 단계; 및 인쇄회로기판을 세척하는 단계;를 포함한다. The printed circuit board through-hole surface treatment method according to the present invention comprises immersing a printed circuit board having through-holes in a solution containing charged and reduced graphene oxide to form a charged and reduced graphene oxide layer inside the through-holes. step; and cleaning the printed circuit board.

본 발명에 따른 인쇄회로기판 관통홀 표면처리방법에서는 인쇄회로기판(110)의 관통홀 내부에 도금촉매로서 하전되고 환원된 산화그래핀층(120)을 형성한다. 하전되고 환원된 산화그래핀층(120)은 산화그래핀을 환원시키고 극성을 부여하여 극성을 나타내는 상태의 환원된 산화그래핀을 포함한다. 산화그래핀은 절연체이나, 산화그래핀을 환원시킨 환원된 산화그래핀(Reduced Graphene Oxide)은 전도성을 나타낸다. In the printed circuit board through-hole surface treatment method according to the present invention, a charged and reduced graphene oxide layer 120 is formed as a plating catalyst in the through-hole of the printed circuit board 110 . The charged and reduced graphene oxide layer 120 includes reduced graphene oxide in a state showing polarity by reducing graphene oxide and imparting polarity. Graphene oxide is an insulator, but reduced graphene oxide obtained by reducing graphene oxide (Reduced Graphene Oxide) exhibits conductivity.

인쇄회로기판(110)의 박형화 및 소형화에 기인하여 관통홀의 크기 또한 작아져, 미세패턴을 갖는 인쇄회로기판(110)의 관통홀은 직경이 10㎛ 미만일 수 있다. 관통홀을 도금시키기 위하여는 도금촉매를 관통홀 내부에 형성하여야 하는데, 도 3 과 같이 관통홀 내부에 요철이 형성되어 있거나, 도 4와 내측면에 경사를 갖는 돌출부가 형성되어 있는 경우에는 내부에 촉매형성이 어렵다. Due to the thinning and miniaturization of the printed circuit board 110 , the size of the through hole is also reduced, and the through hole of the printed circuit board 110 having a fine pattern may have a diameter of less than 10 μm. In order to plate the through hole, a plating catalyst must be formed inside the through hole. Catalyst formation is difficult.

도 3의 관통홀과 같이 요철이 형성된 경우에는 입자가 큰 촉매에 의해 인쇄회로기판(110)과 촉매와의 사이에 공극이 형성되어 도금공정 수행이후에 도금층의 불량 및 도금층 탈락이 가능하다. 그러나, 본 발명에서와 같이 도금촉매로 판상형이면서도 유연성있는 하전되고 환원된 산화그래핀을 이용하면 요철의 형태를 따라 하전되고 환원된 산화그래핀층(120)이 형성될 수 있으므로 우수한 도금층 형성과 도금층 탈락을 방지할 수 있다. When the unevenness is formed as in the through hole of FIG. 3 , a void is formed between the printed circuit board 110 and the catalyst by the catalyst having large particles, so that the plating layer may be defective and the plating layer may be removed after the plating process is performed. However, if a plate-shaped and flexible charged and reduced graphene oxide is used as a plating catalyst as in the present invention, a charged and reduced graphene oxide layer 120 can be formed according to the shape of concavities and convexities, so excellent plating layer formation and plating layer dropout can prevent

또한, 도 4에서와 같이 관통홀 형성할 때 인쇄회로기판(110)의 양면에서 레이저를 조사하는 등의 공정이 수행되어 경사를 갖는 돌출부가 중심부에 형성된 경우에는 도금촉매가 관통홀 내부를 막을 수 있다. 그러나, 본 발명에서와 같이 도금촉매로 하전되고 환원된 산화그래핀을 이용하면, 판상형의 환원된 산화그래핀이 여러층 적층되지 않아도 하전되고 환원된 산화그래핀층(120)을 형성할 수 있으므로 관통홀 내부가 막히는 문제를 방지할 수 있다. In addition, when a process such as irradiating a laser on both sides of the printed circuit board 110 is performed when forming the through hole as shown in FIG. 4 and a protrusion having a slope is formed in the center, the plating catalyst can block the inside of the through hole. have. However, if the reduced graphene oxide charged and reduced as a plating catalyst is used as in the present invention, the reduced graphene oxide layer 120 can be formed even if the plate-shaped reduced graphene oxide is not stacked. The problem of clogging the inside of the hole can be prevented.

하전되고 환원된 산화그래핀층은 환원된 산화그래핀이 10층 이하일 수 있다. The charged and reduced graphene oxide layer may have 10 or less reduced graphene oxide layers.

도 5는 본 발명의 일실시예에 따른 인쇄회로기판 관통홀 표면처리방법에 있어서 하전되고 환원된 산화그래핀을 합성하기 위한 산화그래핀을 도시한 도면이고, 도 6은 음으로 하전되고 환원된 산화그래핀을 도시한 도면이며, 도 7 및 도 8은 각각 산화그래핀을 양이온 관능기 처리한 산화그래핀 중간산물 및 중간산물을 환원시켜 얻은 양으로 하전되고 환원된 산화그래핀을 도시한 도면이다. 5 is a view showing graphene oxide for synthesizing charged and reduced graphene oxide in a method for surface treatment of a through hole in a printed circuit board according to an embodiment of the present invention, and FIG. 6 is a negatively charged and reduced graphene oxide. It is a view showing graphene oxide, and FIGS. 7 and 8 are diagrams showing positively charged and reduced graphene oxide obtained by reducing the graphene oxide intermediate product and intermediate product in which the graphene oxide is treated with a cationic functional group, respectively .

본 발명에 따른 인쇄회로기판 관통홀 표면처리방법에서는 하전되고 환원된 산화그래핀을 사용한다. 그래핀(graphene)은 탄소원자로 이루어진 2차원 탄소시트로 기존의 나노소재와 비교하여 넓은 비표면적과 뛰어난 열전도도 및 빠른 전자이동 특성을 나타낸다. 그래핀은 그라파이트를 물리적으로 한층씩 분리하여 얻을 수 있는데 이러한 방식은 대량생산이 부적합하고, 대면적 그래핀 제조가 불가능하다. 또다른 방법으로는 그라파이트의 화학적 박리방법, 즉 산화과정을 통한 제조공정이 있는데, 이 방법은 제조비용이 저렴하면서 대량생산이 가능하고, 생성된 그래핀의 기능화가 가능하여 다양한 응용이 가능한 산화그래핀을 얻을 수 있다. 산화그래핀의 경우, 물리적 방법에 의한 그래핀의 경우보다 적은 층수를 가질 수 있다. In the printed circuit board through-hole surface treatment method according to the present invention, charged and reduced graphene oxide is used. Graphene is a two-dimensional carbon sheet made of carbon atoms and exhibits a large specific surface area, excellent thermal conductivity, and fast electron transfer properties compared to conventional nanomaterials. Graphene can be obtained by physically separating graphite layer by layer, but this method is not suitable for mass production and it is impossible to manufacture large-area graphene. As another method, there is a chemical exfoliation method of graphite, that is, a manufacturing process through an oxidation process, which can be mass-produced with low manufacturing cost, and functionalization of the produced graphene is possible, so that various applications are possible. You can get a pin. In the case of graphene oxide, it may have a smaller number of layers than in the case of graphene by a physical method.

산화과정을 통해 얻은 산화그래핀의 표면에는 에폭시기(epoxy), 히드록시기(hydroxyl), 카르보닐기(carbonyl), 또는 카르복시기(carboxy) 등의 여러 가지 관능기들이 존재한다(도 5). 관능기들의 존재로 산화그래핀은 절연체로 사용된다. 이러한 산화그래핀을 관통홀 도금촉매로 사용하기 위해서는 산화그래핀을 환원시켜 환원된 산화그래핀(Reduced Graphene Oxide, rGO)으로 사용한다. 특히, 본 발명에서는 환원된 산화그래핀 제조시 극성을 부여하여 극성을 띠는 환원된 산화그래핀을 사용할 수 있다. Various functional groups such as an epoxy group, a hydroxyl group, a carbonyl group, or a carboxy group exist on the surface of the graphene oxide obtained through the oxidation process (FIG. 5). Due to the presence of functional groups, graphene oxide is used as an insulator. In order to use such graphene oxide as a through-hole plating catalyst, graphene oxide is reduced and used as reduced graphene oxide (rGO). In particular, in the present invention, reduced graphene oxide having polarity may be used by imparting polarity during the production of reduced graphene oxide.

하전되고 환원된 산화그래핀은 양으로 하전된 환원된 산화그래핀 및 음으로 하전된 환원된 산화그래핀 중 어느 하나일 수 있다. The charged reduced graphene oxide may be any one of positively charged reduced graphene oxide and negatively charged reduced graphene oxide.

음으로 하전된 환원된 산화그래핀은 표면전하가 COO-관능기에 의해 나타나는 것일 수 있다. 음으로 하전된 산화그래핀은 산화그래핀이 NH4OH분위기 하에서 히드라진에 의해 환원된 것일 수 있다. 히드라진은 산화그래핀의 가장자리보다 내부 표면의 산소관능기들의 환원작용을 돕는 환원제이다. The negatively charged reduced graphene oxide may have a surface charge represented by a COO - functional group. Negatively charged graphene oxide may be graphene oxide reduced by hydrazine under NH 4 OH atmosphere. Hydrazine is a reducing agent that helps reduce the oxygen functional groups on the inner surface rather than the edge of graphene oxide.

산화그래핀을 히드라진으로 환원하면 산화그래핀 시트끼리의 반 데르 발스 힘 때문에 시트끼리의 re-stacking 현상이 일어난다. 따라서 NH4OH 분위기에서 환원을 하면 -COOH가 -COO-로 존재하기 때문에 음의 전하를 띄는 환원된 산화그래핀을 얻을 수 있다(도 6).When graphene oxide is reduced with hydrazine, re-stacking between the graphene oxide sheets occurs due to the van der Waals force between the graphene oxide sheets. Therefore, when the NH 4 OH in a reducing atmosphere is -COOH -COO - can be obtained to the presence of oxidized graphene reduced striking a negative charge due to (6).

양으로 하전된 환원된 산화그래핀은 표면전하가 NH3 +관능기에 의해 나타나는 것일 수 있다. 양으로 하전된 환원된 산화그래핀은 산화그래핀을 1-(3-디메틸아미노프로필)-3-에틸카르보디이미드 메티오디드(1-(3-dimethylaminopropyl)-3-ethylcarbodiimide methiodide) 및 에틸렌디아민으로 처리하여 양으로 하전된 산화그래핀을 얻는 단계; 및 히드라진으로 환원시키는 단계;를 수행하여 얻을 수 있다.The positively charged reduced graphene oxide may have a surface charge represented by an NH 3 + functional group. The positively charged reduced graphene oxide converts graphene oxide into 1-(3-dimethylaminopropyl)-3-ethylcarbodiimide methiodide (1-(3-dimethylaminopropyl)-3-ethylcarbodiimide methiodide) and ethylenediamine. processing to obtain positively charged graphene oxide; and reducing with hydrazine;

산화그래핀을 1-(3-디메틸아미노프로필)-3-에틸카르보디이미드 메티오디드와 에틸렌디아민으로 처리하면 -COOH 관능기를 양의 전하를 갖는 NH3+로 바꿔준다(도 7). 이후, 히드라진으로 환원처리를 해주면 내부표면의 산소관능기들이 환원되어 가장자리에 양전하를 갖는 환원된 산화그래핀을 얻는다(도 8).When graphene oxide is treated with 1-(3-dimethylaminopropyl)-3-ethylcarbodiimide methiodide and ethylenediamine, the -COOH functional group is changed to NH 3+ having a positive charge (FIG. 7). Thereafter, when a reduction treatment is performed with hydrazine, oxygen functional groups on the inner surface are reduced to obtain reduced graphene oxide having a positive charge at the edge (FIG. 8).

도 9a는 폴리스티렌 입자 표면에 양으로 하전되고 환원된 산화그래핀을 적층한 이미지이고, 도 9b는 양으로 하전되고 환원된 산화그래핀이 적층된 폴리스티렌 입자 표면에 음으로 하전되고 환원된 산화그래핀을 적층한 이미지이고, 도 9c는 음으로 하전되고 환원된 산화그래핀이 적층된 폴리스티렌 입자 표면에 양으로 하전되고 환원된 산화그래핀을 적층한 이미지이고, 9d는 양으로 하전되고 환원된 산화그래핀이 적층된 폴리스티렌 입자 표면에 음으로 하전되고 환원된 산화그래핀을 적층한 이미지이고, 도 10은 폴리스티렌 입자 표면에 각각 양으로 하전되고 환원된 산화그래핀 및 음으로 하전되고 환원된 산화그래핀을 적층한 후의 전위특성을 도시한 그래프이다. Figure 9a is an image of stacking positively charged and reduced graphene oxide on the surface of polystyrene particles, Figure 9b is negatively charged and reduced graphene oxide on the surface of polystyrene particles on which the positively charged and reduced graphene oxide is stacked. 9c is an image of stacking positively charged and reduced graphene oxide on the surface of polystyrene particles on which negatively charged and reduced graphene oxide is stacked, 9d is positively charged and reduced graphene oxide It is an image of stacking negatively charged and reduced graphene oxide on the surface of polystyrene particles on which fins are stacked, and FIG. 10 is positively charged and reduced graphene oxide and negatively charged and reduced graphene oxide on the surface of polystyrene particles, respectively. It is a graph showing the potential characteristics after stacking.

하전되고 환원된 산화그래핀이 다양한 형태의 관통홀 내부에 적층될 수 있는지 확인하기 위하여 폴리스티렌 입자 표면에 각각의 극성을 갖는 하전되고 하전되고 환원된 산화그래핀층을 형성하였다. 도 9a는 폴리스티렌 입자 표면에 양으로 하전된 환원된 산화그래핀 층을 형성한 것이고, 도 9b는 그 위에 다시 음으로 하전된 환원된 산화그래핀 층을 형성한 것, 도 9c는 그 위에 다시 양으로 하전된 환원된 산화그래핀 층을 형성한 것, 도 9d는 그 위에 다시 음으로 하전된 환원된 산화그래핀 층을 형성하였는데, 각각의 층 형성시 서로 반대 전하로 하전되어 있으므로 박막층 형성이 가능하였다. In order to check whether the charged and reduced graphene oxide can be stacked inside various types of through-holes, charged, charged, and reduced graphene oxide layers having respective polarities were formed on the surface of polystyrene particles. Figure 9a is a positively charged reduced graphene oxide layer is formed on the surface of the polystyrene particles, Figure 9b is a negatively charged reduced graphene oxide layer is formed thereon again, Figure 9c is a positive charge thereon again Forming a reduced graphene oxide layer charged with , FIG. 9d shows that a reduced graphene oxide layer that is negatively charged again is formed thereon, and since each layer is charged with opposite charges when forming, a thin film layer can be formed did.

도 10은 폴리스티렌 입자 표면에 각각 양으로 하전되고 환원된 산화그래핀 및 음으로 하전되고 환원된 산화그래핀을 적층한 후의 전위특성을 도시한 그래프이다. 폴리스티렌 입자는 -14mV의 전위를 나타내는데, 양으로 하전된 환원된 산화그래핀 층이 형성된 후에는 8.67mv의 전위를 나타내었다. 음으로 하전된 환원된 산화그래핀 층이 더 형성된 후에는 -15.45mv, 다시 양으로 하전된 환원된 산화그래핀 층이 형성된 후에는 12/.07mv, 다시 음으로 하전된 환원된 산화그래핀 층이 형성된 후에는 -9.92mv, 다시 양으로 하전된 환원된 산화그래핀 층이 형성된 후에는 14.64mv, 다시 음으로 하전된 환원된 산화그래핀 층이 형성된 후에는 -16.10mv의 전위를 나타내어, 각 하전되고 환원된 산화그래핀이 폴리스티렌 입자 표면에 층을 형성하였음을 확인할 수 있다. 10 is a graph showing potential characteristics after stacking positively charged and reduced graphene oxide and negatively charged and reduced graphene oxide on the surface of polystyrene particles, respectively. The polystyrene particles exhibited a potential of -14 mV, and after the positively charged reduced graphene oxide layer was formed, it exhibited a potential of 8.67 mV. After a further negatively charged reduced graphene oxide layer is formed, -15.45mv, after a positively charged reduced graphene oxide layer is formed again, 12/.07mv, a negatively charged reduced graphene oxide layer again After the formation of -9.92mv, after the positively charged reduced graphene oxide layer is formed again, 14.64mv, after the negatively charged reduced graphene oxide layer is formed again, it shows a potential of -16.10mv, each It can be confirmed that the charged and reduced graphene oxide formed a layer on the polystyrene particle surface.

본 발명의 다른 측면에 따르면, 관통홀을 갖는 인쇄회로기판을 하전되고 환원된 산화그래핀을 포함하는 용액에 침지시켜 관통홀 내부에 하전되고 환원된 산화그래핀층을 형성하는 단계; 및 인쇄회로기판을 세척하는 단계;를 포함하는 인쇄회로기판 관통홀 표면처리방법에 의해 관통홀 내부에 하전되고 환원된 산화그래핀층이 형성되어 표면처리된 인쇄회로기판이 제공된다.According to another aspect of the present invention, the method comprising: immersing a printed circuit board having a through hole in a solution containing charged and reduced graphene oxide to form a charged and reduced graphene oxide layer inside the through hole; and washing the printed circuit board; a charged and reduced graphene oxide layer is formed in the through-hole by the printed circuit board through-hole surface treatment method comprising a surface-treated printed circuit board is provided.

본 발명의 또다른 측면에 따르면, 관통홀을 갖는 인쇄회로기판을 하전되고 환원된 산화그래핀을 포함하는 용액에 침지시켜 관통홀 내부에 하전되고 환원된 산화그래핀층을 형성하는 단계; 및 인쇄회로기판을 세척하는 단계;를 포함하는 인쇄회로기판 관통홀 표면처리방법에 의해 관통홀의 표면이 처리된 인쇄회로기판을 준비하는 단계; 및 인쇄회로기판을 도금액이 침지시켜 무전해도금하는 단계;를 포함하는 인쇄회로기판 도금방법이 제공된다.According to another aspect of the present invention, the method comprising: immersing a printed circuit board having a through hole in a solution containing charged and reduced graphene oxide to form a charged and reduced graphene oxide layer inside the through hole; and washing the printed circuit board; preparing a printed circuit board in which the surface of the through hole is treated by a printed circuit board through hole surface treatment method comprising; and electroless plating by immersing the printed circuit board in a plating solution.

본 발명의 또다른 측면에 따르면, 관통홀을 갖는 인쇄회로기판을 하전되고 환원된 산화그래핀을 포함하는 용액에 침지시켜 관통홀 내부에 하전되고 환원된 산화그래핀층을 형성하는 단계; 및 인쇄회로기판을 세척하는 단계;를 포함하는 인쇄회로기판 관통홀 표면처리방법에 의해 관통홀의 표면이 처리된 인쇄회로기판을 준비하는 단계; 및 인쇄회로기판을 도금액이 침지시켜 무전해도금하는 단계;를 포함하는 인쇄회로기판 도금방법에 의해 도금층이 형성된 다층 인쇄회로기판이 제공된다.According to another aspect of the present invention, the method comprising: immersing a printed circuit board having a through hole in a solution containing charged and reduced graphene oxide to form a charged and reduced graphene oxide layer inside the through hole; and washing the printed circuit board; preparing a printed circuit board in which the surface of the through hole is treated by a printed circuit board through hole surface treatment method comprising; and electroless plating by immersing the printed circuit board in a plating solution. There is provided a multilayer printed circuit board having a plating layer formed thereon by a printed circuit board plating method comprising a.

이상, 본 발명의 실시예들에 대하여 설명하였으나, 해당 기술 분야에서 통상의 지식을 가진 자라면 특허청구범위에 기재된 본 발명의 사상으로부터 벗어나지 않는 범위 내에서, 구성 요소의 부가, 변경, 삭제 또는 추가 등에 의해 본 발명을 다양하게 수정 및 변경시킬 수 있을 것이며, 이 또한 본 발명의 권리범위 내에 포함된다고 할 것이다.In the above, although embodiments of the present invention have been described, those of ordinary skill in the art can add, change, delete or add components within the scope that does not depart from the spirit of the present invention described in the claims. It will be said that various modifications and changes of the present invention can be made by, and this is also included within the scope of the present invention.

110 인쇄회로기판
120 하전되고 환원된 산화그래핀층
130 도금층110 printed circuit board
120 Charged and Reduced Graphene Oxide Layer
130 plating layer

Claims (12)

관통홀을 갖는 인쇄회로기판을 하전되고 환원된 산화그래핀을 포함하는 용액에 침지시켜 관통홀 내부에 하전되고 환원된 산화그래핀층을 형성하는 단계; 및
인쇄회로기판을 세척하는 단계;를 포함하는 인쇄회로기판 관통홀 표면처리방법.
immersing a printed circuit board having a through hole in a solution containing charged and reduced graphene oxide to form a charged and reduced graphene oxide layer inside the through hole; and
A printed circuit board through-hole surface treatment method comprising a; washing the printed circuit board.
 청구항 1에 있어서,
하전되고 환원된 산화그래핀은 양으로 하전된 환원된 산화그래핀 및 음으로 하전된 환원된 산화그래핀 중 어느 하나인 것을 특징으로 하는 인쇄회로기판 관통홀 표면처리방법.
The method according to claim 1,
The charged and reduced graphene oxide is a printed circuit board through-hole surface treatment method, characterized in that any one of positively charged reduced graphene oxide and negatively charged reduced graphene oxide.
 청구항 2에 있어서,
양으로 하전된 환원된 산화그래핀은 표면전하가 NH3 +관능기에 의해 나타나는 것을 특징으로 하는 인쇄회로기판 관통홀 표면처리방법.
3. The method according to claim 2,
The positively charged reduced graphene oxide is a printed circuit board through-hole surface treatment method, characterized in that the surface charge is represented by NH 3 + functional group.
청구항 3에 있어서,
양으로 하전된 환원된 산화그래핀은
산화그래핀을 1-(3-디메틸아미노프로필)-3-에틸카르보디이미드 메티오디드(1-(3-dimethylaminopropyl)-3-ethylcarbodiimide methiodide) 및 에틸렌디아민으로 처리하여 양으로 하전된 산화그래핀을 얻는 단계; 및
히드라진으로 환원시키는 단계;를 수행하여 얻는 것을 특징으로 하는 인쇄회로기판 관통홀 표면처리방법.
4. The method according to claim 3,
The reduced positively charged graphene oxide is
Positively charged graphene oxide was obtained by treating graphene oxide with 1-(3-dimethylaminopropyl)-3-ethylcarbodiimide methiodide (1-(3-dimethylaminopropyl)-3-ethylcarbodiimide methiodide) and ethylenediamine. obtaining; and
Reduction with hydrazine; Printed circuit board through-hole surface treatment method, characterized in that obtained by performing.
 청구항 2에 있어서,
음으로 하전된 환원된 산화그래핀은 표면전하가 COO-관능기에 의해 나타나는 것을 특징으로 하는 인쇄회로기판 관통홀 표면처리방법.
3. The method according to claim 2,
Negatively charged reduced graphene oxide is a printed circuit board through-hole surface treatment method, characterized in that the surface charge is represented by the COO - functional group.
청구항 5에 있어서,
음으로 하전된 산화그래핀은 산화그래핀이 NH4OH분위기 하에서 히드라진에 의해 환원된 것을 특징으로 하는 인쇄회로기판 관통홀 표면처리방법.
6. The method of claim 5,
Negatively charged graphene oxide is a printed circuit board through-hole surface treatment method, characterized in that the graphene oxide is reduced by hydrazine under an NH 4 OH atmosphere.
청구항 1의 인쇄회로기판 관통홀 표면처리방법에 의해 관통홀 내부에 하전되고 환원된 산화그래핀층이 형성되어 표면처리된 인쇄회로기판.
A printed circuit board surface-treated by forming a charged and reduced graphene oxide layer inside the through hole by the printed circuit board through-hole surface treatment method of claim 1 .
 청구항 7에 있어서,
관통홀은 내측면에 요철이 형성된 것을 특징으로 하는 인쇄회로기판.
8. The method of claim 7,
The through hole is a printed circuit board, characterized in that the unevenness is formed on the inner surface.
 청구항 7에 있어서,
관통홀은 내측면에 경사를 갖는 돌출부가 형성된 것을 인쇄회로기판.
8. The method of claim 7,
The through-hole is a printed circuit board in which a protrusion having a slope is formed on the inner surface.
 청구항 7에 있어서,
하전되고 환원된 산화그래핀층은 환원된 산화그래핀이 10층 이하인 것을 특징으로 하는 인쇄회로기판.
8. The method of claim 7,
The charged and reduced graphene oxide layer is a printed circuit board, characterized in that less than 10 layers of reduced graphene oxide.
 청구항 1에 따른 인쇄회로기판 관통홀 표면처리방법에 의해 관통홀의 표면이 처리된 인쇄회로기판을 준비하는 단계; 및
인쇄회로기판을 도금액이 침지시켜 무전해도금하는 단계;를 포함하는 인쇄회로기판 도금방법.
Preparing a printed circuit board in which the surface of the through hole is treated by the printed circuit board through hole surface treatment method according to claim 1; and
A printed circuit board plating method comprising a; electroless plating by immersing the printed circuit board in a plating solution.
 청구항 11의 인쇄회로기판 도금방법에 의해 도금층이 형성된 다층 인쇄회로기판.A multilayer printed circuit board on which a plating layer is formed by the printed circuit board plating method of claim 11 .
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KR101418034B1 (en) * 2013-12-27 2014-08-06 (주)오알켐 Method for manufacturing multi layer pcb
TWI586849B (en) * 2016-08-04 2017-06-11 國立中興大學 A method of reducing the graphene layer of the oxidized graphene layer on the surface of the substrate and the hole wall of the aspect ratio hole and the adjusting liquid used in the method
KR20180084302A (en) * 2017-01-16 2018-07-25 한솔테크닉스(주) Board and the insulation structure formation method that have via hole insulation structure

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