KR20210031367A - Controller and operating method thereof - Google Patents

Abstract

A controller for controlling a nonvolatile memory device according to one embodiment of the present invention may comprise: a first memory temporarily storing user data; a second memory including a plurality of memory areas including at least one meta area for storing meta data and at least one spare area; and a processor controlling the first memory and the second memory and performing first start-gap wear leveling using at least one spare area included in the second memory as a gap.

Description

Controller and its operation method {CONTROLLER AND OPERATING METHOD THEREOF}

The present invention relates to a semiconductor device, and more particularly, to a controller and a method of operating the same.

Recently, the paradigm for the computer environment is shifting to ubiquitous computing, which enables computer systems to be used anytime, anywhere. For this reason, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers is increasing rapidly. Such portable electronic devices generally use a memory system using a memory device. The memory system is used to store data used in portable electronic devices.

A memory system using a memory device has the advantage of excellent stability and durability because there is no mechanical driving part, and the access speed of information is very fast and power consumption is low. Memory systems having such advantages include Universal Serial Bus (USB) memory devices, memory cards having various interfaces, Universal Flash Storage (UFS) devices, and solid state drives.

An embodiment of the present invention is to provide a technique for improving the performance of a memory system using start-gap wear leveling.

A controller according to an embodiment of the present technology is a controller that controls a nonvolatile memory device, comprising: a first memory temporarily storing user data; A second memory including at least one meta area for storing meta data and a plurality of memory areas including at least one spare area; And a processor that controls the first memory and the second memory, and performs first start-gap wear leveling by using at least one spare area included in the second memory as a gap. Can include.

A method of operating a controller according to an embodiment includes a first memory for temporarily storing user data, and a second memory including a plurality of memory areas including at least one meta area and at least one spare area for storing meta data. A method of operating a controller comprising: the controller. Determining whether the number of times of accessing each of the at least one meta area in which the meta data is stored is greater than or equal to a first reference value; And a first start-gap by using at least one spare area as a gap for at least one meta area when the total sum of the number of accesses to the meta data is equal to or greater than a first reference value. It may include; performing wear leveling.

According to an embodiment of the present invention, performance of a memory system may be improved by using start-gap wear leveling.

1 is a diagram illustrating a configuration of a memory system according to an exemplary embodiment.
2 to 6 are diagrams for explaining a start-gap wear leveling operation of a second memory according to an exemplary embodiment.
7 and 8 are flowcharts illustrating a start-gap wear leveling operation of a second memory according to an exemplary embodiment.
9 is a diagram illustrating a data processing system including a solid state drive (SSD) according to an exemplary embodiment.
10 is a view showing an exemplary configuration of the controller of FIG. 9;
11 is a diagram illustrating a data processing system including a memory system according to an exemplary embodiment.
12 is a diagram illustrating a data processing system including a memory system according to an exemplary embodiment.
13 is a diagram illustrating a network system including a memory system according to an exemplary embodiment.
14 is a block diagram schematically illustrating a nonvolatile memory device included in a memory system according to an exemplary embodiment.

Hereinafter, an embodiment of the present technology will be described with reference to the accompanying drawings.

1 is a diagram illustrating a configuration of a memory system according to an exemplary embodiment.

1, the memory system 10 according to an embodiment is accessed by a host 20 such as a mobile phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, an in-vehicle infotainment system, etc. Data can be saved.

The memory system 10 may be manufactured with any one of various types of storage devices according to an interface protocol connected to the host 20. For example, the memory system 10 is a solid state drive (SSD), MMC, eMMC, RS-MMC, micro-MMC type multimedia card, SD, mini-SD, micro-SD Secure digital card, universal storage bus (USB) storage device, universal flash storage (UFS) device, personal computer memory card international association (PCMCIA) card type storage device, and peripheral component interconnection (PCI) card type Storage device, PCI-E (PCI-express) card type storage device, CF (compact flash) card, smart media card, memory stick, etc. Can be configured.

The memory system 10 may be manufactured in any one of various types of packages. For example, the memory system 10 is a POP (package on package), SIP (system in package), SOC (system on chip), MCP (multi-chip package), COB (chip on board), WFP (wafer- level fabricated package), a wafer-level stack package (WSP), and the like.

The memory system 10 may include a nonvolatile memory device 100 and a controller 200.

The nonvolatile memory device 100 may operate as a storage medium of the memory system 10. Depending on the type of memory cell, the nonvolatile memory device 100 includes a NAND flash memory device, a NOR flash memory device, a ferroelectric random access memory (FRAM) using a ferroelectric capacitor, and a tunneling magneto. -resistive, TMR) film using magnetic random access memory (MRAM), phase change random access memory (PRAM) using chalcogenide alloys, transition metal oxide It may be configured with any one of various types of nonvolatile memory devices such as resistive random access memory (ReRAM).

1 illustrates that the memory system 10 includes one nonvolatile memory device 100, this is for convenience of description, and the memory system 10 may include a plurality of nonvolatile memory devices. Also, the present invention can be equally applied to the memory system 10 including a plurality of nonvolatile memory devices.

The nonvolatile memory device 100 includes a memory cell array (not shown) having a plurality of memory cells disposed in regions where a plurality of bit lines (not shown) and a plurality of word lines (not shown) cross each other. Not). The memory cell array may include a plurality of memory blocks, and each of the plurality of memory blocks may include a plurality of pages.

Each memory cell of the memory cell array may operate as a single level cell (SLC) storing 1 bit of data, and a multi level cell (MLC) capable of storing 2 or more bits of data. . The multi-level cell XLC may store 2 bits of data, 3 bits of data, and 4 bits of data. In general, a memory cell storing 2 bits of data is referred to as a multi-level cell (MLC), a memory cell storing 3 bits of data is referred to as a triple level cell (TLC), and a 4 bit data is referred to as a triple level cell (TLC). A memory cell to be stored is referred to as a quad level cell (QLC). However, in the present embodiment, for convenience of description, a memory cell that stores 2 to 4 bits of data will be collectively referred to as a multi-level cell XLC.

The memory cell array may include at least one of a single level cell SLC and a multi level cell XLC. Further, the memory cell array may include memory cells having a 2D horizontal structure or may include memory cells having a 3D vertical structure.

The controller 200 may control all operations of the memory system 10 by driving firmware or software loaded in the first memory 230. The controller 200 may decode and drive an instruction or algorithm in the form of code such as firmware or software. The controller 200 may be implemented in hardware or a combination of hardware and software.

The controller 200 may include a host interface 210, a processor 220, a first memory 230, a second memory 240, and a memory interface 250. Although not shown in FIG. 1, the controller 200 generates a parity code by encoding the write data provided from the host to an error correction code (ECC), and parity the read data read from the nonvolatile memory device 100. An ECC engine that decodes an error correction code (ECC) using a parity) code may be further included.

The host interface 210 may interface between the host 20 and the memory system 10 in response to the protocol of the host 20. For example, the host interface 210 is a universal serial bus (USB), universal flash storage (UFS), a multimedia card (MMC), a parallel advanced technology attachment (PATA), a serial advanced technology attachment (SATA), a small computer (SCSI). system interface), serial attached SCSI (SAS), peripheral component interconnection (PCI), and PCI express (PCI-E) protocol.

The processor 220 may be configured in a form such as a micro control unit (MCU) and a central processing unit (CPU). The processor 220 may process a request transmitted from the host 20. In order to process the request transmitted from the host 20, the processor 220 drives an instruction or algorithm in the form of code loaded in the memory 230, that is, the firmware, and the host interface 210, the memory ( Internal functional blocks such as 230 and the memory interface 250 and the nonvolatile memory device 100 may be controlled.

The processor 220 generates control signals to control the operation of the nonvolatile memory device 100 based on requests transmitted from the host 20, and transmits the generated control signals to the nonvolatile memory through the memory interface 250. It can be provided to the device 100.

The first memory 230 includes an area used as a command queue (CMDQ) for queuing a command corresponding to a request provided from the host 20, a write data buffer temporarily storing write data, and read data. It can be used as a read data buffer that is temporarily stored.

In one embodiment, the first memory 230 may be configured as a random access memory such as dynamic random access memory (DRAM) or static random access memory (SRAM).

In an embodiment, the first memory 230 may have a higher degree of integration than the second memory 240. That is, the first memory 230 may have a larger data storage capacity than the second memory 240.

In an embodiment, the first memory 230 may have a higher data throughput than the second memory 240 and thus may operate at a higher speed than the second memory 240.

The second memory 240 may store firmware driven by the processor 220. In addition, the second memory 240 may store data necessary for driving the firmware, for example, metadata. That is, the second memory 240 may operate as a working memory of the processor 220. Also, the second memory 240 may operate as a map cache buffer in which map data is cached.

In an embodiment, the second memory 240 may be formed of a memory such as a phase change memory (PCRAM) or the like.

The memory interface 250 may control the nonvolatile memory device 100 under the control of the processor 220. The memory interface 250 may be referred to as a memory controller. The memory interface 250 may provide control signals to the nonvolatile memory device 100. The control signals may include commands and addresses for controlling the nonvolatile memory device 100. The memory interface 250 may provide data stored in the data buffer to the nonvolatile memory device 100 or may store data transmitted from the nonvolatile memory device 100 in the data buffer. The data buffer may be an area allocated to the first memory 230.

FIG. 2 is a diagram illustrating a second memory illustrated in FIG. 1.

The second memory 240 may store user data in the nonvolatile memory device 100 or meta data used to manage the nonvolatile memory device 100. The second memory 240 may include a plurality of memory regions (memory region-01 to memory region_M) to store meta data, and each memory region (memory region-01 to memory region_M) includes a plurality of sub regions (memory region-01 to memory region_M). It can be composed of sub region_01 to sub region_N).

In one embodiment, a plurality of memory regions (memory region-01 to memory region_M) included in the second memory 240 are meta regions and gaps for performing a start-gap wear leveling operation. ) May include at least one spare area.

In an embodiment, sub-regions (sub regions_01 to sub region_N) included in each of the plurality of memory regions included in the second memory 240 are sub-meta regions in which meta data is stored and a start-gap It may include at least one sub spare area used as a gap for performing a wear leveling operation.

In an embodiment, a plurality of memory regions (memory region-01 to memory region_M) included in the second memory 240 are cold meta regions in which meta data having an access number less than a first reference value are stored and a first reference value It may include at least one hot meta area in which meta data having more than one access number is stored.

3 is a diagram illustrating start-gap wear leveling of a second memory according to an exemplary embodiment.

Referring to FIG. 3A, the second memory 240 may include, for example, six memory regions _01 to memory region_06. Of the six memory regions, five memory regions (memory region_01 to memory region_05) may be a meta region in which meta data is stored, and the other memory region (memory region 06) may be a spare region. In this case, it is assumed that a memory region 05 (memory region_05) among the memory regions_01 to memory region_05 is a memory region in which the start-gap wear leveling operation is started, and the gap is a memory region 06 (memory region_06).

Referring to FIG. 3(b), the controller 200 starts start-gap wear leveling when the total number of accesses to the metadata stored in the memory regions_01 to memory region_05 is equal to or greater than the first reference value. I can. First, meta data stored in a memory region 05 (memory region_05) in which the start-gap wear leveling operation is started may be migrated to a memory region 06 (memory region_06) that is a gap region. It is obvious that the first reference value may be set or changed at the time of manufacture or use of the memory system 10. As a result of the start-gap wear leveling operation, the memory region 05 (memory region_05) may be converted to a spare region, and the memory region 06 (memory region_06) may be converted to a meta region. In addition, memory region 04 (memory region_04) may be selected as a meta region to be subjected to a subsequent start-gap wear leveling operation, and memory region 05 (memory region_05) is selected as a gap for subsequent start-gap wear leveling. Can be.

That is, the memory region in which the start-gap wear leveling has already been performed by sequentially decreasing or increasing the address of the memory region_05 where the start-gap wear leveling starts, or by calculating the address of the memory region using a set address calculation formula. One of the remaining memory areas except for may be selected as the target meta area for the subsequent start-gap wear leveling operation, and one of the memory areas converted to the gap area after the start-gap wear leveling operation has already been performed is the subsequent start-gap wear. It can be selected as the gap of the leveling operation.

3(c), the controller 200 migrates the meta data stored in the memory region 04 (memory region_04), which is the target of the start-gap wear leveling operation, to the gap region, that is, the memory region 05 (memory region_05). I can. Accordingly, the memory region 04 (memory region_04) may be converted into a spare region, and the memory region 05 (memory region_05) may be converted into a meta region. Also, a memory region 03 (memory region_03) may be a target for a subsequent start-gap wear leveling operation, and a memory region 04 (memory region_04) may be a gap for a subsequent start-gap wear leveling operation.

In FIG. 3, an example of performing start-gap wear leveling by selecting addresses of memory regions to be converted to spare regions (memory region_01 to memory region_05) in descending order is exemplified, but two or more spare regions are used as gaps or spare regions It goes without saying that it is possible to change and transform the address such as starting-gap wear leveling by selecting the address of in ascending order.

The start-gap wear leveling shown in FIG. 3 is performed based on the total number of accesses to the metadata stored in the memory regions (memory region_01 to memory region_05), so it may be referred to as global start-gap wear leveling. .

4 is a conceptual diagram illustrating a start-gap wear leveling method of a second memory according to an embodiment, and illustrates a start-gap wear leveling concept for a sub-region.

Referring to FIG. 4A, an example of a memory region including 10 sub regions_01 to subregion_10 is shown. Each sub region (sub region_01 to sub region_10) may include a sub meta region in which meta data (meta data_01 to meta data_0) are stored and a spare region (Gap (spare)). In this case, it is assumed that the sub region_09 of the sub regions_01 to sub region_10 is the sub region where the start-gap wear leveling operation is started, and the gap is the sub region_10.

Referring to FIG. 4(b), the controller 200 starts start-gap wear leveling when the total number of accesses to the meta data stored in the sub-regions (sub region_01 to sub region_09) exceeds the second reference value. I can. First, the meta data 09 stored in the sub region 09 (sub region_09) in which the start-gap wear leveling operation is started may be migrated to the sub region 10 (sub region_10). Accordingly, the sub region 09 (sub region_09) may be converted to a gap for the subsequent start-gap wear leveling operation, and the sub region 08 (sub region_08) may be a target of the subsequent start-gap wear leveling operation.

That is, the address of the sub-region where start-gap wear leveling is started (sub region_09) is sequentially decreased or increased, or the address of the sub-region is calculated according to a set address calculation formula, and the start-gap wear leveling is already performed. One of the remaining sub-regions except for may be selected as the target meta-region for the subsequent start-gap wear leveling operation, and one of the sub-regions converted to the gap region after the start-gap wear leveling operation has already been performed is the subsequent start-gap wear. It can be selected as the gap of the leveling operation.

Referring to FIG. 4C, the controller 200 may migrate the meta data 08 stored in the sub region 08 (sub region_08) to the sub region 09 (sub region_09). Accordingly, sub-region 0 (sub region_08) 8 may be selected as a gap for a subsequent start-gap wear leveling operation, and sub region 07 (sub region_07) may be a target for a subsequent start-gap wear leveling operation.

In FIG. 4, start-gap wear leveling in which addresses of sub-regions to be converted to sub-regions (sub region_01 to sub region_09) are selected in descending order has been described as an example, but two or more sub-regions are selected as gaps or addresses of sub-regions Of course, various modifications and changes are possible, such as selecting in ascending order.

The start-gap wear leveling shown in FIG. 4 is performed based on the total number of accesses to the meta data stored in each sub region (sub region_01 to sub region_09) for each memory region (memory region_01 to memory region_05). ) It may be referred to as start-gap wear leveling.

5 and 6 are diagrams for explaining start-gap wear leveling of a second memory according to an exemplary embodiment.

5 and 6 illustrate three memory regions_01 to memory region_03 of a plurality of memory regions_01 to memory region_M of the second memory 240.

Each memory region (memory region_01 to memory region_03) may include nine sub regions (sub region_01 to sub region_09). Here, the memory region 01 (memory region_01) and the memory region 02 (memory region_02) are cold meta regions that store meta data having the number of accesses less than the first reference value, and the memory region 03 (memory region_03) is at least one sub spare. The following describes a situation that includes an area as an example. In FIG. 5A, a memory region 03 (memory region_03) includes one sub-meta region (sub region_01) and eight sub-spare regions (sub region_02 to sub region_09), and is sub-meta region 01 (sub region_01). Although the case in which the meta data (meta data_A) accessed by more than 3 reference values is stored is illustrated, the present invention is not limited thereto, and the memory region 03 (memory region_03) may be formed only as a sub spare region.

In this situation, a method of assembling hot data in the cold meta region (memory region_01, memory region_02) into another memory region 03 (memory region_03) will be described.

Hot data refers to data that is continuously and frequently accessed. Accordingly, among the sub-areas included in the specific memory area, the sub-area in which access is continuously concentrated may be determined as an area storing hot meta data. In an embodiment, a sub-region in which the number of accesses to the sub-region for each memory region is equal to or greater than the third reference value may be determined as the meta region. In order to determine whether the third reference value is satisfied, when a memory area in which the total number of accesses is equal to or greater than the first set value is detected, the number of accesses to a specific sub area within the corresponding memory area is set to a third reference value (=first setting). Values*α, α can be checked if they are greater than or equal to 0<α<1. Here, α may be set or changed at the time of manufacture or use of the memory system 10 according to the hot data classification criterion.

For example, when the first set value is 10,000 and α=0.6, the meta data in the sub-region having the number of accesses of 6,000 or more, which is the third reference value, may be classified as hot data.

If the total number of accesses to memory region 01 (memory region_01) is 10,000 times and the number of accesses to meta data (meta data_B) stored in sub region 04 (sub region_04) is 6,000, sub region 04 (sub region_04) Since the number of accesses to the remaining sub regions (sub region_01 to sub region_03, sub region_05 to sub region_09) is 4,000 times, meta data (meta data_B) stored in sub region 04 (sub region_04) may be classified as hot data.

5A, meta data B (meta data_B) stored in sub region 04 (sub region_04) of memory region 01 (memory region_01) and sub region 02 (sub region_02) of memory region 02 (memory region_02) When the number of accesses of the stored meta data C (meta data_C) becomes more than the third reference value, the controller 200 migrates the meta data B (meta data_B) and the meta data C (meta data_C) to the memory region 03 (memory region_03). You can decide what you want to do.

In FIG. 5B, the controller 200 transfers the meta data B (meta data_B) stored in the sub region 04 (sub region_04) of the memory region 01 (memory region_01) to the sub region 02 (sub region 02) of the memory region 03 (memory region_03). After migration to region_02), subregion 04 (sub region_04) of memory region 01 (memory region_01) may be invalidated. Also, the meta data C (meta data_C) stored in the sub region 02 (sub region_02) of the memory region 02 (memory region_02) is migrated to the sub region 03 (sub region_03) of the memory region 03 (memory region_03), and the memory region 02 ( The sub region 02 of the memory region_02 may be invalidated.

Through this migration operation, hot meta data, which is frequently performed in a write or read operation, may be collected into one memory region_03, and the memory region_03 may be converted into a hot meta region.

When hot metadata is collected in a specific memory region_03 as described above, global start-gap wear leveling or local start-gap wear leveling may be performed on the second memory 240.

Referring to FIG. 6 (a), the controller 200 has a total number of accesses to the meta data stored in the sub regions (sub region_01 to sub region_09) in the memory region 03 (memory region_03), which is a hot meta region, is 2 When it exceeds the reference value, local start-gap wear leveling can be started. In this case, it is assumed that the sub-regions 01 to 03 (sub regions_01 to sub region_03) are the memory regions in which the start-gap wear leveling operation is started, and the gaps are sub regions 04 to 06 (sub region_04 to sub region_06).

6(b), the controller 200 transfers meta data A to C (meta data_A to meta data_C) stored in sub regions 01 to 03 (sub region_01 to sub region_03) into sub regions 04 to 06 (sub region_04 to). sub region_06). Thereafter, the controller 200 may determine the sub-regions 04 to 06 (sub region_04 to sub region_06) of the memory region 03 (memory region_03) as a target for the subsequent start-gap wear leveling, and the sub regions 07 to 09 (sub region_07). ~sub region_09) can be determined as a gap.

6(c), the controller 200 transfers the meta data A to C (meta data_A to meta data_C) stored in the sub regions 04 to 06 (sub region_04 to sub region_06) to the sub regions 07 to 09 (sub region_07 to). sub region_09).

This is to increase the lifespan of the second memory 240 by intensively performing a wear leveling operation on metadata having a high number of accesses.

Meanwhile, when the total number of times of accessing metadata stored in the memory regions_01 to memory region_M is equal to or greater than the first reference value, global start-gap wear leveling may be started.

7 is a diagram illustrating a start-gap wear leveling operation of a second memory according to an exemplary embodiment.

Referring to FIG. 7, in step S710, the controller 200 may count the number of times of accessing metadata stored in the second memory 240.

In an embodiment, the controller 200 may count the number of times of accessing metadata included in the start-gap wear leveling target memory areas among a plurality of memory areas included in the second memory 240.

In one embodiment, the controller 200 includes the sum of the total number of accesses to the meta data stored in each of the sub regions (sub region_01 to sub region_09) for each memory region (memory region_01 to memory region_M), and the memory regions (memory region_M). Region_01~memory region_M) The total sum of the number of times the meta data is accessed can be counted.

In step S720, the controller 200 may determine whether the number of times the metadata is accessed is equal to or greater than a set reference value.

In an embodiment, the controller 200 may determine whether the sum of the total number of times of accessing metadata stored in the memory regions_01 to memory region_M is equal to or greater than the first reference value.

In one embodiment, the controller 200 determines whether the sum of the total number of accesses to the metadata stored in each of the sub-regions (sub region_01 to sub region_09) for each memory region (memory region_01 to memory region_M) is greater than or equal to the second reference value. Can be judged.

In step S730, if the number of accesses is greater than or equal to a preset reference value, the controller 200 may perform a start-gap wear leveling operation.

In one embodiment, the controller 200 performs global start-gap wear leveling and starts when the total number of times of accessing metadata stored in memory regions_01 to memory region_M is equal to or greater than the first reference value. Meta data stored in memory regions subject to gap wear leveling may be migrated to the spare region.

In one embodiment, if the total number of times of accessing metadata stored in each of the sub-regions (sub region_01 to sub region_09) for each memory region (memory region_01 to memory region_M) is equal to or greater than the second reference value, By performing local start-gap wear leveling, metadata stored in the sub memory areas subject to start-gap wear leveling may be migrated to the sub spare area.

8 is a flowchart illustrating a start-gap wear leveling operation of a second memory according to an exemplary embodiment.

Referring to FIG. 8, in step S810, the controller 200 may count the number of times of accessing meta data stored in cold meta areas among a plurality of memory areas included in the second memory 240. In an embodiment, the controller 200 may count a total sum of the number of accesses per sub-meta-area included in each cold meta-area and the number of accesses per cold meta-area.

In step S820, the controller 200 may determine whether the number of times of accessing metadata stored in each sub-meta-region of the cold meta-regions is greater than or equal to the third reference value. In one embodiment, when a cold meta area in which the total number of accesses is greater than or equal to the first set value is detected, the controller 200 determines the number of accesses among the sub meta areas within the corresponding cold meta area to a third reference value (=first It is possible to check whether a sub-meta-region with a set value *α, α equal to or greater than 0<α<1) is detected.

In operation S830, the controller 200 may migrate meta data having an access count equal to or greater than the third reference value among meta data stored in the sub meta regions of the cold meta regions to the hot meta region.

In step S840, the controller 200 may count the total number of times of accessing meta data stored in the hot meta area.

In step S850, if the total number of access times to the meta-region data stored in the hot meta-region is equal to or greater than the second reference value, the controller 200 starts-gap for the meta-data stored in the wear-leveling target sub-region. Wear leveling, for example, a local start-gap wear leveling operation may be performed.

9 is a diagram illustrating a data processing system including a solid state drive (SSD) according to an exemplary embodiment. Referring to FIG. 9, the data processing system 2000 may include a host 2100 and a solid state drive 2200 (hereinafter referred to as an SSD).

The SSD 2200 may include a controller 2210, a buffer memory device 2220, nonvolatile memory devices 2231 to 223n, a power supply 2240, a signal connector 2250, and a power connector 2260. .

The controller 2210 may control all operations of the SSD 2200.

The buffer memory device 2220 may temporarily store data to be stored in the nonvolatile memory devices 2231 to 223n. Also, the buffer memory device 2220 may temporarily store data read from the nonvolatile memory devices 2231 to 223n. Data temporarily stored in the buffer memory device 2220 may be transmitted to the host 2100 or the nonvolatile memory devices 2231 to 223n under the control of the controller 2210.

The nonvolatile memory devices 2231 to 223n may be used as a storage medium of the SSD 2200. Each of the nonvolatile memory devices 2231 to 223n may be connected to the controller 2210 through a plurality of channels CH1 to CHn. One or more nonvolatile memory devices may be connected to one channel. Nonvolatile memory devices connected to one channel may be connected to the same signal bus and data bus.

The power supply 2240 may provide power PWR input through the power connector 2260 into the SSD 2200. The power supply 2240 may include an auxiliary power supply 2241. The auxiliary power supply 2241 may supply power so that the SSD 2200 is normally terminated when a sudden power off occurs. The auxiliary power supply 2241 may include large-capacity capacitors capable of charging power PWR.

The controller 2210 may exchange signals SGL with the host 2100 through the signal connector 2250. Here, the signal SGL may include a command, an address, and data. The signal connector 2250 may be configured with various types of connectors according to an interface method between the host 2100 and the SSD 2200.

10 is a diagram illustrating a configuration of the controller of FIG. 9 by way of example. Referring to FIG. 10, the controller 2210 includes a host interface unit 2211, a control unit 2212, a random access memory 2213, an error correction code (ECC) unit 2214, and a memory interface unit 2215. can do.

The host interface unit 2211 may interface the host 2100 and the SSD 2200 according to the protocol of the host 2100. For example, the host interface unit 2211 includes secure digital, universal serial bus (USB), multi-media card (MMC), embedded MMC (eMMC), personal computer memory card international association (PCMCIA), and Parallel advanced technology attachment (PATA), serial advanced technology attachment (SATA), small computer system interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), PCI Express (PCI-E), universal flash (UFS) storage) can communicate with the host 2100 through any one of the protocols. In addition, the host interface unit 2211 may perform a disk emulation function that supports the host 2100 to recognize the SSD 2200 as a general-purpose memory system, for example, a hard disk drive (HDD). .

The control unit 2212 may analyze and process the signal SGL input from the host 2100. The control unit 2212 may control operations of internal functional blocks according to firmware or software for driving the SSD 2200. The random access memory 2213 can be used as a working memory for driving such firmware or software.

The error correction code (ECC) unit 2214 may generate parity data of data to be transmitted to the nonvolatile memory devices 2231 to 223n. The generated parity data may be stored in the nonvolatile memory devices 2231 to 223n together with the data. The error correction code (ECC) unit 2214 may detect an error in data read from the nonvolatile memory devices 2231 to 223n based on the parity data. If the detected error is within the correction range, the error correction code (ECC) unit 2214 may correct the detected error.

The memory interface unit 2215 may provide control signals such as commands and addresses to the nonvolatile memory devices 2231 to 223n under the control of the control unit 2212. In addition, the memory interface unit 2215 may exchange data with the nonvolatile memory devices 2231 to 223n under the control of the control unit 2212. For example, the memory interface unit 2215 provides data stored in the buffer memory device 2220 to the nonvolatile memory devices 2231 to 223n, or buffers data read from the nonvolatile memory devices 2231 to 223n. It may be provided as a memory device 2220.

11 is a diagram illustrating a data processing system including a memory system according to an exemplary embodiment. Referring to FIG. 11, the data processing system 3000 may include a host 3100 and a memory system 3200.

The host 3100 may be configured in the form of a board such as a printed circuit board. Although not shown, the host 3100 may include internal functional blocks for performing the functions of the host.

The host 3100 may include a connection terminal 3110 such as a socket, a slot, or a connector. The memory system 3200 may be mounted on the connection terminal 3110.

The memory system 3200 may be configured in the form of a substrate such as a printed circuit board. The memory system 3200 may be referred to as a memory module or a memory card. The memory system 3200 may include a controller 3210, a buffer memory device 3220, a nonvolatile memory device 3231 to 3232, a power management integrated circuit (PMIC) 3240, and a connection terminal 3250.

The controller 3210 may control all operations of the memory system 3200. The controller 3210 may be configured in the same manner as the controller 2210 shown in FIG. 10.

The buffer memory device 3220 may temporarily store data to be stored in the nonvolatile memory devices 3231 to 3322. Also, the buffer memory device 3220 may temporarily store data read from the nonvolatile memory devices 3231 to 3322. Data temporarily stored in the buffer memory device 3220 may be transmitted to the host 3100 or the nonvolatile memory devices 3231 to 3322 under the control of the controller 3210.

The nonvolatile memory devices 3231 to 3232 may be used as a storage medium of the memory system 3200.

The PMIC 3240 may provide power input through the connection terminal 3250 into the memory system 3200. The PMIC 3240 may manage power of the memory system 3200 under the control of the controller 3210.

The connection terminal 3250 may be connected to the connection terminal 3110 of the host. Signals such as commands, addresses, data, and the like, and power may be transmitted between the host 3100 and the memory system 3200 through the connection terminal 3250. The connection terminal 3250 may be configured in various forms according to an interface method between the host 3100 and the memory system 3200. The connection terminal 3250 may be disposed on either side of the memory system 3200.

12 is a diagram illustrating a data processing system including a memory system according to an exemplary embodiment. Referring to FIG. 12, the data processing system 4000 may include a host 4100 and a memory system 4200.

The host 4100 may be configured in the form of a board such as a printed circuit board. Although not shown, the host 4100 may include internal functional blocks for performing the functions of the host.

The memory system 4200 may be configured in the form of a surface-mounted package. The memory system 4200 may be mounted on the host 4100 through a solder ball 4250. The memory system 4200 may include a controller 4210, a buffer memory device 4220, and a nonvolatile memory device 4230.

The controller 4210 may control all operations of the memory system 4200. The controller 4210 may be configured in the same manner as the controller 2210 shown in FIG. 10.

The buffer memory device 4220 may temporarily store data to be stored in the nonvolatile memory device 4230. Also, the buffer memory device 4220 may temporarily store data read from the nonvolatile memory devices 4230. Data temporarily stored in the buffer memory device 4220 may be transmitted to the host 4100 or the nonvolatile memory device 4230 under the control of the controller 4210.

The nonvolatile memory device 4230 may be used as a storage medium of the memory system 4200.

13 is a diagram illustrating a network system 5000 including a memory system according to an exemplary embodiment. Referring to FIG. 13, a network system 5000 may include a server system 5300 and a plurality of client systems 5410 to 5430 connected through a network 5500.

The server system 5300 may service data in response to a request from the plurality of client systems 5410 to 5430. For example, the server system 5300 may store data provided from a plurality of client systems 5410 to 5430. As another example, the server system 5300 may provide data to a plurality of client systems 5410 to 5430.

The server system 5300 may include a host 5100 and a memory system 5200. The memory system 5200 may include the memory system 10 of FIG. 1, the memory system 2200 of FIG. 9, the memory system 3200 of FIG. 11, and the memory system 4200 of FIG. 12.

14 is a block diagram illustrating a nonvolatile memory device included in a memory system according to an exemplary embodiment. Referring to FIG. 14, the nonvolatile memory device 300 includes a memory cell array 310, a row decoder 320, a data read/write block 330, a column decoder 340, a voltage generator 350, and a control logic. It may contain (60).

The memory cell array 310 may include memory cells MC arranged in a region where the word lines WL1 to WLm and the bit lines BL1 to BLn cross each other.

The row decoder 320 may be connected to the memory cell array 310 through word lines WL1 to WLm. The row decoder 320 may operate under the control of the control logic 360. The row decoder 320 may decode an address provided from an external device (not shown). The row decoder 320 may select and drive the word lines WL1 to WLm based on the decoding result. For example, the row decoder 320 may provide the word line voltage provided from the voltage generator 350 to the word lines WL1 to WLm.

The data read/write block 330 may be connected to the memory cell array 310 through bit lines BL1 to BLn. The data read/write block 330 may include read/write circuits RW1 to RWn corresponding to each of the bit lines BL1 to BLn. The data read/write block 330 may operate under the control of the control logic 360. The data read/write block 330 may operate as a write driver or a sense amplifier according to an operation mode. For example, the data read/write block 330 may operate as a write driver that stores data provided from an external device in the memory cell array 310 during a write operation. As another example, the data read/write block 340 may operate as a sense amplifier that reads data from the memory cell array 310 during a read operation.

The column decoder 340 may operate under the control of the control logic 360. The column decoder 340 may decode an address provided from an external device. The column decoder 340 includes read/write circuits RW1 to RWn and a data input/output line (or data input/output) of the data read/write block 330 corresponding to each of the bit lines BL1 to BLn based on the decoding result. Buffer) can be connected.

The voltage generator 350 may generate a voltage used for internal operation of the nonvolatile memory device 300. Voltages generated by the voltage generator 350 may be applied to the memory cells of the memory cell array 310. For example, a program voltage generated during a program operation may be applied to word lines of memory cells in which the program operation is to be performed. As another example, the erase voltage generated during the erase operation may be applied to a well-region of memory cells in which the erase operation is to be performed. As another example, a read voltage generated during a read operation may be applied to word lines of memory cells in which a read operation is to be performed.

The control logic 360 may control all operations of the nonvolatile memory device 300 based on a control signal provided from an external device. For example, the control logic 360 may control operations of the nonvolatile memory device 300 such as read, write, and erase operations of the nonvolatile memory device 300.

Those of ordinary skill in the art to which the present invention pertains may be implemented in other specific forms without changing the technical spirit or essential features thereof, so the embodiments described above are illustrative and non-limiting in all respects. You must understand. The scope of the present invention is indicated by the claims to be described later rather than the detailed description, and all changes or modified forms derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.

Claims (15)

As a controller for controlling a nonvolatile memory device,
A first memory temporarily storing user data;
A second memory including at least one meta area for storing meta data and a plurality of memory areas including at least one spare area; And
A processor that controls the first memory and the second memory, and performs first start-gap wear leveling by using at least one spare area included in the second memory as a gap;
Controller comprising a. The method of claim 1,
The processor,
And performing the first start-gap wear leveling so that the meta data of at least one meta area moves to the spare area when the sum of the number of times the meta data is accessed is equal to or greater than a first reference value. The method of claim 1,
Each of the at least one meta area,
Includes a plurality of sub-regions consisting of at least one sub-meta-region and at least one sub-spare region for storing the meta data,
The processor,
A controller that performs second start-gap wear leveling with the at least one sub spare region as a gap for the at least one sub meta region. The method of claim 3,
The processor,
When the total number of times of accessing the meta data stored in the sub meta regions for each meta region exceeds a second reference value, the second start so that the meta data of at least one sub meta region moves to the sub spare region. A controller, characterized in that to perform gap wear leveling. The method of claim 3,
The at least one meta area includes a cold meta area and a hot meta area,
The processor,
Migrating meta data having an access count greater than or equal to a third reference value among meta data stored in the cold meta areas to the hot meta area,
And performing the second start-gap wear leveling on the hot meta region. The method of claim 5,
When a cold meta-area in which the total number of accesses is greater than or equal to a first set value is detected, the processor may perform meta data of a sub-meta-area having an access count equal to or greater than the third reference value among sub-meta-areas within the detected cold meta-area A controller configured to migrate to the hot meta area. The method of claim 1,
Wherein the first memory has a larger data storage capacity than the second memory. The method of claim 1,
The controller according to claim 1, wherein the first memory has a faster data processing speed than the second memory. The method of claim 1,
The first memory is a dynamic random access memory (DRAM) module,
The second memory is a PCRAM (Phase-Change Random Access Memory) module, characterized in that the controller. A method of operating a controller including a first memory for temporarily storing user data and a second memory including a plurality of memory areas including at least one meta area and at least one spare area for storing meta data,
The controller. Determining whether the number of times of accessing each of the at least one meta area in which the meta data is stored is greater than or equal to a first reference value; And
When the total sum of the number of accesses to the meta data is greater than or equal to a first reference value, the controller sets at least one spare area to at least one meta area as a gap, and a first start-gap wear. Performing leveling;
The operation method of the controller comprising a. The method of claim 10,
The performing of the first start-gap wear leveling includes moving metadata of at least one memory area to the at least one spare area. The method of claim 10,
Each of the meta regions includes a plurality of sub regions consisting of at least one sub meta region and at least one sub spare region storing the meta data,
Determining, by the controller, whether the sum of the total number of times of accessing the meta data stored in the sub meta areas for each meta area is equal to or greater than a second reference value; And
Performing, by the controller, second start-gap wear leveling with the at least one sub-spare area as a gap for at least one sub-meta-area when the total sum of the number of accesses is greater than or equal to the second reference value;
The operation method of the controller further comprising. The method of claim 12,
The performing of the second start-gap wear leveling includes moving meta data of at least one sub meta area to the at least one sub spare area. The method of claim 12,
The at least one meta area includes a cold meta area and a hot meta area,
Migrating, by the controller, meta data having an access count equal to or greater than a third reference value among meta data stored in the cold meta regions to the hot meta region; And
Performing the second start-gap wear leveling on the hot meta region;
The operation method of the controller further comprising. The method of claim 14,
The migrating may include: detecting, by the processor, a cold meta area in which the sum of the number of accesses is equal to or greater than a first set value; And
Migrating, by the controller, meta data of a sub-meta-area in the detected cold meta-area whose access count is equal to or greater than the third reference value to the hot meta-area;
The operating method of the controller is configured to further include.

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