KR20200009114A - Spin-orbit torque bit design for improved switching efficiency - Google Patents

Abstract

The present invention relates to a method for a non-volatile memory cell, specifically, a spin-orbit torque MRAM (SOT-MRAM) memory cell for reducing current required for switching individual bits. The SOT-MRAM memory cell of the present invention includes: a first interconnect line having a first longitudinal axis; an oval MTJ bit (bit) having a long axis; and a second interconnect line having a second longitudinal axis perpendicular to the first interconnect line. The bit includes a polarized free layer, a barrier layer, and a polarized reference layer having a magnetic moment pinned at a different angle from a long axis. The long axis is disposed to form an angle with respect to the first and second longitudinal direction axes, the reference layer is disposed as described, and voltage is applied to the interconnect lines, thereby inducing a non-zero equilibrium angle between a spin current or a Rashba field and the free layer. Accordingly, switching dynamics may be more consistent.

Description

SPIN-ORBIT TORQUE BIT DESIGN FOR IMPROVED SWITCHING EFFICIENCY}

Embodiments of the present disclosure generally relate to non-volatile memory and, more particularly, to magnetoresistive random access memory (MRAM) with improved spin torque efficiency.

At the heart of the computer is a magnetic recording device, which may typically include rotating magnetic media or solid state media devices. Many different memory technologies exist today for storing information for use in computing systems. These different memory technologies can generally be divided into two main categories: volatile memory and non-volatile memory. Volatile memory may generally refer to the types of computer memory that require power to hold stored data. On the other hand, non-volatile memory may generally refer to types of computer memory that do not require power to hold stored data. Examples of non-volatile memory may include read-only memory (ROM), magnetoresistive RAM (MRAM), and flash memory such as NOR and NAND flash and the like.

Recently, MRAM has attracted more and more attention as the next generation non-volatile memory. MRAM provides fast access time, nearly infinite read / write endurance, radiation hardness, and high storage density. Unlike conventional RAM chip technologies, MRAM data is not stored as a charge, but instead data bits are stored using magnetic moments. MRAM devices may include memory elements formed of two magnetically polarized layers, each of which is separated by a thin insulating layer that together forms a magnetic tunnel junction (MTJ) bit. Thus, the magnetic polarization field can be maintained. The thin insulating layer can be a barrier layer. MTJ memory bits can be designed for in-plane or perpendicular magnetization of the MTJ bit structure to the film surface. One of the two magnetic layers is a permanent magnet set to a specific polarity (ie, has a fixed magnetization); The polarization of the other layer will change under the influence of an external recording mechanism such as a strong magnetic field or spin polarized current (ie, having free magnetization). As such, the cells have two stable states that allow the cells to act as non-volatile memory cells.

One type of MRAM employing MTJ memory bits is spin-torque-transfer MRAM (STT-MRAM), where the bit state is written using spin polarized current. Typically, however, a large amount of write current is required to switch the state of the cell. Over time, the barrier layer may break due to the amount of current, which may render the MTJ inoperable. Additionally, in STT-MRAM devices, it may be difficult to isolate a single MTJ bit for writing without disturbing neighboring MTJ bits, and a large transistor may be needed to select individual MTJ bits.

Thus, there is a need in the art for an improved MRAM device that can select individual MTJ bits without disturbing neighboring MTJ bits, and can also improve the efficiency of write current to prevent destruction of the barrier layer. exist.

TECHNICAL FIELD This disclosure relates generally to non-volatile memory devices, and in particular, a spin orbital torque MRAM (SOT-) that provides a reduction in the amount of current required to switch individual bits, as well as an improvement in switching reliability. MRAM) memory cell. The SOT-MRAM memory cell comprises a first interconnection line having a first longitudinal axis, an elliptical shape MTJ bit with an elongated axis, and a second interconnection line having a second longitudinal axis oriented perpendicular to the first interconnection line. Include. The long axis of the elliptical shape MTJ bit is arranged at an angle with respect to the first longitudinal axis and the second longitudinal axis. The MTJ bit includes a magnetically polarized free layer, a barrier layer used to decouple the magnetic layers, and a magnetically polarized reference layer having a magnetic moment pinned at an angle different from the long axis of the MTJ bit. do. Applied over the MTJ bit by selecting to orient the long axis of the MTJ bit at an angle with respect to the first longitudinal axis and the second longitudinal axis, and to orient the MTJ reference layer moment at an angle different from the long axis of the MTJ bit. A non-zero equilibrium angle can be derived between the free layer moment and the spin currents / rush bar fields induced by any combination of voltage and voltage along the interconnect line, thus switching dynamics The switching dynamics are more coherent and the incubation time for inversion can be reduced.

In one embodiment, the memory cell has a first interconnect line having a first longitudinal axis, a second interconnect line having a second longitudinal axis disposed perpendicular to the first interconnect line, and an oval shaped bit having an elongated axis. It includes. The elliptical shape bit is disposed between the first interconnect line and the second interconnect line, wherein the long axis is disposed at an angle with respect to the first longitudinal axis and the second longitudinal axis. The elliptical shape bit includes a free layer, a reference layer having a magnetic moment, the magnetic moment disposed at an angle different from the long axis, and a barrier layer disposed between the free layer and the reference layer.

In another embodiment, the memory cell comprises an interconnect line having a first longitudinal axis, a separate contact disposed perpendicular to the interconnect line, an elliptical shape bit coupled to the interconnect line, wherein the elliptical shape bit is a long axis. Wherein the long axis is disposed at an angle with respect to the first longitudinal axis, wherein the elliptical shaped bit is a free layer, a reference layer having a magnetic moment disposed at a different angle than the long axis, and the free layer and the reference. And a barrier layer disposed between the layers.

In another embodiment, the memory array includes a first interconnect line having a first longitudinal axis, a second interconnect line having a second longitudinal axis perpendicular to the first interconnect line, parallel to the first interconnect line. A third interconnect line having a third longitudinal axis, a first elliptical shape bit having a first long axis, and a second elliptical shape bit having a second long axis. The first elliptical shape bit is disposed between the first interconnect line and the second interconnect line, wherein the first long axis is disposed at an angle with respect to the first longitudinal axis and the second longitudinal axis. The first elliptical shape bit comprises a first free layer, a first reference layer having a first magnetic moment, the first magnetic moment disposed at an angle different from the first long axis, and between the first free layer and the first reference layer. And a first barrier layer disposed. The second elliptical shape bit is disposed between the second interconnect line and the third interconnect line, wherein the second long axis is disposed at an angle with respect to the second longitudinal axis and the third longitudinal axis. The second elliptical shape bit is a second free layer, a second reference layer having a second magnetic moment, wherein the second magnetic moment is disposed at an angle different from the second long axis, and between the second free layer and the second reference layer. A second barrier layer disposed.

A non-zero equilibrium angle can be induced between the free layer moment and the spin currents / rush bar fields induced by any combination of voltage applied across the MTJ bit and voltage along the interconnect line, thus switching Dynamics become more consistent and the incubation time for reversal can be reduced.

To enable the above-listed features of the present disclosure to be understood in detail, a more specific description of the present disclosure briefly summarized above may be made with reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and, therefore, should not be considered as limiting the scope of the disclosure, which is not intended to limit other equally effective embodiments of the present disclosure. This is because it can be allowed.
1A is a schematic illustration of a SOT-MRAM memory cell according to one embodiment.
FIG. 1B is a schematic top plan view of the SOT-MRAM memory cell of FIG. 1A.
1C is a schematic diagram of free and reference layers of a SOT-MRAM memory cell according to one embodiment.
1D is a schematic side view of a memory bit in accordance with one embodiment.
1E is a schematic side view of a memory bit in accordance with another embodiment.
1F is a schematic side view of a SOT-MRAM memory cell according to one embodiment.
1G is a schematic side view of a SOT-MRAM memory cell according to another embodiment.
1H is a schematic diagram of states of a SOT-MRAM memory cell according to one embodiment.
1I is a schematic diagram of states of a SOT-MRAM memory cell according to another embodiment.
2A is a schematic diagram of a memory array according to one embodiment.
2B is a schematic perspective view of a SOT-MRAM memory array according to one embodiment.
3A is a schematic top view of a SOT-MRAM memory cell.
3B is a schematic diagram of a reference layer and a free layer of the SOT-MRAM memory cell of FIG. 3A.
3C is a schematic side view of a SOT-MRAM memory cell according to one embodiment.
3D is a schematic side view of a SOT-MRAM memory cell according to one embodiment.
3E is a schematic illustration of a SOT-MRAM memory array according to another embodiment.
In order to facilitate understanding, the same reference numerals are used as much as possible to designate the same elements common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized in other embodiments without specifically describing it.

In the following, reference is made to embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the specific embodiments described. Instead, any combination of the following features and elements, or related to different embodiments, is contemplated for implementing and implementing the present disclosure. In addition, although embodiments of the present disclosure may achieve advantages over other possible solutions and / or prior art, whether a particular advantage is achieved by a given embodiment or not does not limit the disclosure. Accordingly, the following aspects, features, embodiments, and advantages are not considered to be elements or limitations of the appended claims, except as illustrative and clearly enumerated in the claim (s). Likewise, reference to "the present disclosure" is not to be construed as a generalization of any subject matter of the invention disclosed herein, except as explicitly stated in the claim (s) or in the elements of the appended claims. It should not be considered limiting.

TECHNICAL FIELD This disclosure relates generally to non-volatile memory devices, and in particular, a spin orbital torque MRAM (SOT-) that provides a reduction in the amount of current required to switch individual bits, as well as an improvement in switching reliability. MRAM) memory cell. The SOT-MRAM memory cell comprises a first interconnection line having a first longitudinal axis, an elliptical shape MTJ bit with an elongated axis, and a second interconnection line having a second longitudinal axis oriented perpendicular to the first interconnection line. Include. The long axis of the elliptical shape MTJ bit is arranged at an angle with respect to the first longitudinal axis and the second longitudinal axis. The MTJ bit includes a magnetically polarized free layer, a barrier layer used to decouple the magnetic layers, and a magnetically polarized reference layer having a magnetic moment pinned at an angle different from the long axis of the MTJ bit. The voltage and mutual applied across the MTJ bits by orienting the long axis of the MTJ bit at an angle with respect to the first longitudinal axis and the second longitudinal axis, and orienting the MTJ reference layer moment at an angle different from the long axis of the MTJ bit. A non-zero equilibrium angle can be induced between the free currents and the spin currents / rush bar fields induced by any combination of voltages along the connection line, thereby making the switching dynamics more consistent and inverting Incubation time for can be reduced.

1A is a schematic illustration of a SOT-MRAM memory cell 100 according to one embodiment. The memory cell 100 may be a spin-hole-effect-based MRAM (SHE-MRAM) or a Rashba effect MRAM. Memory cell 100 has a first interconnect line 105 having a first longitudinal axis 105a, a second interconnect with a second longitudinal axis 110a perpendicular to the first interconnect line 105. It has an elliptical shape bit 115 having a connecting line 110 and an elongated axis 115a disposed at an angle with respect to the first longitudinal axis 105a and the second longitudinal axis 110a. The magnetic tunnel junction memory element or elliptical shape bit 115 may comprise a free layer 120 with free magnetization, a reference layer 125 with a fixed or pinned magnetic moment 125a, and a free layer 120 and a reference layer. Barrier layer 130 used to decouple the magnetic layers disposed between the 125. The magnetic moment 125a of the reference layer 125 is disposed at an angle different from the long axis 115a. It should be understood that additional layers may exist between the free layer 120 and each interconnect line 105, 110, as well as between the reference layer 125 and each interconnect line 105, 110. do. For example, antiferromagnetic layers, synthetic antiferromagnetic structures, or capping layers may be present.

The elliptical shape bit 115 is an elliptical cylinder having a height, a long diameter, and a short diameter, where the long diameter is larger than the short diameter. The long diameter of the elliptical shape bit 115 is equivalent to the long axis 115a. In one embodiment, the long axis 115a is equal to the widths of both the first interconnect line 105 and the second interconnect line 110. In one embodiment, the long axis 115a of the elliptical shape bit 115 is oriented 5 to 60 degrees from the second longitudinal axis 110a. In one embodiment, the long axis 115a of the elliptical shape bit 115 is oriented from 30 degrees to 85 degrees from the first longitudinal axis 105a. In one embodiment, the bit may be oriented such that the free layer 120 contacts the second interconnect 110 at an angle of 5 degrees to 60 degrees from the second longitudinal axis 110a. In another embodiment, the bit may be oriented such that the free layer 120 contacts the first interconnect 105 at an angle of 5 degrees to 60 degrees from the first longitudinal axis 105a. In one embodiment, the long axis 115a is disposed at an angle of 5 degrees to 60 degrees from the first longitudinal axis 105a.

The elliptical shape bit 115 is patterned to provide uniaxial anisotropy along the long axis 115a to the elliptical shape bit 115 so that the free layer 120 is in two directions along the long axis 115a. It ensures that you will only point in one direction. As a result of the patterned shape, uniaxial anisotropic energy is formed sufficiently naturally, creating a barrier to prevent the free layer 120 from spontaneously switching, thus ensuring retention. Uniaxial anisotropy energy is determined by the formula 1 / 2M _s H _k V, where M _s is saturated magnetization, H _k is anisotropic field, and V is volume. Writing occurs by passing spin polarized current through the free layer 120. Spin polarized current forces torque on the free layer 120, allowing the free layer 120 to overcome the anisotropic energy barrier and switch orientation. Spin hole effects and / or lash bar effects generated by passing a current through an interconnect 105 coupled to a free layer may help to improve the writeability of individual bits including elliptical shaped bits 115. . The lash bar effects, only spin hole effects, or a combination of lash bar effects and spin hole effects can be selected to improve the writeability of individual bits. Individual memory cells can be written without disturbing neighboring memory cells. Additionally, to ensure that only selected memory cells are written, lash bars and / or spin hole effects in neighboring memory cells can be suppressed, which is otherwise known as a half-select scheme. have. The opposite case may also occur, i.e., the spin hole effects and / or lashbar effects may be the main write mechanism, and that the spin polarized current flowing through the MTJ bit improves writeability and ensures proper bit selection. It is understood that I can help.

FIG. 1B is a schematic of the SOT-MRAM memory cell 100 of FIG. 1A showing the arrangement of elliptical shaped bits 115 at an angle with respect to the first interconnect line 105 and the second interconnect line 110. Phosphorus top view. In other systems, the pinning of the reference layer 125 is such that the long axis 115a of the elliptical shaped bit 115 is such that the spin polarization of the current interacting with the free layer 120 is collinear with respect to magnetization. Is made parallel to. Since the strength of the spin torque required to switch the free layer 120 is proportional to the sine of the angle between the free and reference layer moments, the free layer 120 and the reference between the layers are 0 degrees or 180 degrees. The collinear orientation of layer 125 results in a sine, resulting in zero spin torque. Thus, switching requires thermal fluctuations of the magnetic moments to induce a small misalignment between the layers, and as the current begins to flow through the free layer 120, vibrations overcome the anisotropic energy barrier. The free layer 120 begins to oscillate and increase in amplitude until the free layer 125 is large enough to allow the orientation to switch. Since these thermal variations are random processes, the initial time required to start processing (known as incubation time), and, accordingly, the total switching time for the entire bit array, as well as individual bits, is one write attempt and the next write attempt. It can change in the liver.

As illustrated in FIG. 1C, by pinning the magnetic moment 125a of the reference layer 125 at an angle different from the elongated axis 115a, the initial state for applying spin torque on the free layer 120 is greater than zero. Starting from a large amount, this eliminates incubation time and greatly improves switching efficiency and coherency. In one embodiment, the magnetic moment 125a of the reference layer 125 is disposed at an angle of 5 to 60 degrees from the long axis 115a of the elliptical shaped bit 115.

Reference layer 125 may be simply pinned by using an antiferromagnetic layer such as IrMn, PtMn, NiMn, NiO, or FeMn. In one embodiment, the elliptical shaped bit 115 may use a synthetic antiferromagnetic (SAF) fixed layer having two magnetic layers coupled through a nonmagnetic layer. In certain embodiments, the fixed ferromagnetic layer is a superlattice of Co and Pt, Co and palladium (Pd), Co and Ni, and / or combinations and mixtures thereof, or B, Ge, platinum (Pt) And / or a single ferromagnetic material comprising an alloy comprising Ni, Fe, Co, or a combination thereof with Mn. In certain embodiments, the nonmagnetic layer includes ruthenium (Ru). In certain embodiments, the SAF includes a first ferromagnetic layer, a second ferromagnetic layer, and a ruthenium (Ru) layer disposed between the first ferromagnetic layer and the second ferromagnetic layer.

In certain embodiments, elliptical shape bit 115 may include a bottom seeding underlayer, a pinning layer, and / or a capping layer. 1D shows a side view of one embodiment of elliptical shaped bits 115. The elliptical shape bit 115 includes an antiferromagnetic layer 135, a reference layer 125, a barrier layer 130, and a free layer 120. An elliptical shape bit 115 is disposed between the first interconnect line 105 and the second interconnect line 110, which is not shown. The antiferromagnetic layer 135 may be coupled to the reference layer 125 and may be coupled to the first interconnect line 105 or the second interconnect line 110. The barrier layer 130 is disposed between the reference layer 125 and the free layer 120.

1E shows a side view of another embodiment of elliptical shaped bit 115. The elliptical shape bit 115 includes a composite antiferromagnetic layer 145, a barrier layer 130, and a free layer 120. Synthetic antiferromagnetic layer 145 includes reference layer 125. In certain embodiments, the SAF includes a first ferromagnetic layer, a second ferromagnetic layer, and a ruthenium (Ru) layer disposed between the first ferromagnetic layer and the second ferromagnetic layer. The ferromagnetic layer adjacent the barrier layer 130 is the reference layer 125. An elliptical shape bit 115 is disposed between the first interconnect line 105 and the second interconnect line 110, which is not shown. The composite antiferromagnetic layer 145 may be coupled to the first interconnect line 105 or the second interconnect line 110. The barrier layer 130 is disposed between the reference layer 125 and the free layer 120.

1F illustrates a side view of one embodiment of a SOT-MRAM memory cell 100. The elliptical shape bit 115 includes a free layer 120 coupled to the first interconnect line 105, and a reference layer 125 disposed directly on the second interconnect line 110. The free layer 120 and the reference layer 125 together with boron (B), germanium (Ge), and / or manganese (Mn) are nickel (Ni), iron (Fe), copper (Co), or alloys thereof. Combinations. The free layer 120 may have a thickness of about 1 nm to 6 nm, and the reference layer 125 may have a thickness of about 1 nm to 6 nm. The barrier layer 130 is disposed between the free layer 120 and the reference layer 125. The barrier layer 130 may be made of an oxide such as magnesium oxide (MgO), hafnium oxide (HfO), or aluminum oxide (AlO _x ), and may have a thickness of about 0.7 nm to 3 nm. The interconnect line (first interconnect 105 in FIG. 1F) coupled to the free layer is formed of Pt, Ta, W, having a thickness of about 4-20 nm to produce spin hole and / or lash bar effects. The second interconnect line 110 coupled to the reference layer 125 may be comprised of a material having a strong spin orbital coupling such as Hf, Ir, CuBi, CuIr, or AuW. And may have a thickness of about 20 nm to 100 nm.

FIG. 1G illustrates another embodiment of a SOT-MRAM memory cell 100, wherein the elliptical shape bits 115 are coupled to a reference layer 125 coupled to a first interconnect line 105, and a second. And a free layer 120 disposed directly on the interconnect line 110. The first interconnect line 105 and the second interconnect line 110 may be word lines and bit lines for read operations. The first interconnect line 105 and the second interconnect line 110 may be word lines and bit lines for write operations. The barrier layer 130 is disposed between the free layer 120 and the reference layer 125.

The elliptical shape bit 115 may be in a state representing 1 or 0, where the components of the free layer moment 120 are substantially antiparallel or parallel to the reference layer moment 125a, respectively. . The resistance of the bit 115 depends on the relative orientation of the magnetic moments of the reference layer 125 and the free layer 120 that interface with the barrier layer 130. When the magnetic moment of the free layer 120 is in a configuration that is substantially parallel to the reference moment 125a, as shown in FIG. 1H, the elliptical shape bits 115 are in a state of expressing zero. When the component of the free layer moment 120 is in a configuration that is substantially antiparallel to the reference moment 125a, as shown in FIG. 1I, the elliptical shape bit 115 is in a state of representing one.

2A illustrates a memory array 240 according to one embodiment. Memory array 240 includes a plurality of bottom interconnect lines, a plurality of top interconnect lines disposed perpendicular to the bottom interconnect lines, and a plurality of bottom interconnect lines and a plurality of top interconnect lines. It is composed of a plurality of elliptical shape bits arranged in. According to one example, in FIG. 2B, memory array 240 includes first interconnect line 205, second interconnect line 210, and a first interconnect disposed perpendicular to first interconnect line 205. A third interconnect line 220 disposed parallel to the connection line 205, a first elliptical shape bit 215 having a first long axis, and a second elliptical shape bit 225 having a second long axis. do. Although not shown, it can be understood that the first elliptical shape bit 215 has a similar arrangement as the elliptical shape bit 115. The first elliptical shape bit 215 is disposed between the first interconnect line 205 and the second interconnect line 210. The first elliptical shape bit 215 is a first free layer, a first reference layer having a first magnetic moment disposed at an angle different from the first long axis, and a first disposed between the first free layer and the first reference layer. 1 barrier layer. The second elliptical shape bit 225 is disposed between the second interconnect line 210 and the third interconnect line 220. The second elliptical shape bit 225 is a second free layer, a second reference layer having a second magnetic moment disposed at an angle different from the second long axis, and a second disposed between the second free layer and the second reference layer. 2 barrier layers. The second long axis of the second elliptical shape bit 225 may be parallel to the first long axis of the first elliptical shape bit 215. A possible alternative exists where the second long axis of the second elliptical shape bit 225 is at an angle different from the angle of the first long axis of the first elliptical shape bit 215. It is contemplated that memory array 240 may include a plurality of elliptical shape bits disposed at different angles with respect to the long axes of the remaining elliptical shape bits of the remaining array of bits in memory array 240. Can be.

3A illustrates another embodiment of a SOT-MRAM memory cell 300, wherein the memory cell 300 is an interconnect line 305 having a first longitudinal axis 305a, an interconnect line 305. Oval shaped bits 315 having an elongated axis 315a coupled to the < RTI ID = 0.0 >), < / RTI > and individual contacts 310 disposed perpendicular to the interconnect line 305. It can be appreciated that the individual contacts 310 can utilize select transistors, non-select transistors, or a combination of both. Elliptical shape bits 315 may be disposed between interconnect line 305 and individual contacts 310. The elongate axis 315a is disposed at an angle with respect to the first longitudinal axis 305a. Individual contact 310 may have a second longitudinal axis, which is not shown. In another embodiment, the long axis 315a is disposed at an angle with respect to the first longitudinal axis 305a and the second longitudinal axis.

Pinning of reference layer 325 may be understood to utilize the same techniques utilized to pin reference layer 125. As illustrated in FIG. 3B, the magnetic moment 325a of the reference layer 325 is pinned at a different angle than the free layer 320.

3C illustrates a side view of one embodiment of a SOT-MRAM memory cell 300. The elliptical shape bit 315 includes a free layer 320 coupled to the interconnect line 305, and a reference layer 325 disposed directly on the individual contact 310. The free layer 320 and the reference layer 325 are nickel (Ni), iron (Fe), copper (Co), or alloys thereof with boron (B), germanium (Ge), and / or manganese (Mn). Combinations. The free layer 320 may have a thickness of about 1 nm to 6 nm, and the reference layer 325 may have a thickness of about 1 nm to 6 nm. The barrier layer 330 is disposed between the free layer 320 and the reference layer 325. The barrier layer 330 may be made of an oxide such as magnesium oxide (MgO), hafnium oxide (HfO), or aluminum oxide (AlO _x ), and may have a thickness of about 0.7 nm to 3 nm. The first interconnect line 305 has a strong spin such as Pt, Ta, W, Hf, Ir, CuBi, CuIr, or AuW with a thickness of about 4-20 nm to produce spin hole and / or lash bar effects. It may be composed of a material having an orbital coupling.

3D illustrates another embodiment of a SOT-MRAM memory device 300, wherein the elliptical shape bits 315 are reference layer 325 coupled to the interconnect line 305, and individual contacts 310. ) A free layer 320 disposed directly on the substrate. The individual contacts 310 coupled to the free layer 320 are Pt, Ta, W, Hf, Ir, CuBi, CuIr, having a thickness of about 4-20 nm to produce spin hole and / or lash bar effects. Or a material having a strong spin orbital coupling, such as AuW, the second interconnect line 305 coupled to the reference layer 325 may be comprised of copper or aluminum, and from about 20 nm to 100 It may have a thickness of nm. The barrier layer 330 is disposed between the free layer 320 and the reference layer 325. Individual contact 310 may be coupled to two select transistors 335, 345 disposed on opposite sides of bit 315. Interconnect line 305 may be in contact with one or more rows of bits. Individual contacts 310 may contact a single bit. As such, the present disclosure may include an array of cells with independent contacts, as shown in FIG. 3E. It can be appreciated that elliptical shape bit 315 can include various embodiments of elliptical shape bit 115. By way of example, the elliptical shape bit 315 may comprise one or more of the following: capping layer, underlayer, and / or pinning layer.

3E illustrates a memory array 340 according to one embodiment. The memory array 340 includes a plurality of interconnect lines, a plurality of independent contacts disposed perpendicular to the plurality of interconnect lines, and a plurality of interconnect lines and a plurality of individual contacts coupled to the plurality of interconnect lines. Is composed of elliptical shape bits. According to one example, the memory array 340 has an elliptical shape bit having an interconnect line 305, an individual contact 310 disposed perpendicular to the first interconnect line 305, and an elongated axis 315a. 315). Interconnect line 305 has been partially removed to show individual contact 310. The elliptical shape bit 315 includes a free layer, a reference layer having magnetic moments disposed at an angle different from the long axis, and a barrier layer disposed between the free layer and the reference layer. It should be understood that elliptical shape bit 315 may be similar to elliptical shape bit 115 as described in FIGS. 1D and 1E. It is contemplated that the memory array 340 may include a plurality of elliptical shape bits disposed at different angles with respect to the long axes of the remaining elliptical shape bits of the remaining array of bits in the memory array 340. Can be.

Thus, the bit is patterned to provide uniaxial anisotropy to the bit, ensuring that the free layer will only point in one of two directions, and at an angle relative to the first interconnection and the second interconnection By placing the bits and placing the magnetic moment of the reference layer at an angle different from the long axis, the switching of the free layer can be enhanced, thereby making the faster and more of the selected memory cells without disturbing neighboring memory cells. Consistent write and read times can be allowed.

While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, and the scope of the present disclosure is determined by the following claims do.

Claims (24)

A first interconnect line having a first longitudinal axis;
A second interconnect line having a second longitudinal axis disposed perpendicular to the first interconnect line; And
An elliptical shape bit having an elongated axis disposed between the first interconnect line and the second interconnect line, the elongated axis disposed at an angle with respect to the first longitudinal axis and the second longitudinal axis.
Including;
The oval shape bit,
Free layer;
A reference layer, having a magnetic moment disposed at an angle different from the elongated axis; And
A barrier layer disposed between the free layer and the reference layer
A memory cell comprising a. The method of claim 1,
And the barrier layer comprises an oxide material comprising one or more of magnesium oxide (MgO), hafnium oxide (HfO), and aluminum oxide (AlO _x ). The method of claim 1,
And the elliptical shape bit is a spin-hole-effect-based magnetoresistive random access memory. The method of claim 1,
And the elliptical shape bit is a Rashba-effect-based magnetoresistive random access memory. The method of claim 1,
And the free layer is coupled to the first interconnect line. The method of claim 1,
The first interconnect line is platinum (Pt), tantalum (Ta), tungsten (W), hafnium (Hf), iridium (Ir), copper-bismuth (CuBi), copper-iridium (CuIr) and aluminum-tungsten And at least one of (AuW), wherein the first interconnect line has a thickness of about 4 nm to 20 nm. The method of claim 1,
Wherein the first interconnect line comprises one or more of copper and aluminum, and wherein the first interconnect line has a thickness of about 20 nm to 100 nm. The method of claim 1,
And the reference layer is coupled to the first interconnect line. The method of claim 1,
And the elongated axis is disposed at an angle of 5 degrees to 60 degrees from the first longitudinal axis. An interconnect line having a first longitudinal axis;
An elliptical shape bit coupled to the interconnect line, the elliptical shape bit having an elongated axis, the elongated axis disposed at an angle between about 5 degrees and about 60 degrees with respect to the first longitudinal axis; And
Individual contacts disposed perpendicular to the interconnect line
Including;
The oval shape bit,
Free layer;
A reference layer having a magnetic moment; And
A barrier layer disposed between the free layer and the reference layer
A memory cell comprising a. The method of claim 10,
And the elliptical shape bit further comprises a capping layer. The method of claim 10,
And the elliptical shape bit further comprises a pinning layer. The method of claim 12,
And the pinning layer is an antiferromagnetic material (AFM). The method of claim 12,
The pinning layer includes one or more of iridium-manganese (IrMn), platinum-manganese (PtMn), nickel-manganese (NiMn), nickel oxide (NiO), and iron-manganese (FeMn). . The method of claim 10,
And the reference layer is part of a synthetic antiferromagnetic structure. The method of claim 15,
The synthetic antiferromagnetic structure includes a first ferromagnetic layer adjacent to the barrier layer, a second ferromagnetic layer, and a ruthenium layer disposed between the first ferromagnetic layer and the second ferromagnetic layer, wherein the reference layer is the first ferromagnetic layer. A memory cell, which is a ferromagnetic layer. The method of claim 10,
And the free layer is coupled to the first interconnect line. The method of claim 10,
The free layer is coupled to the respective contact. The method of claim 10,
The individual contacts are platinum (Pt), tantalum (Ta), tungsten (W), hafnium (Hf), iridium (Ir), copper-bismuth (CuBi), copper-iridium (CuIr) and aluminum-tungsten (AuW) Wherein the individual contacts have a thickness of about 4 nm to 20 nm. A first interconnect line having a first longitudinal axis;
A second interconnect line having a second longitudinal axis perpendicular to the first interconnect line;
A third interconnection line having a third longitudinal axis parallel to the first interconnection line;
A first elliptical shape bit having a first elongated axis disposed between said first interconnect line and said second interconnect line, said first elongated axis being angled with respect to said first longitudinal axis and said second longitudinal axis. Arranged; And
A second elliptical shape bit having a second elongated axis disposed between the second interconnect line and the third interconnect line, the second elongated axis being angled with respect to the second longitudinal axis and the third longitudinal axis. Placed in ―
Including;
The first elliptical shape bit,
A first free layer;
A first reference layer having a first magnetic moment disposed at an angle different from the first long axis; And
A first barrier layer disposed between the first free layer and the first reference layer
Including,
The second elliptical shape bit,
A second free layer;
A second reference layer having a second magnetic moment disposed at an angle different from the second long axis; And
A second barrier layer disposed between the second free layer and the second reference layer
Including, a memory array. The method of claim 20,
And the memory array is a spin-hole-effect-based magnetoresistive random access memory array. The method of claim 20,
And the memory array is a lash bar-effect-based magnetoresistive random access memory array. The method of claim 20,
And the first free layer is coupled to the first interconnect line. The method of claim 23, wherein
The first interconnect line is platinum (Pt), tantalum (Ta), tungsten (W), hafnium (Hf), iridium (Ir), copper-bismuth (CuBi), copper-iridium (CuIr) and aluminum-tungsten And at least one of (AuW), wherein the first interconnect line has a thickness of about 4 nm to 20 nm.

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