KR20190111339A - Semiconductor device - Google Patents

Abstract

According to an embodiment of the present invention, a semiconductor element comprises: a substrate; a semiconductor structure including a first conductive semiconductor layer, a second conductive semiconductor layer arranged on the substrate, and an active layer arranged between the first conductive semiconductor layer and the second conductive semiconductor layer; an electrode layer arranged to be spaced apart from an edge of an upper surface of the semiconductor structure; and a passivation layer arranged on at least a part of a side surface, an upper surface of the semiconductor structure, and the electrode layer. The semiconductor structure includes a plurality of protrusion regions extended from a lower surface to a lower part of the second conductive semiconductor layer. The passivation layer is in direct contact with the edge of the upper surface of the semiconductor structure.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The embodiment relates to a semiconductor device.

Among the semiconductor devices, a light emitting device is a pn junction diode in which electrical energy is converted into light energy. The light emitting device may be formed of compound semiconductors such as group III and group V in the periodic table and by adjusting the composition ratio of the compound semiconductor. Various colors can be realized.

When the forward voltage is applied, the n-layer electrons and the p-layer holes combine to emit energy corresponding to the bandgap energy of the conduction band and the valence band. Is mainly emitted in the form of heat or light, and emits light in the form of light emitting elements.

For example, nitride semiconductors are receiving great attention in the field of optical devices and high power electronic devices due to their high thermal stability and wide bandgap energy. In particular, blue light emitting devices, green light emitting devices, and ultraviolet light emitting devices using nitride semiconductors are commercially used and widely used.

In general, the nitride semiconductor light emitting device may be classified into a horizontal type light emitting device and a vertical type light emitting device according to the position of the electrode layer.

On the other hand, the passivation (passivation) is preferably deposited on the external exposed surface in order to ensure reliability and long life.

The embodiment provides a semiconductor device which minimizes leakage current in a low current region.

In addition, the present invention provides a semiconductor device having improved light output at low current.

The problem to be solved in the examples is not limited thereto, and the object or effect that can be grasped from the solution means or the embodiment described below will also be included.

A semiconductor device according to an embodiment of the present invention, a substrate; A semiconductor structure including a first conductive semiconductor layer disposed on the substrate, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer; An electrode layer spaced apart from an edge of an upper surface of the semiconductor structure; And a passivation layer disposed on at least part of a side surface, an upper surface of the semiconductor structure, and the electrode layer; The semiconductor structure includes a plurality of protrusion regions extending downward from a bottom surface of the second conductive semiconductor layer, and the passivation layer is in direct contact with an edge of an upper surface of the semiconductor structure.

The width of the second conductivity type semiconductor layer may be greater than the width of the electrode layer.

Side surfaces of the semiconductor structure and the side of the electrode layer may be spaced apart in the range 0.1nm ~ 10μm .

The second conductivity type semiconductor layer may include a blocking part disposed from the side thereof.

One side of the blocking portion may directly contact the passivation layer.

The width of the blocking unit may have a range of 0.1 nm to 10 μm.

The blocking portion may be in Schottky contact with the second conductivity type semiconductor layer.

The blocking portion may be doped with a second dopant at a higher concentration than the second conductivity type semiconductor layer.

The doping concentration of the second dopant of the blocking unit may be at least 10 ²⁰ / cm ³ .

A semiconductor device according to another embodiment of the present invention includes a semiconductor including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer. structure; An electrode layer disposed on the semiconductor structure; And a passivation layer disposed on a side of the semiconductor structure and at least a portion of the electrode layer. The semiconductor structure includes a plurality of protrusion regions extending downward from a lower surface of the second conductivity type semiconductor layer, wherein the protrusion region is doped with a second dopant, and the second conductivity type semiconductor layer and The doping concentration of the protruding region is in the range of 10 ¹⁹ / cm ³ ~ 10 ²⁰ / cm ³ .

According to the embodiment, it is possible to minimize the leakage current in the low current region.

It is also possible to improve the light output at low current.

Various and advantageous advantages and effects of the present invention are not limited to the above description, and will be more readily understood in the course of describing specific embodiments of the present invention.

1 is a cross-sectional view of a general semiconductor device,
2 is an exemplary diagram illustrating a process of forming an electron trap by excess oxygen in the passivation layer,
3 is an enlarged view illustrating an enlarged view of FIG. 1 3;
FIG. 4A is a graph showing the thickness change of the depletion layer according to the electron trap density and the doping concentration of the conductive semiconductor, assuming that electron traps are formed uniformly from the interface between the semiconductor structure and the passivation layer, and FIG. 4B is a passivation structure with the semiconductor structure. Assuming the electron trap is formed according to the Gaussian distribution from the interface between the layers, it is a graph showing the thickness change of the depletion layer according to the electron trap density and the doping concentration of the conductive semiconductor.
5 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention;
6 is a cross-sectional view of a semiconductor device according to a second exemplary embodiment of the present invention.
7 is a sectional view of a semiconductor device according to a third embodiment of the present invention;
8 is a cross-sectional view of a semiconductor device according to a fourth exemplary embodiment of the present invention.

The embodiments may be modified in other forms or in various embodiments, and the scope of the present invention is not limited to the embodiments described below.

Although matters described in a specific embodiment are not described in other embodiments, it may be understood as descriptions related to other embodiments unless there is a description that is contrary to or contradictory to the matters in other embodiments.

For example, if a feature is described for component A in a particular embodiment and a feature for component B in another embodiment, a description that is contrary or contradictory, even if the embodiments in which configuration A and configuration B are combined are not explicitly described. Unless otherwise, it should be understood to fall within the scope of the present invention.

In the description of the embodiment, when one element is described as being formed "on or under" of another element, it is on (up) or down (on). or under) includes both two elements being directly contacted with each other or one or more other elements are formed indirectly between the two elements. In addition, when expressed as "on" or "under", it may include the meaning of the downward direction as well as the upward direction based on one element.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

1 is a cross-sectional view of a general semiconductor device, FIG. 2 is an exemplary view illustrating a process of forming an electron trap due to excess oxygen in a passivation layer, FIG. 3 is an enlarged view of FIG. 1 enlarged, and FIG. 4A is Assuming a constant electron trap is formed from the interface between the semiconductor structure and the passivation layer, a graph showing the thickness change of the depletion layer according to the electron trap density and the doping concentration of the conductive semiconductor, Figure 4b is an interface between the semiconductor structure and the passivation layer Assuming that electron traps are formed according to a Gaussian distribution from the graph, the thickness of the depletion layer according to the electron trap density and the doping concentration of the conductive semiconductor is shown.

First, referring to FIG. 1, a general semiconductor device 10 may include a substrate 11, a buffer layer 12, semiconductor structures 13, 14, and 15, an electron blocking layer 16, an electrode layer 17, and a passivation layer ( 18), a first bonding pad 19a and a second bonding pad 19b may be included.

The substrate 11 includes a conductive substrate or an insulating substrate. The substrate 11 may be a material or a carrier wafer suitable for growing a semiconductor material. The substrate 11 may be formed of a material selected from sapphire (Al ₂ O ₃ ), GaN, SiC, GaAs, GaN, ZnO, Si, GaP, InP, and Ge, but is not limited thereto.

The buffer layer 12 is intended to mitigate the difference in lattice mismatch and thermal expansion coefficient of the material between the substrate 11 and the semiconductor structures 13, 14, 15. The material of the buffer layer 12 may be formed of at least one of Group III-V compound semiconductors, for example, GaN, InN, AlN, InGaN, AlGaN, InAlGaN, and AlInN. An undoped semiconductor layer may be formed on the buffer layer 12, but is not limited thereto.

The semiconductor structures 13, 14, and 15 are disposed on an upper surface of the substrate 11 and include a first conductive semiconductor layer 13, a second conductive semiconductor layer 14, and an active layer 15. The semiconductor structures 13, 14, and 15 may be separated into a plurality in the process of cutting the substrate 11.

In addition, although a portion of the first conductivity type semiconductor layer 13 is mesa-etched, the electrode may not be formed under the insulating substrate like the sapphire substrate, and thus, the first bonding pad 19a may be formed in the above-described etched region. Can be placed.

The first conductive semiconductor layer 13 may be a compound semiconductor such as a III-V group or a II-VI group, and the first dopant may be doped into the first conductive semiconductor layer 13. The first conductive semiconductor layer 13 is a semiconductor material having a composition formula of Inx1Aly1Ga1-x1-y1N (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1, 0 ≦ x1 + y1 ≦ 1), for example, GaN, AlGaN, InGaN, InAlGaN and the like can be selected. The first dopant may be an n-type dopant such as Si, Ge, Sn, Se, or Te. When the first dopant is an n-type dopant, the first conductive semiconductor layer 13 doped with the first dopant may be an n-type semiconductor layer.

The second conductive semiconductor layer 14 may be formed of a compound semiconductor such as a group III-V group or a group II-VI, and a second dopant may be doped into the second conductive semiconductor layer 14. The second conductive semiconductor layer 14 is a semiconductor material having a composition formula of Inx5Aly2Ga1-x5-y2N (0≤x5≤1, 0≤y2≤1, 0≤x5 + y2≤1) or AlInN, AlGaAs, GaP, GaAs It may be formed of a material selected from GaAsP, AlGaInP. When the second dopant is a p-type dopant such as Mg, Zn, Ca, Sr, or Ba, the second conductive semiconductor layer 14 doped with the second dopant may be a p-type semiconductor layer.

An electron blocking layer (EBL) 16 may be disposed between the active layer 15 and the second conductive semiconductor layer 14. The electron blocking layer 16 blocks the flow of electrons supplied from the first conductivity type semiconductor layer 13 to the second conductivity type semiconductor layer 14, whereby electrons and holes are recombined in the active layer 15. You can increase your chances.

On the other hand, a plurality of recesses (P) are disposed at the interface between the electron blocking layer 16 and the second conductivity-type semiconductor layer 14. The recess P may be formed by forming a groove in the surface of the electron blocking layer 16, and a second conductive semiconductor layer 14 may be inserted into the groove.

The recess P may be a protruding region disposed to protrude from the lower surface of the second conductive semiconductor layer 14 toward the electron blocking layer 16. The recess P may pass through the electron blocking layer 16 to form the active layer 15 or the first agent. It may protrude up to the first conductivity type semiconductor layer 13.

Although the recess P is illustrated in a V-pit shape, it may be three-dimensionally arranged in a conical shape, a polygonal horn shape, a pyramid shape, or the like.

Hereinafter, the recesses P will be described as V-pits P for convenience of explanation.

On the other hand, when the V-pit P is formed on the surface of the electron blocking layer 16 in contact with the second conductivity-type semiconductor layer 14, the hole H is formed through the V-pit P. 16, the number of times to advance to the active layer 15 may increase. That is, the hole H entering the V-pit P may be easily moved since the thickness of the electron blocking layer 16 disposed between the active layers 15 is thin or does not exist.

However, the volume of the second conductive semiconductor layer 14 may extend through the V-pit P, and thus, the second doped semiconductor layer 14 and the V-pit P are doped. Doping density of the dopant may be lowered.

The active layer 15 is a layer where electrons (or holes) injected through the first conductive semiconductor layer 13 meet holes (or electrons) injected through the second conductive semiconductor layer 14. The active layer 15 may transition to a low energy level as electrons and holes recombine, and may generate light having a corresponding wavelength. There is no restriction on the emission wavelength in this embodiment.

The active layer 15 may have one of a single well structure, a multi well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, or a quantum line structure, and the active layer 15 The structure of is not limited to this.

The semiconductor structures 13, 14, and 15 may be mesa-etched to expose the first conductive semiconductor layer 13 through the second conductive semiconductor layer 14 and the active layer 15. The first conductive semiconductor layer 13 may also be partially etched by mesa etching. The first bonding pads 19a may be disposed in the etching region to be electrically connected to the first conductive semiconductor layer 13. A second bonding pad 131 may be disposed on the second conductive semiconductor layer 14.

The thickness t of the entire electron blocking layer 16 may be 40 nm to 60 nm. If the thickness t is too thin, it is difficult to block electrons entering the active layer 15, and if the thickness t is too thick, The movement of holes entering from the two-conductive semiconductor layer 14 may be an obstacle. Preferably, the second conductivity type semiconductor layer 136 may be about 40 nanometers thick.

The electrode layer 17 is disposed on the second conductivity type semiconductor layer 14 and may be about 200 angstroms thick. The electrode layer 17 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), and indium gallium tin oxide (IGTO). , Aluminum zinc oxide (AZO), antimony tin oxide (ATO), gallium zinc oxide (GZO), IZO (IZO Nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO, IrOx, RuOx, NiO, RuOx / ITO, Ni / IrOx / Au, and Ni / IrOx / Au / ITO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, In, Ru, Mg, Zn, Pt, Au , Hf, and optional compounds or alloys thereof, and may be formed in at least one layer.

The electrode layer 17 is preferably composed of a light transmitting electrode layer serving as an ohmic layer, and a thinner thickness is preferable because a thicker thickness may cause light absorption.

The passivation layer 18 covers the side surfaces of the semiconductor structures 13, 14, and 15 and the top surface of the electrode layer 17 to cover the entire surface. The passivation layer 18 may include an insulating material or an insulating resin formed of at least one of an oxide, nitride, fluoride, and sulfide having at least one of Al, Cr, Si, Ti, Zn, and Zr. The passivation layer 18 may be selectively formed from, for example, SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , TiO ₂ . On the other hand, the passivation layer 18 is preferably composed of SiO ₂ .

In addition, the passivation layer 18 may be formed as a single layer or multiple layers, but is not limited thereto.

The first bonding pad 19a is connected to the first conductive semiconductor layer 13 exposed from the passivation layer 18, and the second bonding pad 19b is connected to the electrode layer 17 exposed from the passivation layer 18. Can be connected.

The first bonding pads 19a may be electrically connected to the first conductive semiconductor layer 13 exposed by mesa etching.

Each of the first bonding pads 19a and the second bonding pads 19b may include a metal material having electrical conductivity, and may include at least one of Ti, Ni, or Au, but embodiments are not limited thereto. Do not.

Meanwhile, referring to FIGS. 2 to 4B, an electron trap such as non-bridging-oxygen (NBO) may be formed in SiO ₂ formed of the passivation layer 18. Such electron traps may widen within the bandgap of the passivation layer 18.

Here, referring to FIGS. 4A and 4B, it is assumed that an electron trap is uniformly formed from an interface between the semiconductor structures 13, 14 and 15 and the passivation layer 18, and the semiconductor structures 13, 14 and 15. Assuming that an electron trap is formed according to the Gaussian distribution near the interface between the and passivation layer 18 shows similar results.

Through the electron trap, the passivation layer 18 forms a plurality of positive charges.

The positive charge in the passivation layer 18 may push out the holes H at the interface of the adjacent second conductive semiconductor layer 14.

As a result, the depletion region A in which the hole H moves in the inward direction of the second conductivity-type semiconductor layer 14 may be formed from the interface between the passivation layer 18 and the second conductivity-type semiconductor layer 14. have.

In addition, the second conductivity-type semiconductor layer 14 may form a hole region B in a region other than the depletion region A formed along the interface of the passivation layer 18.

Meanwhile, the depletion region A of the second conductivity type semiconductor layer 14 may have a first width W1.

In FIG. 4A and FIG. 4B, the matters indicated in the box of the graph indicate the doping concentration of the second dopant in the second conductivity-type semiconductor layer 14.

As shown in FIGS. 4A and 4B, the first width W1 of the depletion region A may vary according to the doping concentration of the second dopant.

For example, as the doping concentration of the second dopant in the second conductivity type semiconductor layer 14 increases, the first width W1 of the depletion region A decreases, and conversely, the doping concentration of the second dopant decreases. As a result, the first width W1 of the depletion region A may increase.

Here, as described above, since the second conductive semiconductor layer 14 has a volume expanded through the V-pit P, the doping density of the doped second dopant may decrease, so that mobility of the holes H may be reduced. The first width W1 of the depletion region A may be reduced.

Meanwhile, the first width W1 may vary depending on the current applied to the first bonding pads 19a and the second bonding pads 19b.

For example, when the current applied to the first bonding pad 19a and the second bonding pad 19b is a high current, the current applied to the second conductive semiconductor layer 14 pushes the holes H outward. The first width W1 of the depletion region A may be reduced or eliminated.

On the other hand, when the current applied to the first bonding pads 19a and the second bonding pads 19b is a low current, the positive charge of the passivation layer 18 is greater than that of the current pushing the holes H outward. A force for pushing (H) into the second conductivity-type semiconductor layer 14 may act largely to increase the first width W1 of the depletion region A. FIG.

Here, the depletion region A of the second conductivity type semiconductor layer 14 may provide a current path through which current can be directly transferred from the first bonding pad 19a to the second bonding pad 19b. Therefore, leakage current (LC) may occur.

Hereinafter, a semiconductor device according to a first exemplary embodiment of the present invention will be described with reference to FIG. 5.

5 is a cross-sectional view of a semiconductor device according to a first exemplary embodiment of the present invention.

5, the configuration of the second conductivity-type semiconductor layer 140, the electrode layer 170, the passivation 180, and the first blocking region C1 is different from that of the semiconductor device illustrated in FIG. 1. Therefore, hereinafter, only the configuration of the second conductive semiconductor layer 140, the electrode layer 170, the passivation 180, and the first blocking region C1 that are differentiated will be described in detail, and reference numerals overlapping the same configurations will be described in detail. Description is omitted.

The semiconductor device 100 according to the first embodiment of the present invention may include a substrate 11, a buffer layer 12, semiconductor structures 13, 140, and 15, an electron blocking layer 16, an electrode layer 170, and a passivation layer ( 180, the first bonding pads 19a and the second bonding pads 19b may be included.

The semiconductor structures 13, 140, and 15 are disposed on the top surface of the substrate 11 and include a first conductive semiconductor layer 13, a second conductive semiconductor layer 140, and an active layer 15. The semiconductor structures 13, 140, and 15 may be separated into a plurality in the process of cutting the substrate 11.

The V-pit P may be formed on the surface of the electron blocking layer 16 in contact with the second conductivity-type semiconductor layer 140. Through this, the number of times that the hole H passes through the electron blocking layer 16 through the V-pit P to the active layer 15 may increase. That is, the hole H entering the V-pit P may be easily moved since the thickness of the electron blocking layer 16 disposed between the active layers 15 is thin or does not exist.

However, the volume of the second conductive semiconductor layer 140 may extend through the V-pit P, and accordingly, the second doped semiconductor layer 140 and the V-pit P are doped. The doping density of the dopant may be lowered to increase the width of the depletion region A described above.

The second conductive semiconductor layer 140 is inward from the interface between the passivation layer 180 and the second conductive semiconductor layer 140 due to the positive charge in the passivation layer 180. As a result, the hole H may include the depletion region A in which the hole H is moved.

In addition, the second conductivity-type semiconductor layer 140 may include a hole region B, which is a region other than the depletion region A formed along the interface of the passivation layer 180.

As described above, the depletion region A of the second conductivity-type semiconductor layer 140 may have a first width that varies according to the doping concentration of the second dopant or the applied current.

The electrode layer 170 is disposed on the second conductivity type semiconductor layer 140. The electrode layer 170 is preferably composed of a translucent electrode layer that serves as an ohmic layer, and a thinner thickness is preferable because a thicker thickness may cause light absorption.

Here, the electrode layer 170 may have a smaller width than the width of the second conductive semiconductor layer 140.

That is, the side surface of the electrode layer 170 may be spaced apart from the side surface of the second conductivity type semiconductor layer 140.

Side surfaces of the electrode layer 170 may be spaced apart from the side surfaces of the second conductivity-type semiconductor layer 140 to form a first blocking region C1.

Substantially, the first blocking region C1 is a region where the side surface of the electrode layer 170 and the side surface of the second conductive semiconductor layer 140 are separated from each other, and the depletion region A of the second conductive semiconductor layer 140 is separated. It can serve to block leakage current that can flow through.

The first blocking region C1 may have a second width W2. That is, the side surface of the electrode layer 170 may be spaced apart from the side surface of the second conductivity type semiconductor layer 140 by the second width W2.

The second width W2 may be set in a range of 0.1 nm to 10 μm. Preferably, the second width W2 may be equal to the first width of the depletion region A of the second conductivity-type semiconductor layer 140.

Here, when the second width W2 is 0.1 nm or less, a leakage current flowing through the depletion region A of the second conductivity-type semiconductor layer 140 leaks to the outside through the electrode layer 170 to block leakage current. Can't expect On the other hand, when the second width W2 is 10 μm or more, the width of the electrode layer 170 is reduced more than necessary, which may inadvertently reduce the light emitting area of the semiconductor device 100.

The passivation layer 180 covers the side surfaces of the semiconductor structures 13, 140, and 15 and the top surface of the electrode layer 170 to cover the entire surface.

As described above, a plurality of electron traps, such as non-bridging-oxygen (NBO), may be formed in SiO ₂ formed of the passivation layer 180, and the electron trap may be formed in the passivation layer 180. It can spread widely within the bandgap.

Through the electron trap, the inside of the passivation layer 180 forms a plurality of positive charges, and the positive charges in the passivation layer 180 are formed at the interface of the adjacent second conductive semiconductor layer 140. ) To form a depletion region (A).

Hereinafter, a semiconductor device according to a second exemplary embodiment of the present invention will be described with reference to FIG. 6.

6 is a cross-sectional view of a semiconductor device according to a second exemplary embodiment of the present invention.

6, the configuration of the second conductive semiconductor layer 240, the blocking unit 290, and the second blocking region C2 is different from that of the semiconductor device illustrated in FIG. 1. Only the configuration of the second conductive semiconductor layer 240, the blocking portion 290, and the second blocking region C2 that are differentiated will be described in detail, and detailed description of the same reference numerals will be omitted.

The semiconductor device 200 according to the second embodiment of the present invention may include a substrate 11, a buffer layer 12, semiconductor structures 13, 240, and 15, an electron blocking layer 16, an electrode layer 17, and a passivation layer ( 18), a first bonding pad 19a and a second bonding pad 19b may be included.

The semiconductor structures 13, 240, and 15 are disposed on the top surface of the substrate 11 and include a first conductive semiconductor layer 13, a second conductive semiconductor layer 240, and an active layer 15. The semiconductor structures 13, 240, and 15 may be separated into a plurality in the process of cutting the substrate 11.

The V-pit P may be formed on the surface of the electron blocking layer 16 in contact with the second conductivity-type semiconductor layer 240. Through this, the number of times that the hole H passes through the electron blocking layer 16 through the V-pit P to the active layer 15 may increase. That is, the hole H entering the V-pit P may be easily moved since the thickness of the electron blocking layer 16 disposed between the active layers 15 is thin or does not exist.

However, the volume of the second conductive semiconductor layer 240 may be extended through the V-pit P, and accordingly, the second doped semiconductor layer 240 and the V-pit P are doped. The doping density of the dopant may be lowered to increase the width of the depletion region A described above.

The second conductive semiconductor layer 240 is inward from the interface between the passivation layer 18 and the second conductive semiconductor layer 240 due to the positive charge in the passivation layer 18. As a result, the hole H may include the depletion region A in which the hole H is moved.

In addition, the second conductivity-type semiconductor layer 240 may include a hole region B, which is a region other than the depletion region A formed along the interface of the passivation layer 18.

As described above, the depletion region A of the second conductivity-type semiconductor layer 240 may have a first width that varies according to the doping concentration of the second dopant or the applied current.

The electrode layer 17 is disposed on the second conductivity type semiconductor layer 240. The electrode layer 17 is preferably composed of a light transmitting electrode layer serving as an ohmic layer, and a thinner thickness is preferable because a thicker thickness may cause light absorption.

Here, the electrode layer 17 may be equal to the width of the second conductivity-type semiconductor layer 240. Meanwhile, as illustrated in FIG. 5, the width of the electrode layer 17 may have a smaller width than the width of the second conductive semiconductor layer 240.

The blocking part 290 may be disposed at an interface between the second conductivity-type semiconductor layer 240 and the electrode layer 17. Here, the blocking part 290 may be disposed such that one side thereof directly contacts the passivation layer 18.

The blocking unit 290 may be disposed in the depletion region A of the second conductive semiconductor layer 240, and the blocking unit 290 may be in Schottky contact with the second conductive semiconductor layer 240.

In this case, since the blocking portion 290 may block the flow of current to the portion where the schottky contact is made with the second conductive semiconductor layer 240, the schottky contact portion may form the second blocking region C2. .

Substantially, the second blocking region C2 is an arrangement region of the blocking portion 290, and indicates that leakage current that can flow through the depletion region A of the second conductivity-type semiconductor layer 240 flows to the electrode layer 17. Can play a role of blocking.

The second blocking region C2 may have a third width W3. That is, the blocking part 290 may have a third width W3.

The third width W3 may be set in a range of 0.1 nm to 10 μm. Preferably, the third width W3 may be equal to the first width of the depletion region A of the second conductivity-type semiconductor layer 240.

Here, when the third width W3 is 0.1 nm or less, leakage current flowing through the depletion region A of the second conductivity-type semiconductor layer 240 leaks to the outside through the electrode layer 17, thereby preventing leakage current. Can't expect On the other hand, when the third width W3 is 10 μm or more, the width of the electrode layer 17 is reduced more than necessary, which may inadvertently reduce the emission area of the semiconductor device 200.

The passivation layer 18 covers the side surfaces of the semiconductor structures 13, 240, and 15 and the top surface of the electrode layer 17 to cover the entire surface.

As described above, a plurality of electron traps such as non-bridging-oxygen (NBO) and the like may be formed in SiO ₂ composed of the passivation layer 18, and the electron trap may be formed in the passivation layer 18. It can spread widely within the bandgap.

Through the electron trap, the passivation layer 18 forms a plurality of positive charges, and the positive charges in the passivation layer 18 are formed at the interface of the adjacent second conductive semiconductor layer 240. ) To form a depletion region (A).

Hereinafter, a semiconductor device according to a third exemplary embodiment of the present invention will be described with reference to FIG. 7.

7 is a cross-sectional view of a semiconductor device according to a third exemplary embodiment of the present invention.

Referring to FIG. 7, the second conductive semiconductor layer 340, the blocking unit 390, and the third blocking region C3 are different from each other in the structure of the semiconductor device illustrated in FIG. 1. Only the configurations of the second conductive semiconductor layer 340, the blocking portion 390, and the third blocking region C3, which are differentiated, will be described in detail, and detailed descriptions thereof will be omitted.

The semiconductor device 300 according to the third embodiment of the present invention may include a substrate 11, a buffer layer 12, semiconductor structures 13, 340, and 15, an electron blocking layer 16, an electrode layer 17, and a passivation layer ( 18), a first bonding pad 19a and a second bonding pad 19b may be included.

The semiconductor structures 13, 340, and 15 are disposed on the top surface of the substrate 11 and include a first conductive semiconductor layer 13, a second conductive semiconductor layer 340, and an active layer 15. The semiconductor structures 13, 340, and 15 may be separated into a plurality in the process of cutting the substrate 11.

The V-pit P may be formed on the surface of the electron blocking layer 16 in contact with the second conductivity-type semiconductor layer 340. Through this, the number of times that the hole H passes through the electron blocking layer 16 through the V-pit P to the active layer 15 may increase. That is, the hole H entering the V-pit P may be easily moved since the thickness of the electron blocking layer 16 disposed between the active layers 15 is thin or does not exist.

However, the volume of the second conductive semiconductor layer 340 may be extended through the V-pit P, and accordingly, the second doped semiconductor layer 340 and the V-pit P are doped. The doping density of the dopant may be lowered to increase the width of the depletion region A described above.

The second conductive semiconductor layer 340 is inward from the interface between the passivation layer 18 and the second conductive semiconductor layer 340 due to the positive charge in the passivation layer 18. As a result, the hole H may include the depletion region A in which the hole H is moved.

In addition, the second conductivity-type semiconductor layer 340 may include a hole region B, which is a region other than the depletion region A formed along the interface of the passivation layer 18.

As described above, the depletion region A of the second conductivity-type semiconductor layer 340 may have a first width that varies according to the doping concentration of the second dopant or the applied current.

The electrode layer 17 is disposed on the second conductivity type semiconductor layer 340. The electrode layer 17 is preferably composed of a light transmitting electrode layer serving as an ohmic layer, and a thinner thickness is preferable because a thicker thickness may cause light absorption.

Here, the electrode layer 17 may be equal to the width of the second conductivity-type semiconductor layer 340. Meanwhile, as illustrated in FIG. 5, the width of the electrode layer 17 may have a smaller width than the width of the second conductive semiconductor layer 340.

The blocking unit 390 may be disposed at an interface between the second conductivity-type semiconductor layer 340 and the electrode layer 17. Here, the blocking part 390 may be disposed such that one side thereof directly contacts the passivation layer 18.

The blocking unit 390 may be disposed in the depletion region A of the second conductive semiconductor layer 340, and the blocking unit 390 may have a second dopant selectively compared to the second conductive semiconductor layer 340. It may be an overdoped region.

In general, the doping concentration of the second dopant doped in the second conductivity-type semiconductor layer 340 may be set to about 10 ¹⁹ / cm ³ , so that the doping concentration of the second dopant in the blocking portion 390 is about at least 10 ^20. / cm ³ can be set.

Over doping of the second dopant in the blocking unit 390 may be performed by ion implantation.

In this case, since the blocking unit 390 may block a current from flowing due to a difference in doping concentration from the second conductive semiconductor layer 340, the blocking unit 390 may cover the third blocking region C3 corresponding to the entire width of the blocking unit 390. Can be formed.

Substantially, the third blocking region C3 is an arrangement region of the blocking unit 390, and a leakage current that can flow through the depletion region A of the second conductivity-type semiconductor layer 340 is applied to the electrode layer 17. It can play a role of blocking it.

The third blocking region C3 may have a fourth width W4. That is, the blocking unit 390 may have a fourth width W4.

The fourth width W4 may be set in a range of 0.1 nm to 10 μm. Preferably, the third width W4 may be equal to the first width of the depletion region A of the second conductivity-type semiconductor layer 340.

Herein, when the fourth width W4 is 0.1 nm or less, the leakage current flowing through the depletion region A of the second conductivity-type semiconductor layer 340 leaks to the outside through the electrode layer 17 to block leakage current. Can't expect On the other hand, when the fourth width W4 is 10 μm or more, the width of the electrode layer 17 is reduced more than necessary, which may unintentionally finally reduce the light emitting area of the semiconductor device 300.

The passivation layer 18 covers the side surfaces of the semiconductor structures 13, 340, and 15 and the upper surface of the electrode layer 17 to cover the entire surface.

As described above, a plurality of electron traps such as non-bridging-oxygen (NBO) and the like may be formed in SiO ₂ composed of the passivation layer 18, and the electron trap may be formed in the passivation layer 18. It can spread widely within the bandgap.

Through the electron trap, the passivation layer 18 forms a plurality of positive charges, and the positive charges in the passivation layer 18 are formed at the interface of the adjacent second conductive semiconductor layer 340. ) To form a depletion region (A).

Hereinafter, a semiconductor device according to a fourth exemplary embodiment of the present invention will be described with reference to FIG. 8.

8 is a cross-sectional view of a semiconductor device according to a fourth exemplary embodiment of the present invention.

Here, referring to FIG. 7, since the second conductive semiconductor layer 440 is different from the configuration of the semiconductor device illustrated in FIG. 1, a configuration of the second conductive semiconductor layer 440 that is differentiated below will be described. Only the details will be described, and detailed descriptions of the same reference numerals will be omitted.

The semiconductor device 400 according to the fourth embodiment of the present invention may include a substrate 11, a buffer layer 12, semiconductor structures 13, 440, and 15, an electron blocking layer 16, an electrode layer 17, and a passivation layer ( 18), a first bonding pad 19a and a second bonding pad 19b may be included.

The semiconductor structures 13, 440, and 15 are disposed on an upper surface of the substrate 11, and include a first conductive semiconductor layer 13, a second conductive semiconductor layer 440, and an active layer 15. The semiconductor structures 13, 440, and 15 may be separated into a plurality in the process of cutting the substrate 11.

The V-pit P may be formed on the surface of the electron blocking layer 16 in contact with the second conductivity-type semiconductor layer 440. Through this, the number of times that the hole H passes through the electron blocking layer 16 through the V-pit P to the active layer 15 may increase. That is, the hole H entering the V-pit P may be easily moved since the thickness of the electron blocking layer 16 disposed between the active layers 15 is thin or does not exist.

However, the volume of the second conductive semiconductor layer 440 may be extended through the V-pit P, and accordingly, the second doped semiconductor layer 440 and the V-pit P are doped. The doping density of the dopant may be lowered to increase the width of the depletion region A described above.

The second conductive semiconductor layer 440 is in an inward direction of the second conductive semiconductor layer 440 from the interface between the passivation layer 18 and the second conductive semiconductor layer 440 due to the positive charge in the passivation layer 18. As a result, the hole H may include the depletion region A in which the hole H is moved.

In addition, the second conductivity-type semiconductor layer 440 may include a hole region B, which is a region other than the depletion region A formed along the interface of the passivation layer 18.

As described above, the depletion region A of the second conductivity-type semiconductor layer 440 may have a width that varies according to the doping concentration of the second dopant or the applied current.

On the other hand, the second conductive semiconductor layer 440 of the semiconductor device 400 according to the fourth embodiment increases the doping concentration of the second dopant compared to the general second conductive semiconductor layer 14 shown in FIG. The width of the depletion region A may be reduced to the fifth width W5.

Here, the doping concentration of the second dopant of the second conductivity type semiconductor layer 440 may be set in a range of about 10 ¹⁹ / cm ³ to 10 ²⁰ / cm ³ .

When the doping concentration of the second dopant of the second conductive semiconductor layer 440 is 10 ¹⁹ / cm ³ or less, ohmic contact with the electrode layer 17 may be difficult, and the depletion region A of the second conductive semiconductor layer 440 may be difficult. In the case where the first width of the s) becomes large and the current leaking through the depletion region A cannot be adequately blocked, on the contrary, when the doping concentration of the second dopant of the second conductivity-type semiconductor layer 440 is 10 ²⁰ / cm ³ or more, The light transmittance may be significantly lowered, which may cause a problem of reducing the light emission efficiency.

The electrode layer 17 is disposed on the second conductivity type semiconductor layer 440. The electrode layer 17 is preferably composed of a light transmitting electrode layer serving as an ohmic layer, and a thinner thickness is preferable because a thicker thickness may cause light absorption.

Here, the electrode layer 17 may be equal to the width of the second conductivity-type semiconductor layer 440. Meanwhile, as illustrated in FIG. 5, the width of the electrode layer 17 may have a smaller width than the width of the second conductive semiconductor layer 440.

The passivation layer 18 covers the side surfaces of the semiconductor structures 13, 440, and 15 and the upper surface of the electrode layer 17 to cover the entire surface.

As described above, a plurality of electron traps such as non-bridging-oxygen (NBO) and the like may be formed in SiO ₂ composed of the passivation layer 18, and the electron trap may be formed in the passivation layer 18. It can spread widely within the bandgap.

Through the electron trap, the inside of the passivation layer 18 forms a plurality of positive charges, and the positive charges in the passivation layer 18 are formed at the interface of the adjacent second conductive semiconductor layer 440. ) To form a depletion region (A).

Although the above description has been made based on the embodiments, these are merely examples and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains may not have been exemplified above without departing from the essential characteristics of the present embodiments. It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiment can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

Claims (10)

Board;
A semiconductor structure including a first conductive semiconductor layer disposed on the substrate, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer;
An electrode layer spaced apart from an edge of an upper surface of the semiconductor structure; And
A passivation layer disposed on at least part of the side and top surfaces of the semiconductor structure; The semiconductor structure includes a plurality of protruding regions extending downward from a bottom surface of the second conductive semiconductor layer.
The passivation layer is in direct contact with the edge of the upper surface of the semiconductor structure.
The method of claim 1,
The width of the second conductive semiconductor layer is larger than the width of the electrode layer.
The method of claim 1,
The side of the semiconductor structure and the side of the electrode layer is a semiconductor device spaced apart from 0.1nm ~ 10μm range.
The method of claim 1,
The second conductive semiconductor layer includes a blocking portion disposed inside from the side.
The method of claim 4, wherein
One side of the blocking portion is in direct contact with the passivation layer.
The method of claim 5,
The width of the blocking portion is a semiconductor device having a range of 0.1nm ~ 10μm.
The method of claim 6,
And the blocking portion is in schottky contact with the second conductivity-type semiconductor layer.
The method of claim 4, wherein
The blocking part
And a second dopant doped at a higher concentration than the second conductive semiconductor layer.
The method of claim 8,
And a doping concentration of the second dopant in the blocking portion is at least 10 ²⁰ / cm ³ .
A semiconductor structure comprising a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer;
An electrode layer disposed on the semiconductor structure; And
A passivation layer disposed on a side of the semiconductor structure and at least a portion of the electrode layer; Including,
The semiconductor structure includes a plurality of protrusions extending downward from the lower surface of the second conductivity type semiconductor layer,
The doped region is doped with a second dopant,
The doping concentration of the second conductive semiconductor layer and the protruding region is 10 ¹⁹ / cm ³ Semiconductor device having a range of ~ 10 ²⁰ / cm ³ .

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