KR20190050207A - System and method for motion estimation for high-performance hevc encoder - Google Patents

Abstract

The present invention relates to a system and a method for estimating a motion for a high-performance encoder which can effectively reduce a hardware area and an operation time by calculating a result of the sum of absolute differences (SAD) on the whole prediction unit (PU) block by reusing an SAD operation result calculated by 4×4 unit.

Description

[0001] SYSTEM AND METHOD FOR MOTION ESTIMATION FOR HIGH-PERFORMANCE HEVC ENCODER [0002]

The present invention relates to a motion estimation system and method for an HEVC encoder, and more particularly, to a motion estimation system and method for an HEVC encoder, in which a SAD calculation result calculated in 4x4 units is re- To a motion estimation system and method for a high performance HEVC encoder.

Recent developments of various video equipment supporting UHD (Ultra High Definition) ultra high resolution video have increased the interest and demand of users' high resolution images. For this reason, it has become necessary to develop a new video compression technology standard to support high resolution images such as UHD class images. In accordance with this trend, HEVC (High Efficiency Video Coding) has been developed by Moving Picture Experts Group (MPEC) of ISO / IEC and VCEC (Video Coding Experts Group) of ITU-T who have conducted H.264 / AVC standardization It is a new next generation video compression standard developed jointly by Joint-Collaborative Team on Video Coding (JCT-VC) In HEVC, three kinds of coding units are applied and coding of a hierarchical quad-tree structure is performed by applying CU (Coding Unit), PU (Prediction Unit), PU (Prediction Unit) And uses encoding units of various sizes from 64x64 to 8x8. In addition, it shows about twice the compression performance compared to the previous compression codec H.264 / AVC by applying the increase in intra prediction direction, improved motion estimation, motion vector merging, and refined loop filter. However, The computational complexity is greatly increased.

Among the new techniques, motion prediction generates a prediction block that is most similar to the current block. In the process of comparing the correlation between the current PU and the reference block, Sum of Absolute Difference (SAD), which is a simplified correlation measurement method, is used in consideration of the characteristics of test pixels and sub-pixels. Since the SAD operation is repeated for PUs of various sizes ranging from × 8 PU to a maximum of 64 × 64 PU, there is a large amount of computation and computation time.

Specifically, Motion Estimation (ME) of inter-picture prediction is a process performed by an encoder, and is a process of searching for a prediction block having a high degree of correlation with a current PU in a reference picture. As a result of the motion estimation, the coefficients obtained by transforming and quantizing the information of the reference picture list, the reference picture index, the motion vector and the difference signal in units of PU are transmitted to the decoder. The decoder performs a motion compensation process using the surrounding information transmitted from the encoder to generate the same prediction block as the encoder and generate the reconstruction block using the quantized residual signal. 1 shows a motion estimation process.

In the process of comparing the correlation between the current PU and the reference block, SAD (Sum Absolute Difference), which is a simplified correlation measurement method, is used.

Where B _cur denotes the current block, B _ref denotes the motion estimation candidate block existing in the reference picture, i, j denotes the position of the current PU, and l denotes the PU position of the motion estimation target. In motion estimation of an integer pixel, one prediction block is selected by selecting a reference block that minimizes the absolute value of the difference value between the current block and the reference block.

The HEVC also uses the Test Zone Search (TZS) algorithm and the Full-Search algorithm to find the optimal prediction block. In the full-search case, as shown in FIG. 2, the search performance is improved because the search is repeated from the X and Y pixel coordinates (-64, -64) to (64, 64). However, . On the other hand, the TZS algorithm computes only four or eight search points at each step in the grid search, so that the computation speed is fast but the prediction performance is lower than that of the full search.

Accordingly, the present invention proposes a system and method for applying a new algorithm for reducing the computational complexity and computation time of the SAD computation that is repeatedly computed for a high performance HEVC encoder.

Korean Patent Laid-Open Publication No. 10-2014-0056599 (Apr. 20, 2014) Korean Registered Patent No. 10-1621358 (2016.05.17)

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above problems occurring in the prior art, and it is an object of the present invention to provide a method and apparatus for reusing an SAD calculation result calculated in 4 × 4 units in a global search process, The present invention provides a motion estimation system and method for a high performance HEVC encoder that can effectively reduce hardware area and computation time by designing to optimally process PU split block selection in parallel.

According to an aspect of the present invention, there is provided a motion estimation method for a high performance HEVC encoder, the method including: calculating a Merge / SKIP RD-Cost for 2N × 2N; storing a SAD result calculated in units of 4 × 4; (N), N × N, N × 2N, and 2N × N PU modes, calculating a result value by calling a memory index corresponding to a corresponding area from the memory, and calculating an asymmetric partition according to AMP (Asymmetric Motion Partition) And determining the optimal PU mode by calling the memory index of the corresponding area from the memory in the process of calculating the RD-cost for the RD-cost.

Meanwhile, a motion estimation system for a high performance HEVC encoder according to the present invention includes a CLKGen module for dividing a required clock, a MemCtrl module for receiving pixels from a memory, a SAD calculation unit for a 4x4 block unit And a TEnSearch module for obtaining a SAD calculation result for all PU block segmentation using the SAD value calculated in units of 4x4 blocks.

As described above, the motion estimation system and method for a high performance HEVC encoder according to the present invention provides the following effects.

In the global search process, the SAD computation result in 4 × 4 units is reused to calculate the SAD result for the entire PU block and to optimally process the PU split block selection in parallel, effectively reducing the hardware area and computation time .

1 shows a motion estimation process of a conventional HEVC.
FIG. 2 shows a search range based on a 64 × 64 PU block global search in a conventional HEVC.
FIG. 3 illustrates a method for reusing blocks in a motion estimation algorithm for a high performance HEVC encoder according to a preferred embodiment of the present invention.
FIG. 4 shows an overall flow of inter-picture prediction that is proposed for reusing blocks in a motion estimation algorithm for a high performance HEVC encoder according to a preferred embodiment of the present invention.
5 shows an overall block diagram of a motion estimation system in accordance with a preferred embodiment of the present invention.
6 shows an internal structure of a TComRDCost module of a motion estimation system according to a preferred embodiment of the present invention.
7 shows an internal structure of a TEnSearch module of a motion estimation system according to a preferred embodiment of the present invention.
FIG. 8 shows a verification method of a hardware structure according to a preferred embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

Hereinafter, a motion estimation system and method for a high performance HEVC encoder according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 illustrates a method for reusing blocks in a motion estimation algorithm for a high performance HEVC encoder according to a preferred embodiment of the present invention.

In order to effectively reduce the amount of computation in the full-search algorithm, the present invention proposes an algorithm for calculating the SAD result for the entire PU block by reusing the result of the 4 × 4 SAD operation. As shown in FIG. 3, the sum of the SAD values of the 4 × 4 blocks is the same as the SAD value of the 8 × 8 block, and the values of the 4 × 8 blocks are the same as the SAD values of one 16 × 16 block. Therefore, it is possible to reduce the number of iterative SAD operations effectively and to obtain the SAD value for all the PU partitions by storing the 4 × 4 unit SAD result value and calling only the value of the required area (PU division size) and adding the value.

FIG. 4 shows an overall flow of inter-picture prediction that is proposed for reusing blocks in a motion estimation algorithm for a high performance HEVC encoder according to a preferred embodiment of the present invention.

Referring to Fig. 4, in step S410, the Merge / SKIP RD-Cost is calculated for 2N x 2N. Instead of calculating RD-Cost in the order of PU mode such as 2N × 2N, N × N, N × 2N and 2N × N, Inter 2N × 2N mode is performed when 2N × 2N SAD operation is performed and 4 × 4 (Step S420). Then, a memory index corresponding to the area is sequentially called from the memory in order of the NxN, Nx2N, and 2NxN PU modes, and the result value (Steps S431 to S433). Finally, in the asymmetric partitions (step S440), according to the AMP (Asymmetric Motion Partition) condition, the memory index of the corresponding area is called from the memory in the process of calculating the RD-cost, (Steps S451 to S454).

Experimental Example 1

In order to compare the performance improvement of the SAD algorithm proposed in the present invention, all class images were verified using HM 16.12, the HEVC reference software. Performance evaluation index used BD-PSNR and BD-Bitrate for 4 QP (22, 27, 32, 37). Table 1 shows the experimental results.

As a result of comparing the performance of [4] and [5], the proposed SAD algorithm improved the encoding rate by 61% on average compared to the standard software and calculated as Equation 2.

Where TS is the encoding speed, TS _HM is the TS of the HM 16.12 reference software, and TS _propose is the TS of the present invention.

Hereinafter, a motion estimation system for a high performance HEVC encoder of the present invention using the above-described method will be described.

The present invention uses a parallel architecture of 4 × 4 arithmetic units to reduce the amount of computation and computation time that occur when SAD computation is performed in 32 × 32 pixel units and to minimize the hardware area.

The structure of the existing motion estimation SAD calculator is divided into sub-blocks up to 3-depth as shown in Table 2 to determine the optimal SAD value by top-down method and determine the PU block division. do. The structure of the motion estimation system according to the preferred embodiment of the present invention is designed such that the lowest depth is first calculated in a bottom-up manner and the previously computed results are reused up to a higher depth.

As a bottom-up method using 4 × 4 SAD results from 4 × 4, which is the lowest depth, and using 8 × 8 SAD results, it is necessary to process 32 × 32 blocks in the top-down method. While the bottom-up method processes only 16 pixels because it processes 4 × 4 blocks in parallel. Therefore, according to the present invention, hardware size, computation amount, and computation time are greatly reduced.

5 shows an overall block diagram of a motion estimation system in accordance with a preferred embodiment of the present invention. The entire structure of the motion estimation system according to the preferred embodiment of the present invention includes a CLKGen module for dividing a required clock, a MemCtrl module for receiving pixels from a memory, a SAD calculation unit for calculating a SAD in units of 4x4 blocks, A TComRDCost module for storing the SAD calculation result, and a TEnSearch module for obtaining the SAD calculation result for all the PU block division using the SAD value calculation information in units of 4 × 4 blocks.

6 shows an internal structure of a TComRDCost module of a motion estimation system according to a preferred embodiment of the present invention. The TComRDCost module of the motion estimation hardware structure according to the preferred embodiment of the present invention performs the SAD operation in units of 4 × 4 blocks and is composed of 64 operators in order to parallelize the LCU size 32 × 32 in units of 4 × 4. Each SAD Computing module performs an abs (absolute value, absolute) operation on the current block 4 × 4 pixels and the reference block 4 × 4 pixels respectively, and outputs the SAD result value.

7 shows an internal structure of a TEnSearch module of a motion estimation system according to a preferred embodiment of the present invention. The TEnSearch module of the motion estimation hardware structure according to the preferred embodiment of the present invention computes the SAD result for all the divided PUs for the 32 × 32 block in the bottom-up method using the 4 × 4 unit SAD value received from the TComRDCost module do. The SAD result for each depth is calculated using the results of 64 input 4 × 4 SAD operations. The SAD values for the 8x4, 4x8, and 8x8 blocks are calculated in the Depth_3 block. Then, the value of Depth_3 is reused to calculate the value of Depth_2 and the value of Depth_2 to calculate the bottom-up value. Since motion estimation is performed by determining a PU block having the minimum SAD result when determining the optimal PU block division in the motion estimation algorithm and estimating a motion vector, only the value having the minimum SAD calculation result for each block in the Save_min block is determined as SAD_Result .

Experimental Example 2

The hardware structure verification method according to the preferred embodiment of the present invention extracts 32 × 32 block pixel values from HM 16.12, which is the HEVC reference software, as shown in FIG. 8, and outputs HM 16.12 and hardware inputs according to the preferred embodiment of the present invention The results were compared.

As a result of the synthesis with the 65nm CMOS process library, the maximum operation frequency and the total number of gates of the motion estimation algorithm according to the preferred embodiment of the present invention are 255 MHz and 65.1K, respectively, as shown in Table 3.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the present invention is not limited to the disclosed exemplary embodiments, but various modifications may be made without departing from the spirit of the invention.

Claims (12)

A motion estimation method for a high performance HEVC encoder that reuses the sum of absolute difference (SAD) computation results calculated in 4 × 4 units to calculate the SAD result for the entire PU (Prediction Unit) block. In claim 1,
A Motion Estimation Method for High Performance HEVC Encoder Processing Optimal PU Partition Block Selection in Parallel. [Claim 2]
A motion estimation method for a high performance HEVC encoder that stores the SAD operation result calculated in the 4 × 4 unit and calls only the SAD operation result value by the PU division size. Calculating a Merge / SKIP RD-Cost for 2N x 2N,
Storing the SAD result calculated in 4 4 units,
N × N, N × 2N, and 2N × N PU memory indexes of the corresponding area from the memory in the order of the mode,
Determining an optimal PU mode by calling the memory index of the corresponding area from the memory in the process of calculating an RD-cost for an asymmetric partition according to an AMP (Asymmetric Motion Partition) condition, A Motion Estimation Method for High Performance HEVC Encoder. A motion estimation system for a high performance HEVC encoder that reuses SAD computation results in 4 × 4 units and computes SAD results for the entire PU block. In claim 5,
A Motion Estimation System for High Performance HEVC Encoder Processing Optimal PU Partition Block Selection in Parallel. In claim 5 or 6,
A motion estimation system for a high performance HEVC encoder that stores the SAD operation result calculated in the 4 × 4 unit and calls only the SAD operation result value of the PU division size. In claim 5,
A motion estimation system for a high performance HEVC encoder that first computes an optimal SAD value for the lowest depth and reuses the previously computed results up to the highest depth. A CLKGen module that schedules the required clock,
A MemCtrl module for receiving pixels from the memory,
A TComRDCost module for storing a value obtained by calculating a SAD in units of 4x4 blocks with respect to the input pixel;
And a TEnSearch module for obtaining a SAD calculation result for all PU block segmentation using the SAD value calculated in 4x4 block units. In claim 9,
The TComRDCost module performs a SAD operation on a 4x4 block basis and performs a motion estimation for a high performance HEVC encoder composed of a number of SAD operators for parallel processing the LCU (Largest Coding Unit) size in 4x4 units system. In claim 10,
Wherein the SAD operator performs an absolute value operation on each of the 32 values of the current block 4x4 pixels and the reference block 4x4 pixels and outputs the SAD result value. 10. The method according to any one of claims 9 to 11,
The TEnSearch module calculates a SAD result according to each depth in a bottom-up manner using the 4 × 4 unit SAD value received from the TComRDCost module and calculates a SAD result for all divided PUs for a 32 × 32 block Motion estimation system for HEVC encoder.

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