KR20180137639A - Display apparatus - Google Patents

Display apparatus Download PDF

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Publication number
KR20180137639A
KR20180137639A KR1020170076813A KR20170076813A KR20180137639A KR 20180137639 A KR20180137639 A KR 20180137639A KR 1020170076813 A KR1020170076813 A KR 1020170076813A KR 20170076813 A KR20170076813 A KR 20170076813A KR 20180137639 A KR20180137639 A KR 20180137639A
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South Korea
Prior art keywords
wiring
additional
electrode
end
located
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KR1020170076813A
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Korean (ko)
Inventor
이원세
인윤경
김광민
문중수
신애
이지은
Original Assignee
삼성디스플레이 주식회사
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Priority to KR1020170076813A priority Critical patent/KR20180137639A/en
Publication of KR20180137639A publication Critical patent/KR20180137639A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/28Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
    • H01L27/32Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes [OLED]
    • H01L27/3241Matrix-type displays
    • H01L27/3244Active matrix displays
    • H01L27/3248Connection of the pixel electrode to the TFT
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/28Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
    • H01L27/32Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes [OLED]
    • H01L27/3241Matrix-type displays
    • H01L27/3244Active matrix displays
    • H01L27/3276Wiring lines
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2227/00Indexing scheme for devices consisting of a plurality of semiconductor or other solid state components formed in or on a common substrate covered by group H01L27/00
    • H01L2227/32Devices including an organic light emitting device [OLED], e.g. OLED display
    • H01L2227/323Multistep processes for AMOLED
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/28Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
    • H01L27/32Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes [OLED]
    • H01L27/3241Matrix-type displays
    • H01L27/3244Active matrix displays
    • H01L27/3246Banks, i.e. pixel defining layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/28Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
    • H01L27/32Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes [OLED]
    • H01L27/3241Matrix-type displays
    • H01L27/3244Active matrix displays
    • H01L27/3258Insulating layers formed between TFT elements and OLED elements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/28Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
    • H01L27/32Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes [OLED]
    • H01L27/3241Matrix-type displays
    • H01L27/3244Active matrix displays
    • H01L27/326Active matrix displays special geometry or disposition of pixel-elements
    • H01L27/3262Active matrix displays special geometry or disposition of pixel-elements of TFT

Abstract

In the present invention, provided is a display apparatus capable of minimizing the occurrence of pixel defects on an outline of a display area during a manufacturing process. The display apparatus comprises: a substrate having a display area, a first portion in a round shape on an outline, a surrounding area on an outward side of the display area, and a pad area in the surrounding area; a first wiring extended in the direction of the first portion to make a first end located on the pad area and to make the other first end located in the surrounding area; a first additional wiring extended toward the display area to make a first additional end electrically connected to the other first end and to make the other additional end located in the surrounding area; and a first signal line which has one end electrically connected to the other additional end and is extended to the inside of the display area.

Description

[0001]

Embodiments of the present invention relate to a display device, and more particularly, to a display device capable of minimizing the occurrence of defects in pixels at the edge of a display area in a manufacturing process.

Generally, a display device has a display area, and many pixels are located within the display area. If some of the pixels located in the display area become defective pixels, the quality of the image implemented by the display device is inevitably degraded. Therefore, it is necessary to prevent defective pixels from occurring in the manufacturing process or to minimize the incidence of defective pixels.

However, the conventional display device has a problem that a defective pixel is formed at the edge of the display area in the manufacturing process.

The present invention has been made to solve the above-mentioned problems and it is an object of the present invention to provide a display device capable of minimizing the occurrence of defects in the pixels at the edge of the display area during the manufacturing process. However, these problems are exemplary and do not limit the scope of the present invention.

According to an aspect of the present invention, there is provided a display device, comprising: a substrate having a display area where a first portion of an edge has a round shape and a peripheral area outside the display area and having a pad area in the peripheral area; A first wiring extending in the first part direction so that the first other end is located in the peripheral region and a second wiring extending in the first direction so that the first additional end is electrically connected to the first other end, And a first signal line extending in the display area, one end of which is electrically connected to the first additional end, and a first signal line extending into the display area.

And a first bridge wiring connecting the first other end and the first additional end. The first wiring and the first additional wiring may include the same material, and the first bridge wiring may include the same material as the first signal line and may be disposed on the same layer as the first signal line.

The first wiring and the first additional wiring may be disposed on the same layer.

And a first additional bridge wiring located above the first bridge wiring and having both ends connected to the first bridge wiring.

The thin film transistor may further include a thin film transistor located in the display region and including a gate electrode and a source electrode and a drain electrode located on an interlayer insulating film covering the gate electrode, Wherein the first signal line includes the same material as the source electrode and the drain electrode and is disposed on the same layer as the source electrode and the drain electrode .

And a first bridge wiring which connects the first other end and the first additional end and includes the same material as the first signal line and is disposed on the same layer as the first signal line. A pixel electrode electrically connected to either one of the source electrode and the drain electrode; a pixel electrode electrically connected to either the source electrode or the drain electrode, the pixel electrode being connected to the first bridge wiring and having the same material as the pixel electrode, 1 additional bridge wiring can be further provided.

A pixel electrode electrically connected to either one of the source electrode and the drain electrode, and a second additional end connected to the first and second additional ends and including the same material as the pixel electrode, And may further include a first additional bridge wiring disposed therein.

The first other end may be closer to the display area than the first additional end.

Wherein the display region includes first and second opposite edges facing each other and a third edge and a fourth edge positioned between the first edge and the second edge facing each other, Connecting the edge to the fourth edge, and the pad region may be adjacent to the fourth edge of the first edge or the fourth edge. A second wiring line extending in the first partial direction so that the second end is located in the pad region and the second end is located in the peripheral region and is disposed closer to the first edge than the first wiring; 2 further extending toward the display region such that an additional one end is electrically connected to the second other end and a second additional end is located within the peripheral region and is disposed adjacent to the first edge than the first additional wiring, And a second signal line, one end of which is electrically connected to the second additional end and extends into the display area.

In this case, the shortest distance from the imaginary straight line including the fourth edge of the second point at which the second other end and the second additional end are connected to each other is set such that the first other end and the first additional end are connected to each other Can be made longer than the shortest distance from the imaginary straight line of the first point.

A first bridge wiring connecting the first end and the first additional end and a second bridge wiring connecting the second end and the second additional end.

The first TFT includes a first gate electrode, a first source electrode, and a first drain electrode. The first TFT includes a first gate electrode, a first source electrode, and a first drain electrode. Wherein the first gate electrode and the second gate electrode are located in different layers, and the first source electrode, the first drain electrode, the second source electrode, Drain electrode is located on an interlayer insulating film covering the first gate electrode and the second gate electrode, the first wiring and the first additional wiring include the same material as the first gate electrode, And the second wiring and the second additional wiring may include the same material as the second gate electrode and may be disposed on the same layer as the second gate electrode.

Or a first thin film transistor located in the display region and including a first gate electrode, a first source electrode, and a first drain electrode; and a second thin film transistor located in the display region and having a second gate electrode, Wherein the first gate electrode and the second gate electrode are located in different layers, and the first source electrode, the first drain electrode, the second source electrode, 2 drain electrode is located on an interlayer insulating film covering the first gate electrode and the second gate electrode, the first wiring and the second additional wiring include the same material as the first gate electrode, The second wiring and the first additional wiring may include the same material as the second gate electrode and may be disposed on the same layer as the second gate electrode.

The first TFT includes a first gate electrode, a first source electrode, and a first drain electrode. The first TFT includes a first gate electrode, a first source electrode, and a first drain electrode. The first TFT includes a second gate electrode, Wherein the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are located in different layers, and the first signal line and the first The bridge wiring includes the same material as the first source electrode and the first drain electrode, and is disposed on the same layer as the first source electrode and the first drain electrode, and the second signal line and the second bridge wiring The second source electrode, and the second drain electrode, and may be disposed on the same layer as the second source electrode and the second drain electrode.

Or a first thin film transistor located in the display region and including a first gate electrode, a first source electrode, and a first drain electrode, and a second thin film transistor located within the display region and having a second gate electrode, A first additional bridge wiring which is located above the first bridge wiring and has both ends connected to the first bridge wiring and a second additional bridge wiring which is located above the second bridge wiring, And a second additional bridge wiring connected to the bridge wiring, wherein the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are located in different layers, and the first bridge wiring, Wherein the second bridge wiring includes the same material as the first source electrode and the first drain electrode and is disposed on the same layer as the first source electrode and the first drain electrode, 1 additional bridge wiring and the second additional bridge wiring and the second may be a source electrode and the second drain electrode and the same material and disposed on the second source electrode and second drain electrodes in the same layer.

According to another aspect of the present invention, there is provided a display device, comprising: a substrate having a display area where a first portion of an edge has a round shape and a peripheral area outside the display area and having a pad area in the peripheral area; A first interconnection having a first discontinuous point extending in a first direction and a first discontinuity point being physically discontinuous and a first bridge interconnection allowing the first interconnection to be electrically continuous at the first discontinuity point.

A second wiring extending from the pad region toward the first portion and having a second discontinuity point that is physically discontinuous and a second bridge wiring for electrically continuing the second wiring at the second discontinuity point Wherein the second bridge wiring is located farther from the pad area than the first bridge wiring and the second bridge wiring is closer to the edge of the substrate than the first bridge wiring.

Other aspects, features and advantages of the present invention will become apparent from the following detailed description, claims, and drawings.

According to an embodiment of the present invention as described above, it is possible to realize a display device capable of minimizing the occurrence of defects in the pixels at the edges of the display area during the manufacturing process. Of course, the scope of the present invention is not limited by these effects.

FIG. 1 is a conceptual view schematically showing an aspect of a manufacturing process of a display device according to an embodiment of the present invention.
Fig. 2 is a conceptual diagram schematically showing part A of Fig. 1. Fig.
3 is a conceptual diagram schematically showing a portion B in Fig.
Figure 4 is a cross-sectional view schematically showing the parts of Figure 3;
5 is a cross-sectional view schematically showing portions of a display device according to another embodiment of the present invention.
6 is a cross-sectional view schematically showing portions of a display device according to another embodiment of the present invention.
7 is a cross-sectional view schematically showing portions of a display device according to another embodiment of the present invention.
8 is a cross-sectional view schematically showing portions of a display device according to another embodiment of the present invention.
9 is a cross-sectional view schematically showing portions of a display device according to another embodiment of the present invention.
10 is a cross-sectional view schematically showing portions of a display device according to another embodiment of the present invention.
11 is a cross-sectional view schematically showing portions of a display device according to another embodiment of the present invention.
12 is a cross-sectional view schematically showing portions of a display device according to another embodiment of the present invention.
13 is a cross-sectional view schematically showing portions of a display device according to another embodiment of the present invention.
14 is a cross-sectional view schematically showing parts of a display device according to another embodiment of the present invention.
15 is a cross-sectional view schematically showing portions of a display device according to another embodiment of the present invention.
16 is a cross-sectional view schematically showing parts of a display device according to another embodiment of the present invention.
17 is a cross-sectional view schematically showing parts of a display device according to another embodiment of the present invention.
18 is a cross-sectional view schematically showing portions of a display device according to another embodiment of the present invention.
19 is a cross-sectional view schematically showing portions of a display device according to another embodiment of the present invention.
20 is a cross-sectional view schematically showing portions of a display device according to another embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention is capable of various modifications and various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention and methods of achieving them will be apparent with reference to the embodiments described in detail below with reference to the drawings. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein like reference numerals refer to like or corresponding components throughout the drawings, and a duplicate description thereof will be omitted .

In the following embodiments, when various components such as layers, films, regions, plates, and the like are referred to as being " on " other components, . Also, for convenience of explanation, the components may be exaggerated or reduced in size. For example, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, and thus the present invention is not necessarily limited to those shown in the drawings.

In the following embodiments, the x-axis, the y-axis, and the z-axis are not limited to three axes on the orthogonal coordinate system, and can be interpreted in a broad sense including the three axes. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but may refer to different directions that are not orthogonal to each other.

FIG. 1 is a conceptual view schematically showing a manufacturing process of a display device according to an embodiment of the present invention. FIG. 2 is a conceptual view schematically showing part A of FIG. 1, Fig. 4 is a cross-sectional view schematically showing the parts of Fig. 3; Fig.

The display device according to the present embodiment has a display area DA in which a plurality of pixels are located and a peripheral area PA located outside the display area DA as shown in FIG. It may be understood that the substrate 100 has such a display area DA and a peripheral area PA. The peripheral area PA includes a pad area PADA, which is an area where various electronic elements, a printed circuit board, and the like are electrically attached.

1 may be understood as a plan view showing the appearance of a substrate or the like during the manufacturing process. In an electronic device such as a smart phone including a final display device or a display device, a part of the substrate or the like can be bent in order to minimize the area of the peripheral area PA recognized by the user. The peripheral area PA may include the bending area BA such that the bending area BA is positioned between the pad area PADA and the display area DA as shown in Fig. In this case, the substrate may be bent in the bending area BA so that at least a part of the pad area PADA overlaps with the display area DA. Of course, the bending direction is set so that the pad area PADA does not cover the display area DA but the pad area PADA is located behind the display area DA. Accordingly, the user recognizes that the display area DA occupies most of the display device.

Such a substrate 100 may comprise a variety of materials having flexible or ben-double characteristics, such as polyethersulphone (PES), polyacrylate, polyetherimide (PEI), polyethylene BACKGROUND OF THE INVENTION [0002] The present invention relates to a method of manufacturing a semiconductor device, which includes a step of forming a semiconductor layer on a semiconductor substrate, the method comprising: forming a semiconductor layer on a semiconductor substrate; forming a semiconductor layer on the semiconductor substrate; forming a semiconductor layer on the semiconductor substrate; , PC) or cellulose acetate propionate (CAP). Of course, the substrate 100 may have a multi-layer structure (not shown) comprising two layers each containing such a polymeric resin and a barrier layer comprising an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride, etc.) interposed between the layers And various modifications are possible.

The edges of the display area DA may have a rectangular or square-like shape as a whole. However, as shown in Figs. 1 and 2, the display area DA has the rounded shape of the first portion P1 of the edge. Specifically, the display area DA has a first edge E1 and a second edge E2 opposite to each other, and a third edge (a first edge E1 and a second edge E2) which are opposite to each other and are located between the first edge E1 and the second edge E2 E3 and a fourth edge E4. The pad region PADA is adjacent to a fourth edge E4 of the first to fourth edges E1 to E4. At this time, the first portion P1 having a round shape connects the first edge E1 and the fourth edge E4. Of course, the display area DA may have a round shape in addition to the first part P1 as well as the second part P2 of the edge. The second portion P2 connects the second edge E2 and the fourth edge E4. Also, the display area DA may have a round shape at other portions of the edge.

For reference, FIG. 3 is a conceptual diagram schematically showing part B of FIG. 2, showing a part of the first part P1. 1 and 2, when a user using the display device according to the present embodiment or an electronic device having the display device according to the present embodiment observes under a normal use environment, the first portion P1 may have a round shape, that is, a curved shape . However, in an environment in which the first portion P1 can be enlarged and wirings having a width of several micrometers or tens of micrometers can be observed, as shown in Fig. 3, the first portion P1 is bent in a straight line shape . ≪ / RTI > As shown in FIG. 3, if the first portion P1 is enlarged as described above and the first portion P1 appears to have a linear shape bent a plurality of times, in a normal use environment, the first portion P1 may have a round shape , That is, having a curved shape, the following description will be made assuming that the first part P1 has a round shape. A plurality of pixels PX1, PX1-1, PX1-2, PX2, PX3 are located in the display area DA along the first part P1 which is round in shape. For convenience, only a part of a plurality of pixels in the display area DA is shown in FIG.

Various signals may be applied to the display area DA. For example, a data signal for adjusting the brightness of each pixel may be applied to the display area DA, and various wirings such as a data line may be located in the display area DA. Hereinafter, such wiring and the like will be described.

The display device according to the present embodiment includes a first wiring W1, a first additional wiring AW1, and a first signal line S1. The first wiring W1 extends in the first portion P1 direction so that the first end is located in the pad region PADA and the first end is located in the peripheral region PA. Although only a part of the first wiring W1 is shown in FIG. 3, since the first end of the first wiring W1 is located in the pad area PADA as shown in FIGS. 1 and 2, W1 may be long wirings. In addition, the first wiring W1 has a long shape extending from the pad region PADA to the first portion P1, and may have a bent shape a plurality of times as shown in Figs. 1 and 2.

The first additional wiring AW1 is electrically connected to the first other end of the first wiring W1 at the first additional end and extended toward the display area DA so that the first additional end is located in the peripheral area PA. do. Since the first additional end of the first additional wiring AW1 and the first additional end of the first additional wiring AW1 are all located in the peripheral area PA, the first additional wiring AW1 is not in the display area DA but in the peripheral area PA. . Of course, since the first additional wiring AW1 extends toward the display area DA, the first additional end of the first additional wiring AW1 is positioned near the display area DA. In order to electrically connect the first additional end of the first additional wiring AW1 to the first other end of the first wiring W1, the display device includes a first additional wiring AW1 and a first additional wiring AW1, And a first bridge wiring BW1 that contacts the other end of the first bridge wiring W1.

Most of the first signal line S1 is located in the display area DA. However, since one end of the first signal line S1 is located in the peripheral area PA and is electrically connected to the first additional end of the first additional wiring AW1, the first signal line S1 is connected to the first additional line AW1 in the display area DA It is not only located. In other words, it can be understood that the first signal line S1 is electrically connected to the first additional end of the first additional wiring AW1 and extended into the display area DA. The first signal line S1 may be, for example, a data line for transmitting a data signal to pixels located in the display area DA.

In the display device according to this embodiment, it is possible to minimize the occurrence of defects in the pixels at the edges of the display area during the manufacturing process. In the manufacturing process, the first wiring W1, the first additional wiring AW1, and the first signal line S1 are not all formed at the same time. For example, the first wiring W1 and the first additional wiring AW1 are simultaneously formed of the same material, and the first signal line S1 and the first bridge wiring BW1 are connected to the first wiring W1 and the first additional wiring AW1 may be formed. That is, the first signal line S1 and the first bridge wiring BW1 may be located in a different layer from the first wiring W1 and the first additional wiring AW1.

The first wirings W1 and the first additional wirings AW1 are formed of a metal such as molybdenum or aluminum, and may be formed by a method such as sputtering. When forming the first interlayer insulating film 131 (see FIG. 4) after forming the first wiring W1 and the first additional wiring AW1, a method such as PECVD may be used. In this case, charges can be accumulated in the preformed first wirings W1 and the first additional wirings AW1. Particularly, when the insulating layer or the like is formed by the PECVD method after the first wirings W1 and the first additional wirings AW1 are formed, since the plasma is used, the first wirings W1 and the first additional wirings Charge can be accumulated in the light-emitting element AW1. The total length of the first wirings W1 among the first wirings W1 and the first additional wirings AW1 is relatively long and the total amount of charges accumulated in the first wirings W1 is larger than the total amount of charges accumulated in the first additional wirings AW1 Becomes larger than the total amount of accumulated charges.

The first wirings W1 themselves may be formed longer without forming the first additional wirings AW1 so that the first other end of the first wirings W1 is positioned near the display area DA and the first signal line S1 May be connected to the first end of the first wiring W1. In this case, the first wiring W1 is formed before the first signal line S1 is formed. The first wiring W1 has the first end located in the pad region PADA and the first end positioned in the display region DA The amount of charge accumulated in the first wiring W1 in the process of forming the insulating layer or the like after the formation of the first wiring W1 becomes very large.

In the display area DA, a semiconductor layer, which is a component of the thin film transistor, and an insulating layer covering the semiconductor layer are formed. Under such circumstances, the long first wiring W1 is formed. Therefore, in this case, between the first other end of the first wiring W1 located near the display area DA and the semiconductor layer to be a component of the thin film transistor in the pixel in the display area DA, a strong electromagnetic field . This is because a large amount of charges are accumulated in the first wiring W1. Such a strong electromagnetic field causes a phenomenon such as dielectric breakdown (dielectric breakdown) in the insulating layer covering the semiconductor layer, and even if the thin film transistor is completed later, the thin film transistor may not operate properly. This eventually causes the pixel to become a defective pixel.

In the case of the display device according to the present embodiment, such a problem can be prevented or minimized. That is, the first wirings W1, which are relatively long among the first wirings W1 and the first additional wirings AW1, are not positioned adjacent to the display area DA, ). ≪ / RTI > Therefore, even if a large amount of charge is accumulated in the first wiring W1 during the manufacturing process, it is possible to prevent insulation breakdown or the like between the insulating layer covering the semiconductor layer in the display area DA and the first wiring W1 have. Therefore, in the case of the display device according to the present embodiment, it is possible to effectively prevent or minimize the occurrence of defective pixels in the manufacturing process. Of course, while the first additional wiring AW1 is located near the display area DA, the length of the first additional wiring AW1 is shorter than that of the first wiring W1, The amount of charge accumulated in the additional wiring AW1 becomes small. Therefore, insulation breakdown or the like does not occur between the insulating layer covering the semiconductor layer in the display area DA and the first additional end of the first additional wiring AW1.

Of course, after the first wiring W1 and the first additional wiring AW1 are formed, the first bridge wiring BW1 is formed to electrically connect the first wiring W1 and the first additional wiring AW1. However, in this case, the first signal line S1 electrically connected to the first additional wiring AW1 is simultaneously formed of the same material when the first bridge wiring BW1 is formed. Therefore, A large amount of charges move to the first signal line S1 instead of only to the first additional wiring AW1 through the first bridge wiring BW1. The first signal line S1 is formed to extend in the y-axis direction so as to pass through the plurality of pixels PX1, PX1-1, PX1-2, PX1-3 in the display area DA. For example, the first signal line S1 has a long shape extending from the vicinity of the fourth edge E4 to the vicinity of the third edge E3. Accordingly, the charges accumulated in the first wiring W1 spread along the first additional wiring AW1 and the first signal line S1, so that a strong electromagnetic field is not formed locally at a specific position. Therefore, the problem of insulation breakdown of the insulating layer does not occur. For reference, the first signal line S1 and the like may include a metal such as titanium or aluminum, and may have a single layer or a multilayer structure. For example, the signal line S1 may have a three-layer structure of titanium / aluminum / titanium.

In such a display device, the first other end of the first wiring W1 may be closer to the display area DA than the first additional end of the first additional wiring AW1 (in the x-axis direction). The second wiring W2 and the third wiring W3 are also present as described later and the first wiring W1 to the third wiring W3 are formed in the pad region PADA) in the direction of the display area DA. At this time, the first to third wirings W1 to W3 have a shape spreading from the pad area PADA toward the display area DA. Considering the layout of the first wirings W1 to W3 and the first to fourth additional wirings AW1 to AW3 connected to the first wirings W1 to W3, The first additional end of the first additional wiring AW1 is made to be closer to the display area DA than the first additional end of the first additional wiring AW1 (in the x-axis direction) It is preferable that the first wiring W1 is further away from the display area DA than the first other end (in the x-axis direction) of the first wiring W1.

The first wiring W1 may be electrically connected to the first signal line S1 and may transmit an electrical signal such as a data signal to the pixels PX1, PX1-1, PX1-2, PX1-3 in a row. Electric signals such as a data signal must be transmitted to pixels in a row other than the one row. For this purpose, other wirings may be arranged in the peripheral area PA. For example, as shown in Fig. 3, the second wiring W2 may be disposed in the peripheral area PA. 3, the second end of the second wiring W2 is located in the pad region PADA and the second end of the second wiring W2 is located in the peripheral region PA in the direction of the first portion P1 And the second wiring W2 are disposed closer to the first edge E1 (see FIG. 2) than the first wiring W1. The second wiring W2 transmits an electrical signal to the pixel PX2 or the like. To this end, the second wiring W2 is electrically connected to the second signal line S2 through the second bridge wiring BW2 and the second additional wiring AW2.

The second additional end of the second additional wiring AW2 is electrically connected to the second end of the second wiring W2 through the second bridge wiring BW2 and the second additional end of the second additional wiring AW2 is electrically connected to the other end of the second wiring W2 through the second bridge wiring BW2, Extends toward the display area DA so as to be located in the peripheral area PA. Of course, the second additional wiring AW2 is also arranged closer to the first edge E1 than the first additional wiring AW1. The second additional end of the second additional wiring AW2 is electrically connected to one end of the second signal line S2 and the second signal line S2 extends into the display area DA , The pixel PX2, and the like.

The positional relationship between the second wiring W2, the second bridge wiring BW2, the second additional wiring AW2 and the second signal line S2 is the same as the positional relationship between the first wiring W1 and the first bridge wiring BW1, It goes without saying that the above-described contents can be directly applied to the positional relationship between the first additional wiring AW1 and the first signal line S1. At this time, the second point where the second other end of the second wiring W2 and the second additional end of the second additional wiring AW2 are connected to each other, that is, the point where the second bridge wiring BW2 is located, The first additional end of the first additional wiring AW1 and the first additional end of the first additional wiring AW1 are located farther from the pad area PADA than the first point where the first additional end of the first additional wiring AW1 and the first additional end of the first additional wiring AW1 are connected to each other, can do. In FIG. 3, the position of the second bridge wiring BW2 is located farther from the pad region PADA in the + y direction than the position of the first bridge wiring BW1. This is because the shortest distance from the imaginary straight line of the second bridge wiring BW2 assumes the shortest distance from the imaginary straight line including the fourth edge E4 (see Fig. 2) The shortest distance from the straight line of FIG.

Of course, as shown in FIG. 3, there may also be a third wiring W3 disposed closer to the first edge E1 (see FIG. 2) than the first wiring W1 and the second wiring W2. The third wiring W3 is electrically connected to the third signal line S3 through the third bridge wiring BW3 and the third additional wiring AW3 and is capable of applying an electrical signal to the pixel PX3 . In this case, the third bridge wiring BW3 may be located farther from the pad region PADA than the point where the second bridge wiring BW2 is located. This is because the first portion P1 of the edge of the display area DA has a round shape so that the positions of the first to third bridge wirings BW1 to BW3 are changed according to the shape of the first portion P1 It is necessary to adjust.

As the length of each of the first to fourth additional wirings AW1 to AW3 becomes longer, the amount of charges accumulated in the first to fourth additional wirings AW1 to AW3 increases, thereby increasing the possibility of failure in pixels in adjacent display areas. Therefore, it is necessary to prevent the lengths of the first to fourth additional wirings AW1 to AW3 from becoming long.

For this purpose, the positions of the first bridge wiring BW1 to the third bridge wiring BW3 are adjusted in accordance with the shape of the rounded first portion P1 to form the first additional wiring AW1 to the third additional wiring AW3) should not be unnecessarily long. The positions of the first bridge wiring BW1 to the third bridge wiring BW3 thus adjusted are the same as those described above. That is, the third bridge wiring BW3 is located farther away from the pad area PADA than the second bridge wiring BW2, and the second bridge wiring BW2 is located at a position where the first bridge wiring BW1 is located May be located farther away from the pad area PADA than the pad area PADA.

Since the first wirings W1 and the first additional wirings AW1 are simultaneously formed of the same material in the manufacturing process as described above, the first wirings W1 and the first additional wirings AW1 are made of the same material . Of course, the first wiring W1 and the first additional wiring AW1 can be located on the same layer. Since the first signal line S1 and the first bridge wiring BW1 are simultaneously formed of the same material as described above, the first signal line S1 and the first bridge wiring BW1 may include the same material . Of course, the first signal line S1 and the first bridge wiring BW1 may be located on the same layer. And may further include a first additional bridge wiring which is located above the first bridge wiring BW1 and whose both ends are connected to the first bridge wiring BW1. In this case, since the first bridge wiring BW1 and the first additional bridge wiring are connected in parallel, the overall resistance can be reduced when the first bridge wiring BW1 and the first additional bridge wiring are taken into consideration.

Hereinafter, the present embodiment will be described in more detail with reference to Fig. 4, which is a cross-sectional view schematically showing the portions of Fig. Fig. 4 is a cross-sectional view showing portions spaced apart from each other in Fig. 3, and does not show components adjacent to each other. For example, in FIG. 4, the pixel PX1 and the pixel PX2 are shown. As shown in FIG. 3, the pixels PX1 and PX2 are not adjacent to each other. FIG. 4 is a cross-sectional view showing portions separated from each other in FIG. 3, and cross-sections at mutually spaced portions are not cross-sectional views in the same direction. The cross section taken along the first signal line S1 and the first additional wiring AW1 is a cross section taken along the direction in which the first signal line S1 extends (y-axis direction) , The first wiring W1 and the first bridge wiring BW1 are taken along a section along the direction in which the first bridge wiring BW1 extends (x-axis direction).

4, the display region of the substrate 100 includes not only the display elements 310 and 320 but also the thin film transistors 210 and 220 to which the display elements 310 and 320 are electrically connected . In FIG. 4, the organic light emitting elements are disposed as the display elements 310 and 320 in the display area DA. It is understood that the organic light emitting devices are electrically connected to the thin film transistors 210 and 220 because the pixel electrodes 311 and 321 are electrically connected to the thin film transistors 210 and 220.

In FIG. 4, the first thin film transistor 210 is located in the pixel PX1, the second thin film transistor 220 is located in the pixel PX2, the first display element 310 is the first thin film transistor 210 And the second display device 320 is electrically connected to the second thin film transistor 220. The second thin film transistor 220 is electrically connected to the second thin film transistor 220. [ Hereinafter, the first TFT 210 and the first TFT 310 will be described for convenience, and the present invention may be applied to the second TFT 220 and the second TFT 320. The description of the second semiconductor layer 221, the second gate electrode 223, the second source electrode 225a and the second drain electrode 225b of the second thin film transistor 220, The description of the pixel electrode 321, the counter electrode 325 and the intermediate layer 323 of the pixel electrode 320 will be omitted. The counter electrode 325 of the second display device 320 may be integral with the counter electrode 315 of the first display device 310. [

The first thin film transistor 210 includes a first semiconductor layer 211 including amorphous silicon, polysilicon or organic semiconductor material, a first gate electrode 213, a first source electrode 215a and a first drain electrode 215b ). A first gate insulating film 121 including an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride is formed in order to ensure the insulating property between the first semiconductor layer 211 and the first gate electrode 213 And may be interposed between the first semiconductor layer 211 and the first gate electrode 213. A first interlayer insulating layer 131 including an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride may be disposed on the first gate electrode 213. The first interlayer insulating layer 131 may include a first source electrode 215a, And the first drain electrode 215b may be disposed on such a first interlayer insulating film 131. [ The insulating film containing an inorganic material may be formed through CVD or ALD (atomic layer deposition). This also applies to the following embodiments and modifications thereof.

A buffer layer 110 including an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride may be interposed between the first thin film transistor 210 and the substrate 100 having such a structure. The buffer layer 110 prevents or minimizes impurities from the substrate 100 or the like from penetrating into the first semiconductor layer 211 of the first thin film transistor 210, can do.

A planarization layer 140 may be disposed on the first thin film transistor 210. For example, as shown in FIG. 4, when the organic light emitting diode is disposed on the first thin film transistor 210, the planarization layer 140 may substantially flatten the upper portion of the protective film covering the first thin film transistor 210 have. The planarization layer 140 may be formed of an organic material such as acrylic, BCB (benzocyclobutene), or HMDSO (hexamethyldisiloxane). Although the planarization layer 140 is shown as a single layer in FIG. 4, the planarization layer 140 may be a multi-layered structure.

In the display area DA of the substrate 100, the first display device 310 may be positioned on the planarization layer 140. The first display element 310 may be an organic light emitting element having a pixel electrode 311, an opposite electrode 315, and an intermediate layer 313 interposed therebetween and including a light emitting layer. The pixel electrode 311 is in contact with any one of the first source electrode 215a and the first drain electrode 215b through an opening formed in the planarization layer 140 or the like as shown in FIG. ).

The pixel defining layer 150 may be disposed on the planarization layer 140. The pixel defining layer 150 serves to define a pixel by having an opening corresponding to each of the sub-pixels, that is, at least a central portion of the pixel electrode 311 is exposed. 4, the pixel defining layer 150 is formed by increasing the distance between the edge of the pixel electrode 311 and the counter electrode 315 above the pixel electrode 311, And prevents the occurrence of an arc or the like at the edge of the substrate. The pixel defining layer 150 may be formed of an organic material such as polyimide or hexamethyldisiloxane (HMDSO).

The intermediate layer 313 of the organic light emitting diode may include a low molecular weight or a high molecular weight material. When the intermediate layer 313 includes a low molecular material, the intermediate layer 313 may include a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (Electron Transport Layer), and EIL (Electron Injection Layer) may be stacked in a single or a composite structure, and they may be formed by a vacuum deposition method. When the intermediate layer 313 includes a polymer material, the intermediate layer 313 may have a structure including a hole transport layer (HTL) and a light emitting layer (EML). In this case, the hole transport layer may include PEDOT, and the light emitting layer may include a polymer material such as poly-phenylenevinylene (PPV) and polyfluorene. The intermediate layer 313 may be formed by a screen printing method, an inkjet printing method, a laser induced thermal imaging (LITI) method, or the like. Of course, the intermediate layer 313 is not necessarily limited to this, and may have various structures. The intermediate layer 313 may include a layer that is integrated over the plurality of pixel electrodes 311 and 321 and may include a patterned layer corresponding to each of the plurality of pixel electrodes 311 and 321 have.

The counter electrode 315 is disposed on the display area DA, and may be disposed to cover the display area DA. That is, the counter electrode 315 may be integrally formed with a plurality of organic light emitting elements to correspond to the plurality of pixel electrodes 311 and 321.

Since such an organic light emitting element can be easily damaged by moisture or oxygen from the outside, an encapsulating layer (not shown) can cover and protect the organic light emitting element. The sealing layer may cover the display area DA and extend to at least a part of the peripheral area PA. Such an encapsulating layer may comprise a first inorganic encapsulating layer, an organic encapsulating layer and a second inorganic encapsulation layer.

The first wirings W1 and the first additional wirings AW1 may be formed of the same material at the same time so that the first wirings W1 and the first additional wirings AW1 may include the same material have. The first wirings W1 and the first additional wirings AW1 may be formed of the same material on the first gate insulating film 121 at the same time when the first gate electrode 213 is formed. Accordingly, the first wiring W1 and the first additional wiring AW1 include the same material as the first gate electrode 213 and are disposed on the same layer. As described above, the first signal line S1 and the first bridge wiring BW1 are formed simultaneously with the same material. Specifically, the first signal line S1 and the first bridge wiring BW1 are connected to the first source electrode The first drain electrode 215a and the first drain electrode 215b may be formed of the same material on the first interlayer insulating film 131 at the same time. The first signal line S1 and the first bridge wiring BW1 include the same material as the first source electrode 215a and the first drain electrode 215b and are disposed on the same layer.

Considering the manufacturing process, the first gate electrode 213, the first wiring W1, and the first additional wiring AW1 are formed, and then the first interlayer insulating film 131 covering the first gate electrode 213, the first wiring W1, and the first additional wiring AW1 is formed. The first end of the first wiring W1 is electrically connected to the pad region PADA even if a large amount of charges are stored in the first wiring W1 after the first wiring W1 is formed, And the first other end is located at a distance from the display area DA, it is possible to prevent the occurrence of defects as described above in the display area DA due to the large amount of charges accumulated in the first wiring W1 . The first additional wirings AW1 are arranged such that the first additional end is located adjacent to the first other end of the first wiring W1 and the first additional end is located adjacent to the display area DA, The amount of charge accumulated is not so small, and the display area DA is not defective.

Thereafter, a plurality of contact holes are formed in the first interlayer insulating film 131 and the first source electrode 215a, the first drain electrode 215b, the first signal line S1 and the first bridge wiring BW1 are simultaneously formed . The first signal line S1 is connected to the first additional end of the first additional wiring AW1 through the contact hole and the first bridge wiring BW1 is connected to the first additional wiring AW1 through the contact holes. And the first additional end and the first other end of the first wiring W1, respectively. Since the first signal line S1 and the first bridge wiring BW1 are formed at the same time in this manner, the charges accumulated in the first wiring W1 are transferred to the first signal line S1 through the first additional wiring AW1 and the first signal line S1 in an instant So that it does not cause a defect in the display area DA because it does not form a local strong electromagnetic field.

5 is a cross-sectional view schematically showing portions of a display device according to another embodiment of the present invention. The display device according to this embodiment differs from the above-described display device with reference to Fig. 4 in that it further includes a first additional bridge wiring ABW1.

A planarization layer 140 covering the first source electrode 215a, the first drain electrode 215b, the first signal line S1 and the first bridge wiring BW1 is formed in the manufacturing process and the planarization layer 140 is formed on the planarization layer 140 The pixel electrodes 311 and 321 are formed on the planarization layer 140 after the contact holes for connecting the pixel electrodes 311 and 321 to the first and second thin film transistors 210 and 220 are formed, . In forming the contact holes, contact holes for exposing the first bridge wiring BW1 are formed at the same time. When the pixel electrodes 311 and 321 are formed, both ends of the first bridge wiring The first additional bridge wirings ABW1 connected to the first bridge wiring BW1 can be simultaneously formed from the same material. In this case, since the first bridge wiring BW1 and the first additional bridge wiring ABW1 are connected in parallel, the overall resistance is reduced when the first bridge wiring BW1 and the first additional bridge wiring ABW1 are considered .

6, which is a cross-sectional view schematically showing parts of a display device according to another embodiment of the present invention, a first additional wiring line without a first bridge wiring BW1, Only the bridge wiring ABW1 may be present. That is, the first additional bridge wiring ABW1 is in contact with the first other end of the first wiring W1 and the first additional end of the first additional wiring AW1, and the first additional wiring W1 and the first additional wiring AW1 may be electrically connected. Of course, the first additional bridge wiring ABW1 may be formed of the same material at the same time when the pixel electrodes 311 and 321 are formed.

In the display device according to this embodiment, the first ends of the first wirings W1, in which many charges are accumulated, are located in the pad region PADA and the first ends of the first wirings W1 are located a certain distance from the display region DA It is possible to prevent the occurrence of defects as described above in the display area DA due to the large amount of charges accumulated in the first wiring W1. The time at which the first wiring W1 in which a large amount of electric charge is accumulated is electrically connected to the first additional wiring AW1 and the first signal line S1 by the first additional bridge wiring ABW1, After the formation of the thin film transistors 210, 220, Therefore, it is possible to effectively prevent or minimize the occurrence of defects in the thin film transistors 210 and 220 during the manufacturing process.

7, which is a cross-sectional view schematically showing parts of a display device according to another embodiment of the present invention, the first additional bridge wiring ABW1 is connected to the first wiring W1 of the first wiring W1, And may be indirectly connected to the first additional end of the first additional wiring AW1. That is, the first and second source electrodes 215a and 215b are formed of the same material as the first source electrode 215a and the first drain electrode 215b and are located on the same layer and have mutually spaced connection layers BW1 ' One is interposed between the first additional wiring AW1 and the additional bridge wiring ABW1 and the other of the connecting layers BW1 'is interposed between the first wiring W1 and the further bridge wiring ABW1, The first additional bridge wiring ABW1 may be electrically connected to the first further end of the first wiring W1 and the first additional end of the first additional wiring AW1. The mutually spaced connection layers BW1 'may be formed at the same time when the first source electrode 215a and the first drain electrode 215b are formed.

8 is a cross-sectional view schematically showing portions of a display device according to another embodiment of the present invention. The display device according to the present embodiment differs from the display device according to the embodiment described above with reference to FIG. 4 in the display area DA in that the first thin film transistor 210 And the second gate electrode 223 of the second thin film transistor 220 is located on such a second gate insulating film 122. The second gate insulating film 122 is formed on the second gate insulating film 122, . That is, the first gate electrode 213 and the second gate electrode 223 are located in different layers. Of course, the first source electrode 215a, the first drain electrode 215b, the second source electrode 225a and the second drain electrode 225b are formed to cover the first gate electrode 213 and the second gate electrode 223 And is located on the first interlayer insulating film 131.

The second gate insulating film 122 extends to the peripheral region PA and also covers the first wiring W1 and the first additional wiring AW1. The first signal line S1 contacts the first additional wiring AW1 through the second gate insulating film 122 and the contact hole passing through the first interlayer insulating film 131 and the first bridge wiring BW1 Contact the first additional wiring AW1 and the first wiring W1 through the contact holes passing through the second gate insulating film 122 and the first interlayer insulating film 131. [

On the other hand, in the case of the display device according to the present embodiment, the positions of the second wirings W2 and the second additional wirings AW2 may be different from the positions of the first wirings W1 and the first additional wirings AW1 have. That is, the first wiring W1 and the first additional wiring AW1 are located on the first gate insulating film 121 in the same manner as the first gate electrode 213, while the second wiring W2 and the second additional wiring AW1 AW2 may be located on the second gate insulating film 122 in the same manner as the second gate electrode 223. Of course, in this case, the first wiring W1 and the first additional wiring AW1 include the same material as the first gate electrode 213, and the second wiring W2 and the second additional wiring AW2 include the same material as the second gate Electrode 223 as shown in FIG. The first wirings W1 and the first additional wirings AW1 may be formed simultaneously with the first gate electrode 213 and the second wirings W2 and the second additional wirings AW2 may be formed simultaneously 2 gate electrode 223, as shown in FIG.

As the resolution of the display device increases, the gap between the first wiring W1 and the second wiring W2 becomes narrower. If the first wirings W1 and the second wirings W2 are located on the same layer, the widths of the first wirings W1 and the second wirings W2 must be narrowed in order to prevent them from being electrically connected to each other This causes problems such as an increase in resistance in the first wiring W1 and the second wiring W2. However, in the case of the display device according to the present embodiment, since the first wirings W1 and the second wirings W2 are positioned in different layers, each of the first wirings W1 and the second wirings W2 has a sufficient width They are not electrically connected to each other. This is also applied to the first additional wiring AW1 and the second additional wiring AW2. This also applies to the following embodiments and modifications thereof.

8, the first wiring W1 electrically connected to the pixel PX1 and the first additional wiring AW1 are located on the same layer as the first gate electrode 213 and are electrically connected to the pixel PX2. The second wirings W2 and the second additional wirings AW2 are located on the same layer as the second gate electrodes 223, but the present invention is not limited thereto. 8, the first wiring W1 electrically connected to the pixel PX1 and the first additional wiring AW1 are located on the same layer as the second gate electrode 223, and the pixel PX2, The second wirings W2 and the second additional wirings AW2 electrically connected to the first gate electrode 213 may be located on the same layer as the first gate electrode 213. [

The present invention is not limited thereto. For example, as shown in FIG. 9, which is a cross-sectional view schematically showing portions of a display device according to another embodiment of the present invention, a first wiring W1 and a second additional wiring AW2 are formed on a first gate electrode 213 and the second wiring W2 and the first additional wiring AW1 may be located on the same layer as the second gate electrode 223. [ In this case, the first wiring W1 and the second additional wiring AW2 include the same material as the first gate electrode 213, and the second wiring W2 and the first additional wiring AW1 include the same material Electrode 223 may be formed of the same material.

10, which is a cross-sectional view schematically showing parts of a display device according to another embodiment of the present invention, a second wiring W2 and a first additional wiring AW1 are formed on a first gate electrode The first wirings W1 and the second additional wirings AW2 may be located on the same layer as the second gate electrodes 223. In this case, In this case, the second wiring W2 and the first additional wiring AW1 include the same material as the first gate electrode 213, and the first wiring W1 and the second additional wiring AW2 include the same material Electrode 223 may be formed of the same material.

8 to 10, the first thin film transistor 210 is located in the pixel PX1 and the second thin film transistor 220 is located in the pixel PX2. However, the present invention is not limited thereto. 11 to 13, which are cross-sectional views schematically showing portions of display devices according to still another embodiment of the present invention, the second thin film transistor 220 as well as the first thin film transistor 210, (PX1). That is, in the first thin film transistor 210 and the second thin film transistor 220 belonging to one pixel PX1, the first gate electrode 213 of the first thin film transistor 210 and the second thin film transistor 220 The second gate electrode 223 may be located in different layers. Of course, the pixel PX2 may also include thin film transistors having the same structure as the first thin film transistor 210 and the second thin film transistor 220 belonging to the pixel PX1. The first wiring W1, the second wiring W2, the first additional wiring AW1, the second additional wiring AW2, the first signal line S1 ) And the second signal line S2 can be applied to display devices such as those shown in Figs. 11 to 13. Fig.

14 is a cross-sectional view schematically showing parts of a display device according to another embodiment of the present invention. The display device according to the present embodiment differs from the display device according to the embodiment described above with reference to FIG. 4 in the display area DA in that the first thin film transistor 210 And a second interlayer insulating film 132 covering the first source electrode 215a and the first drain electrode 215b and the second source electrode 225a and the second drain electrode 225b of the second thin film transistor 220. [ Is located on such a second interlayer insulating film 132. [ That is, the first source electrode 215a and the first drain electrode 215b and the second source electrode 225a and the second drain electrode 225b are located in different layers.

The second interlayer insulating film 132 extends to the peripheral area PA and also covers the first signal line S1 and the first bridge wiring BW1. However, the second signal line S2 and the second bridge wiring BW2 are located on the second interlayer insulating film 132. [ The second signal line S2 is in contact with the second additional wiring AW2 through the contact hole passing through the first interlayer insulating film 131 and the second interlayer insulating film 132 and is electrically connected to the second bridge wiring BW2, Contact the second additional wiring AW2 and the second wiring W2 through the contact holes passing through the first interlayer insulating film 131 and the second interlayer insulating film 132. [

In FIG. 14, the first thin film transistor 210 is located in the first pixel PX1 and the second thin film transistor 220 is located in the second pixel PX2. However, the present invention is not limited thereto. The second thin film transistor 220 as well as the first thin film transistor 210 are also connected to the pixel PX1, as shown in FIG. 15, which is a sectional view schematically showing portions of a display device according to another embodiment of the present invention. . That is, in the first thin film transistor 210 and the second thin film transistor 220 belonging to one pixel PX1, the first source electrode 215a and the first drain electrode 215b of the first thin film transistor 210 And the second source electrode 225a and the second drain electrode 225b of the second thin film transistor 220 may be located in different layers. The second thin film transistor 220 may further include a second interlayer insulating film 132 covering the first source electrode 215a and the first drain electrode 215b of the first thin film transistor 210, The source electrode 225a and the second drain electrode 225b may be located on such a second interlayer insulating film 132. [ Of course, the pixel PX2 may also include thin film transistors having the same structure as the first thin film transistor 210 and the second thin film transistor 220 belonging to the pixel PX1.

The second interlayer insulating film 132 extends to the peripheral area PA and also covers the first signal line S1 and the first bridge wiring BW1. However, the second signal line S2 and the second bridge wiring BW2 are located on the second interlayer insulating film 132. [ The second signal line S2 is in contact with the second additional wiring AW2 through the contact hole passing through the first interlayer insulating film 131 and the second interlayer insulating film 132 and is electrically connected to the second bridge wiring BW2, Contact the second additional wiring AW2 and the second wiring W2 through the contact holes passing through the first interlayer insulating film 131 and the second interlayer insulating film 132. [

16, which is a cross-sectional view schematically showing portions of a display device according to another embodiment of the present invention, a first source electrode 215a of the first thin film transistor 210, And the first drain electrode 215b are electrically connected to the pixel electrode 311, the intermediate conductive layer 311a may be electrically connected to either the first source electrode 215a or the first drain electrode 215b, Electrode 311, as shown in FIG. That is, the intermediate conductive layer 311a may be in contact with either the first source electrode 215a or the first drain electrode 215b, and the pixel electrode 311 may be in contact with the intermediate conductive layer 311a. The intermediate conductive layer 311a may include the same material as the second source electrode 225a and the second drain electrode 225b of the second thin film transistor 220 and may be located on the same layer. That is, the intermediate conductive layer 311a may be formed at the same time when the second source electrode 225a and the second drain electrode 225b are formed.

15, the first signal line S1 and the first bridge wiring BW1 are connected to the first source electrode 215a and the first drain electrode 215a of the first thin film transistor 210. In the display device according to the embodiment of the present invention, The second signal line S2 and the second bridge wiring BW2 are formed on the first interlayer insulating film 131 including the same material as the electrode 215b and the second source electrode 225a of the second thin film transistor 220 And the second drain electrode 225b and is located on the second interlayer insulating film 132. However, the present invention is not limited thereto.

17, which is a cross-sectional view schematically showing parts of a display device according to another embodiment of the present invention, a first source electrode 215a and a first drain electrode 215b of a first thin film transistor 210, The second signal line S2 and the second bridge wiring BW2 are connected to each other while the second source electrode 225a and the second drain electrode 225b of the second thin film transistor 220 are located in different layers, It can be positioned in the same layer as the first signal line S1 and the first bridge wiring BW1. That is, the first signal line S1, the first bridge wiring BW1, the second signal line S2 and the second bridge wiring BW2 are connected to the first source electrode 215a of the first thin film transistor 210, 1 drain electrode 215b may be formed simultaneously with the same material.

18, which is a cross-sectional view schematically showing portions of a display device according to another embodiment of the present invention, the second interlayer insulating film 132 is formed in a peripheral region PA So as to cover the second signal line S2 and the second bridge wiring BW2 located on the first interlayer insulating film 131. [ The first signal line S1 and the first bridge wiring BW1 may be located on the second interlayer insulating film 132. [ The first signal line S1 is in contact with the first additional wiring AW1 through the contact hole passing through the first interlayer insulating film 131 and the second interlayer insulating film 132 and the first signal line S1 is electrically connected to the first bridge wiring BW1, The first interlayer insulating film 131 and the second interlayer insulating film 132 are contacted with the first additional interconnection AW1 and the first interconnection W1 through contact holes passing through the first interlayer insulating film 131 and the second interlayer insulating film 132. [

19 is a cross-sectional view schematically showing portions of a display device according to another embodiment of the present invention. The display device according to this embodiment is different from the display device according to the above-described embodiment with reference to Fig. 14 in that it further includes a first additional bridge wiring ABW1 and a second additional bridge wiring ABW2. The first additional bridge wiring ABW1 is located above the first bridge wiring BW1, and both ends are connected to the first bridge wiring BW1. The second additional bridge wiring ABW2 is located above the second bridge wiring BW2, and both ends are connected to the second bridge wiring BW2.

In the manufacturing process, the first source electrode 215a, the first drain electrode 215b, the second source electrode 225a, the second drain electrode 225b, the first signal line S1, the first bridge wiring BW1, The planarization layer 140 covering the second signal line S2 and the second bridge wiring BW2 is formed and the pixel electrodes 311 and 321 are formed in the planarization layer 140 by the first thin film transistor 210 and the second thin film transistor 210, The pixel electrodes 311 and 321 are formed on the planarization layer 140 after the contact holes are formed to connect the thin film transistor 220 to each other. At this time, when forming the contact holes, contact holes exposing the first bridge wiring BW1 and contact holes exposing the second bridge wiring BW2 are formed at the same time. Thereafter, when forming the pixel electrodes 311 and 321, a first additional bridge wiring ABW1 whose both ends are connected to the first bridge wiring BW1 via the contact holes, The second additional bridge wirings ABW2 connected to the bridge wirings BW2 can be simultaneously formed from the same material. In this case, since the first bridge wiring BW1 and the first additional bridge wiring ABW1 are connected in parallel and the second bridge wiring BW2 and the second additional bridge wiring ABW2 are connected in parallel, Considering the first additional bridge wiring BW1 and the first additional bridge wiring ABW1 and considering the second bridge wiring BW2 and the second additional bridge wiring ABW2, the overall resistance can be reduced.

In FIG. 19, the first thin film transistor 210 belongs to the pixel PX1 and the second thin film transistor 220 belongs to the pixel PX2, but the present invention is not limited to this. The second thin film transistor 220 as well as the first thin film transistor 210 are also connected to the pixel PX1, as shown in FIG. 20, which is a sectional view schematically showing portions of a display device according to another embodiment of the present invention. . That is, in the first thin film transistor 210 and the second thin film transistor 220 belonging to one pixel PX1, the first source electrode 215a and the first drain electrode 215b of the first thin film transistor 210 And the second source electrode 225a and the second drain electrode 225b of the second thin film transistor 220 may be located in different layers. In this case, the second thin film transistor 220 further includes a second interlayer insulating film 132 covering the first source electrode 215a and the first drain electrode 215b of the first thin film transistor 210, The source electrode 225a and the second drain electrode 225b may be located on such a second interlayer insulating film 132. [ Of course, the pixel PX2 may also include thin film transistors having the same structure as the first thin film transistor 210 and the second thin film transistor 220 belonging to the pixel PX1.

In such a case as well, the first signal line S1, the first wiring W1, the first additional wiring AW1, the first bridge wiring BW1, the first additional bridge wiring ABW1, The signal line S2, the second wiring W2, the second additional wiring AW2, the second bridge wiring BW2 and the second additional bridge wiring ABW2 may be applied as they are.

20, the first bridge wiring BW1 and the second bridge wiring BW2 include the same material as the first source electrode 215a and the first drain electrode 215b And the first additional bridge wiring ABW1 and the second additional bridge wiring ABW2 are disposed on the same layer and include the same material as the second source electrode 225a and the second drain electrode 225b, As shown in FIG.

While various embodiments have been described above, the present invention is not limited thereto. 1 to 3) having a round shape and a peripheral area PA (see FIG. 1 (A)) outside the display area DA, 1-3) extending in the direction of the first part P1 from the pad area PADA and having a pad area PADA (see FIGS. 1 to 3) A first interconnection having a first discontinuity point and a first interconnection bridge allowing a first interconnection to be electrically continuous at a first discontinuity point are included in the scope of the present invention.

At this time, a second wiring line extending from the pad region PADA toward the first portion P1 and having a second discontinuity point that is physically discontinuous, and a second wiring line L2 electrically connecting the second wiring line at the second discontinuity point, And the second bridge wiring is located farther from the pad area PADA (+ y direction (see Fig. 3)) than the first bridge wiring, and the second bridge wiring is located farther from the edge E1, see Fig. 1).

Although the edge of the display area DA as a whole has a rectangular shape or a square shape and a round shape as a whole, the present invention is not limited thereto. For example, even when a portion other than the first portion P1 of the display area DA has a round shape, it also belongs to the scope of the present invention. For example, the entire edge of the display area DA is circular or elliptical.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art . Therefore, the true scope of the present invention should be determined by the technical idea of the appended claims.

W1: first wiring W2: second wiring
W3: third wiring AW1: first additional wiring
AW2: second additional wiring AW3: third additional wiring
BW1: first bridge wiring BW2: second bridge wiring
BW3: Third bridge wiring ABW1: First additional bridge wiring
ABW2: second additional bridge wiring S1: first signal line
S2: second signal line S3: third signal line
P1: first part P2: second part
PX1, PX1-1, PX1-2, PX2, PX3:
DA: display area PA: peripheral area
PADA: Pad area 100: substrate
110: buffer layer 121: first gate insulating film
122: second gate insulating film 131: first interlayer insulating film
132: second interlayer insulating film 140: planarization layer
150: pixel defining layer 210: first thin film transistor
220: second thin film transistor 310: first display element
320: second display element

Claims (20)

  1. A first portion of the edge having a rounded shape and a peripheral region outside said display region and having a pad region within said peripheral region;
    A first wiring extending in the first part direction such that a first end is located in the pad area and a first end is located in the peripheral area;
    A first additional wiring extending toward the display region such that a first additional end is electrically connected to the first other end and a first additional end is located within the peripheral region; And
    A first signal line, one end of which is electrically connected to the first additional end and extends into the display area;
    And a display device.
  2. The method according to claim 1,
    Further comprising a first bridge wiring connecting the first other end and the first additional end.
  3. 3. The method of claim 2,
    Wherein the first wiring and the first additional wiring include the same material and the first bridge wiring includes the same material as the first signal line and is disposed on the same layer as the first signal line.
  4. The method of claim 3,
    Wherein the first wiring and the first additional wiring are disposed on the same layer.
  5. The method of claim 3,
    And a first additional bridge wiring located above the first bridge wiring and having both ends connected to the first bridge wiring.
  6. The method according to claim 1,
    And a thin film transistor located in the display region and including a gate electrode and a source electrode and a drain electrode located on an interlayer insulating film covering the gate electrode,
    Wherein the first wiring and the first additional wiring include the same material as the gate electrode and are disposed on the same layer as the gate electrode, the first signal line includes the same material as the source electrode and the drain electrode, The source electrode, and the drain electrode.
  7. The method according to claim 6,
    Further comprising a first bridge wiring connecting the first end and the first additional end and including the same material as the first signal line and disposed on the same layer as the first signal line.
  8. 8. The method of claim 7,
    A pixel electrode electrically connected to one of the source electrode and the drain electrode; And
    A first additional bridge wiring having opposite ends connected to the first bridge wiring, the first additional bridge wiring including the same material as the pixel electrode and disposed on the same layer as the pixel electrode;
    And a display device.
  9. The method according to claim 6,
    A pixel electrode electrically connected to one of the source electrode and the drain electrode; And
    A first additional bridge wiring connecting the first other end and the first additional end and including the same material as the pixel electrode and disposed on the same layer as the pixel electrode;
    And a display device.
  10. The method according to claim 1,
    Wherein the first other end is closer to the display area than the first additional end.
  11. The method according to claim 1,
    Wherein the display region includes first and second opposite edges facing each other and a third edge and a fourth edge positioned between the first edge and the second edge facing each other, Connecting said edge with said fourth edge,
    Wherein the pad region is adjacent to the fourth edge of the first to fourth edges.
  12. 12. The method of claim 11,
    A second wiring extending in the first part direction such that a second one end is located in the pad region and a second other end is located in the peripheral region and is disposed closer to the first edge than the first wiring;
    A second additional end electrically connected to the second other end and a second additional end extending toward the display area such that the second additional end is located within the peripheral region, A second additional wiring; And
    A second signal line, one end of which is electrically connected to the second additional end and extends into the display area;
    And a display device.
  13. 13. The method of claim 12,
    Wherein the shortest distance from a virtual straight line including the fourth edge of the second point at which the second other end and the second additional end are connected to each other is a distance from a virtual straight line including a first point at which the first other end and the first additional end are connected to each other Is shorter than the shortest distance from the imaginary straight line of the display device.
  14. 13. The method of claim 12,
    A first bridge wiring connecting the first other end and the first additional end; And
    A second bridge wiring connecting the second other end and the second additional end;
    And a display device.
  15. 15. The method of claim 14,
    A first thin film transistor located within the display region and including a first gate electrode, a first source electrode, and a first drain electrode; And
    A second thin film transistor located within the display region, the second thin film transistor including a second gate electrode, a second source electrode, and a second drain electrode;
    Respectively,
    Wherein the first gate electrode and the second gate electrode are located in different layers, and the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are formed on the first gate electrode and the second gate electrode, An interlayer insulating film covering the gate electrode,
    Wherein the first wiring and the first additional wiring include the same material as the first gate electrode and are disposed on the same layer as the first gate electrode, And the second gate electrode is disposed on the same layer as the second gate electrode.
  16. 15. The method of claim 14,
    A first thin film transistor located within the display region and including a first gate electrode, a first source electrode, and a first drain electrode; And
    A second thin film transistor located within the display region, the second thin film transistor including a second gate electrode, a second source electrode, and a second drain electrode;
    Respectively,
    Wherein the first gate electrode and the second gate electrode are located in different layers, and the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are formed on the first gate electrode and the second gate electrode, An interlayer insulating film covering the gate electrode,
    Wherein the first wiring and the second additional wiring include the same material as the first gate electrode and are disposed on the same layer as the first gate electrode, And the second gate electrode is disposed on the same layer as the second gate electrode.
  17. 15. The method of claim 14,
    A first thin film transistor located within the display region and including a first gate electrode, a first source electrode, and a first drain electrode; And
    A second thin film transistor located within the display region, the second thin film transistor including a second gate electrode, a second source electrode, and a second drain electrode;
    Respectively,
    Wherein the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are located in different layers,
    Wherein the first signal line and the first bridge wiring comprise the same material as the first source electrode and the first drain electrode and are disposed on the same layer as the first source electrode and the first drain electrode, Wherein the signal line and the second bridge wiring comprise the same material as the second source electrode and the second drain electrode and are disposed on the same layer as the second source electrode and the second drain electrode.
  18. 15. The method of claim 14,
    A first thin film transistor located within the display region and including a first gate electrode, a first source electrode, and a first drain electrode;
    A second thin film transistor located within the display region, the second thin film transistor including a second gate electrode, a second source electrode, and a second drain electrode;
    A first additional bridge wiring located above the first bridge wiring and having both ends connected to the first bridge wiring; And
    A second additional bridge wiring located above the second bridge wiring and having both ends connected to the second bridge wiring;
    Respectively,
    Wherein the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are located in different layers,
    Wherein the first bridge wiring and the second bridge wiring comprise the same material as the first source electrode and the first drain electrode and are disposed on the same layer as the first source electrode and the first drain electrode,
    Wherein the first additional bridge wiring and the second additional bridge wiring comprise the same material as the second source electrode and the second drain electrode and are disposed on the same layer as the second source electrode and the second drain electrode, Display device.
  19. A first portion of the edge having a rounded shape and a peripheral region outside said display region and having a pad region within said peripheral region;
    A first wiring extending from the pad region in the first partial direction and having a first discontinuity point that is physically discontinuous; And
    A first bridge wiring for allowing the first wiring to be electrically continuous at the first discontinuity point;
    And a display device.
  20. 20. The method of claim 19,
    A second wiring extending in the first portion direction from the pad region and having a second discontinuity point that is physically discontinuous; And
    A second bridge wiring for electrically continuing the second wiring at the second discontinuity point;
    Wherein the second bridge wiring is located farther from the pad area than the first bridge wiring and the second bridge wiring is closer to the edge of the substrate than the first bridge wiring.
KR1020170076813A 2017-06-16 2017-06-16 Display apparatus KR20180137639A (en)

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US15/880,089 US10163941B1 (en) 2017-06-16 2018-01-25 Display apparatus
EP18154366.1A EP3416194A1 (en) 2017-06-16 2018-01-31 Display apparatus
CN201810178146.3A CN109148510A (en) 2017-06-16 2018-03-05 Display device
US16/211,479 US20190109156A1 (en) 2017-06-16 2018-12-06 Display apparatus

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TW200531284A (en) 2003-07-29 2005-09-16 Samsung Electronics Co Ltd Thin film array panel and manufacturing method thereof
KR101316791B1 (en) 2007-01-05 2013-10-11 삼성디스플레이 주식회사 Gate driving circuit and liquid crystal display having the same, manufacturing method for thin film transistor array panel
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KR101452288B1 (en) 2012-11-19 2014-10-21 엘지디스플레이 주식회사 Display device
KR20140099139A (en) 2013-02-01 2014-08-11 엘지디스플레이 주식회사 Flexible display substrate, flexible organic light emitting display device and method for manufacturing the same
KR102048437B1 (en) 2013-08-30 2019-11-25 엘지디스플레이 주식회사 Thin film transistor substrate and Display Device using the same
KR20150045556A (en) * 2013-10-18 2015-04-29 삼성디스플레이 주식회사 Display apparatus
KR20150080825A (en) * 2014-01-02 2015-07-10 삼성디스플레이 주식회사 Display panel, display apparatus having the same and method of manufacturing the same
US9287329B1 (en) 2014-12-30 2016-03-15 Lg Display Co., Ltd. Flexible display device with chamfered polarization layer
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EP3416194A1 (en) 2018-12-19

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