KR20180040474A - Memory module reporting fail information of chip unit and Operating method of Memory module and Memory controller - Google Patents

Abstract

Disclosed are a memory module reporting fail information in chip units and an operating method of the memory module and a memory controller. The memory module according to an aspect of the technical idea of the present disclosure comprises: first to M^th memory chips mounted on a module board and respectively storing data (where, M is an integer of 2 or more); and an (M+1)^th memory chip mounted on the module board and storing a parity code for restoring data of a memory chip, in which chip-unit failure has occurred, among the first to M^th memory chips. Fail bits are generated by an on-chip error detection operation from the first to (M+1)^th memory chips, and fail information according to a result of operation of the fail bits from the first to (M+1)^th memory chips is output. The present invention is able to reduce manufacturing costs and improve capability of detecting and correcting errors.

Description

[0001] The present invention relates to a memory module, a memory module, and a memory controller for reporting fail information on a chip basis,

TECHNICAL FIELD [0002] The present invention relates to a memory module, and more particularly, to a memory module, a memory module, and a memory controller that report fail information on a chip basis.

Semiconductor memory devices, which are widely used in high performance electronic systems, are increasing in capacity and speed. As an example of a semiconductor memory device, a DRAM is a volatile memory, and is a memory that determines data by a charge stored in a capacitor.

As the operation of the semiconductor memory device increases in speed, the probability of error occurrence of data increases. As an example of correcting an error, there is proposed a method of recovering an error on a chip-by-chip basis. The memory controller generates a parity code (for example, ECC parity) corresponding to data of a predetermined unit of bits, (For example, a memory package, a memory module, etc.) including the memory chips, and the data of the fail chip can be recovered through the recovery algorithm using the read data and the parity code. However, the number of memory chips to be separately provided for storing the parity code can be increased, which increases the implementation cost of the semiconductor memory device.

The technical idea of the present disclosure provides a method of operating a memory module, a memory module, and a memory controller that can reduce manufacturing cost and improve error detection and correction capability.

In order to achieve the above object, a memory module according to one aspect of the technical idea of the present disclosure includes first to Mth memory chips, each of which is mounted on a module board and stores data, wherein M is an integer of 2 or more And a (M + 1) th memory chip mounted on the module board and storing a parity code for recovering data of a memory chip in which the chip unit fail is generated among the first to Mth memory chips, Fail bits are generated from the first to (M + 1) th memory chips through an intra-chip error detection operation, and fail information according to a result of calculating fail bits from the first to (M + And outputs the output signal.

Further, the memory module according to another aspect of the technical idea of the present disclosure includes an in-DRAM error correction circuit (In-DRAM ECC), and outputs a fail bit indicating whether or not the chip unit fails through internal error detection And a buffer chip for receiving the fail bits from the M DRAM chips and generating and outputting fail information through a calculation operation on the fail bits, .

According to an aspect of the present invention, there is provided a method of operating a memory controller, the method comprising: receiving data and corresponding parity codes from a plurality of memory chips; Requesting a fail bit indicating a position of a failed memory chip among the plurality of memory chips, and using the fail bit and the parity code, And recovering the data of the memory chip.

According to an aspect of the present invention, there is provided a method of operating a memory module, comprising: reading data stored in a plurality of memory chips and a parity code for recovering failures of the memory chips; Generating a fail bit indicating whether or not a chip unit fails, through the chip internal error detecting operation, and outputting the fail information generated through the operation on the generated fail bit.

According to the operation method of the memory module, the memory module and the memory controller according to the technical idea of the present disclosure, the data of the failed memory chip can be recovered without generating the detection code indicating the position of the fail chip, There is an effect that the unit price can be reduced.

According to the operation method of the memory module, the memory module and the memory controller according to the technical idea of the present disclosure, it is possible to recover data of the fail chip without storing a separate detection code in a specific memory chip, The bit error can be corrected, so that the error correction capability of the semiconductor memory device can be improved.

1 is a diagram of a memory system in accordance with an exemplary embodiment of the present invention.
2 is a diagram of a memory system according to another exemplary embodiment of the present invention.
3 is a diagram of a memory system in accordance with another exemplary embodiment of the present invention.
4 is a flowchart showing an operation method of a semiconductor memory device according to an exemplary embodiment of the present invention.
5 is a flowchart showing an operation method of a semiconductor memory device according to another exemplary embodiment of the present invention.
Figure 6 is a block diagram illustrating a specific implementation of a memory system in accordance with an exemplary embodiment of the present invention.
Figures 7 and 8 are block diagrams illustrating specific implementations of a memory system in accordance with another illustrative embodiment of the present invention.
9 is a block diagram illustrating an embodiment of the RCD shown in FIG.
10 is a flowchart showing an example of an error correction process in the memory controller.
11 is a block diagram illustrating an embodiment of a memory module according to another exemplary embodiment of the present invention.
12 is a block diagram illustrating an embodiment of a memory module according to another exemplary embodiment of the present invention.
13 is a block diagram illustrating an embodiment of a memory module according to another exemplary embodiment of the present invention.
14 is a block diagram illustrating an embodiment of a memory module according to another exemplary embodiment of the present invention.
15 is a block diagram illustrating an embodiment of a memory module according to another exemplary embodiment of the present invention.
16 is a flowchart showing an operation method of the memory controller according to the modified embodiment of the present invention.
17 is a block diagram illustrating a data processing system in accordance with one embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram of a memory system in accordance with an exemplary embodiment of the present invention.

1, a memory system 10 may include a memory controller 11 and a semiconductor memory device 12, and the semiconductor memory device 12 may include a plurality of memory chips 12_1 to 12_M. have. As an example, the semiconductor memory device 12 may include a plurality of dynamic random access memory chips (DRAM Chips) as volatile memory chips. The DRAM chip may correspond to a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), an LPDDR (Low Power Double Data Rate) SDRAM, a GDDR (Graphics Double Data Rate) SDRAM and a RDRAM (Rambus Dynamic Random Access Memory). For example, the semiconductor memory device 12 may include a flash memory, a magnetic RAM (MRAM), a ferroelectric RAM (FeRAM), a phase change RAM (PRAM) Or a nonvolatile memory such as ReRAM (Resistive RAM). Each of the memory chips 12_1 to 12_M may correspond to a DRAM chip according to various standards such as DDR, DDR2, DDR3, DDR4 and DDR5.

In the following description, each of the memory chips 12_1 to 12_M will be referred to as a DRAM chip. However, the memory chips 12_1 to 12_M may be implemented by chips of various other types (for example, nonvolatile memory).

According to an embodiment, the semiconductor memory device 12 may correspond to a semiconductor package having a stacked structure of a plurality of DRAM chips 12_1 to 12_M. Alternatively, according to one embodiment, the semiconductor memory device 12 may correspond to a memory module in which a plurality of DRAM chips 12_1 to 12_M are mounted on a module board. Although one semiconductor memory device 12 is shown in FIG. 1, the memory controller 11 may communicate with a plurality of semiconductor memory devices to write or read data (DATA). Although the semiconductor memory device 12 is described as being a memory module in the following embodiments, the semiconductor memory device 12 may include various types of memory devices including a plurality of DRAM chips (for example, A memory package, or the like).

The memory controller 11 provides various signals to the semiconductor memory device 12 to control the memory operation. For example, the memory controller 11 can supply data (DATA) and parity information (Info_PAR) to the semiconductor memory device 12 and can read data (DATA) and parity information (Info_PAR) from the semiconductor memory device 12 have. The memory controller 11 may include an ECC engine 11_1 and the ECC engine 11_1 corrects an error included in the data DATA through an error correction operation using data DATA and parity information Info_PAR can do. According to one embodiment, the memory controller 11 may be referred to as a host, and the host may include a central processing unit (CPU) that performs overall processing operations and a control module that performs access to the semiconductor memory device 12 . ≪ / RTI > Alternatively, the host may correspond to an application processor.

The parity information (Info_PAR) may include various information related to error correction and / or recovery of a fail chip. According to one embodiment, a parity code having a parity value for error correction and / or recovery of a fail chip may be included in the parity information (Info_PAR). Further, a detection code for detecting a position where an error has occurred or a position of a fail chip may be further included in the parity information (Info_PAR) for error correction and / or recovery of a fail chip.

According to one embodiment, an In DRAM ECC (not shown) may be employed in each of the DRAM chips 12_1 to 12_M, so that each of the DRAM chips 12_1 to 12_M performs chip level error detection / And it is possible to correct errors in the DRAM chip internal data or to generate information indicating that error correction is impossible (for example, a fail bit indicating whether or not each chip fails) in accordance with the error detection result. For example, assuming that the semiconductor memory device 12 includes M DRAM chips 12_1 to 12_M, each of the M DRAM chips 12_1 to 12_M generates a 1-bit fail bit, The M bits of fail bits indicating the fail state of the M DRAM chips 12_1 to 12_M can be generated in the memory 12.

According to one embodiment, the semiconductor memory device 12 may generate the fail information (Info_F) using the M bits of fail bits and output the generated fail information (Info_F) to the memory controller (11) . The fail information (Info_F) may be generated according to various methods. As an example, fail bits corresponding to M bits are generated from M DRAM chips 12_1 to 12_M in the semiconductor memory device 12, and fail information (Info_F) is generated based on the result of calculation of the fail bits . For example, the fail information (Info_F) is generated by performing the XOR operation on the M bits of the fail bits, thereby generating the fail information (Info_F) when at least one of the DRAM chips (12_1 to 12_M) May have a first logic state (e.g., logic high). On the other hand, the fail information Info_F may have a second logic state (e.g., logic low) when failures have not occurred in the M DRAM chips 12_1 to 12_M.

The semiconductor memory device 12 provides the fail information Info_F to the memory controller 11 or the host and the memory controller 11 determines which DRAM chip is in the semiconductor memory device 12 based on the fail information Info_F It is possible to judge whether or not it is a failure. The ECC engine 11_1 of the memory controller 11 can perform the error correction operation using the parity information Info_PAR and / or the data recovery operation of the fail chip based on the fail information Info_F. The error detection / correction operation in the memory controller 11 may correspond to a module level or system level error detection / correction operation.

For example, when the fail information (Info_F) indicates that there is no failed DRAM chip, the ECC engine 11_1 corrects an error present in the data (DATA) by performing a general error correcting operation using the parity information (Info_PAR) can do. As an example, the parity information (Info_PAR) may include code information for detecting or correcting a predetermined number of bits (for example, one bit) of error, together with code for recovering data of the fail chip, If there is no DRAM chip, a data recovery operation may not be performed. Further, when the fail information (Info_F) indicates that at least one failed DRAM chip exists, the ECC engine 11_1 stores the data of the failed DRAM chip through the data (DATA) recovery operation using the parity information (Info_PAR) It can be recovered. Accordingly, the memory controller 11 is informed of the fail status of the DRAM chips 12_1 to 12_M of the semiconductor memory device 12, and can selectively perform the data recovery operation of the fail chip according to the reporting result.

In embodiments of the present invention, the data recovery operation for the fail chip may be performed through various error correction algorithms. For example, the memory controller 11 may recover the data of the fail chip through a data recovery scheme based on various schemes such as a Reed-Solomon Error Correction Code.

The memory controller 11 can generate parity information (Info_PAR) through internal coding (e.g., ECC coding) on a predetermined unit of data (e.g., 32 or 64 bits of data). According to an embodiment of the present invention, the parity information (Info_PAR) may include only the parity code used for the data recovery operation without including the detection code for detecting the position of the fail chip. Accordingly, the memory controller 11 can generate only a parity code through an encoding process for a predetermined unit of data. If a 4-bit detection code is generated corresponding to 64-bit data, the 4-bit detection code need not be generated or stored according to the embodiment of the present invention. Therefore, The resource (for example, the storage area of the DRAM chip or the DRAM chip) can be reduced.

Alternatively, according to a variant embodiment, the memory controller 11 may generate both a parity code and a detection code through encoding for the predetermined unit of data. On the other hand, by storing only the parity code in the semiconductor memory device 12, the memory controller 11 can reduce resources for storing the detection code in the semiconductor memory device 12. [

In addition, according to the deformable embodiment, the memory controller 11 can generate parity code for data recovery of a fail chip and code information for additional error correction through encoding of the predetermined unit of data. The code information may be stored in a resource for storing the detection code in the semiconductor memory device 12. [ That is, according to this variant embodiment, code information for additional error correction (e.g., random error and / or multi-bit error correction) can be provided to semiconductor memory device 12 ), Whereby the data reliability of the semiconductor memory device 12 can be improved.

According to an exemplary embodiment of the present invention, the parity code may further include code for correcting at least one general error, in addition to the code for data recovery of the fail chip. Further, according to an embodiment of the present invention, additional code information stored in a resource for storing a detection code will be described as being configured to be distinguished from the parity code for convenience of explanation. However, It may be defined as being included in the code.

Further, according to the deformable embodiment, since the memory controller 11 can receive an error status from the semiconductor memory device 12, the memory controller 11 generates only the detection code having the smallest size through encoding of the predetermined unit of data . As an example, an encoding scheme capable of minimizing the size of the detected code among various types of encodings can be applied to the memory controller 11, and a detection code having the minimized size is stored in the semiconductor memory device 12 . For example, a detection code smaller than the existing 4-bit detection code (e.g., 2 bits) is generated and stored in the semiconductor memory device 12, and the resources that can be further utilized thereby include the above- (E.g., index or tag information when the semiconductor memory device is used as a cache, and the like) can be stored.

According to the embodiment shown in FIG. 1, since the detection code for determining the position of the fail chip does not need to be stored, the number of DRAM chips provided in the semiconductor memory device 12 can be reduced. Further, since the resource for storing the existing detection code can be utilized as a resource for storing additional error detection and correction (e.g., random error or correction of multi-bit error), data reliability of the memory system 10 can be improved .

2 is a diagram of a memory system according to another exemplary embodiment of the present invention. In the description of the configurations shown in FIG. 2, the same configurations as those shown in FIG. 1 are the same or similar in their operation, and a detailed description thereof will be omitted.

Referring to FIG. 2, the memory system 100 may include a memory controller 110 and a semiconductor memory device 120, and the semiconductor memory device 120 may include DRAM chips 121_1 to 121_M. In addition, the memory controller 110 may include an ECC engine 111_1.

As in the above embodiment, each of the DRAM chips 121_1 to 121_M includes an In DRAM ECC (not shown), and a fail bit indicating that error correction is impossible through a chip level error detection operation on the read data Lt; / RTI > That is, M bits of fail bits (Fail [1: M]) can be generated from the DRAM chips 121_1 to 121_M of the semiconductor memory device 120, and M bits of fail bits [Fail [1: M] Fail information (Info_F) can be generated and output to the memory controller (110) through the used operation operation.

According to one embodiment, a failure bit (Fail [1: M]) of M bits is generated in the semiconductor memory device 120 as a 1-bit fail bit is generated from each of the DRAM chips 121_1 to 121_M The embodiment of the present invention need not be limited to this. For example, two or more fail bits may be generated from each of the DRAM chips 121_1 to 121_M, or a fail bit may be generated only in chips of some of the DRAM chips 121_1 to 121_M (for example, DRAM chips storing data) The number of bits of the fail bit (Fail [1: M]) generated in the semiconductor memory device 120 may be varied.

Also, according to an embodiment, the fail information (Info_F) generated through the arithmetic operation using the M bits of the fail bit (Fail [1: M]) may correspond to one bit. Alternatively, if the operation using the M bits of the fail bit (Fail [1: M]) is generated through various other calculation processes, the fail information Info_F may include a different number of bits.

2, the semiconductor memory device 120 may output fail information (Info_F) to the memory controller 110 together with data (DATA) and parity information (Info_PAR). If a chip-level failure is not generated in the DRAM chips 121_1 to 121_M, it is assumed that one or more general errors can be corrected through the parity information (Info_PAR), the memory controller 110 stores the received parity information Info_PAR) to correct one or more generic errors present in the data (DATA). On the other hand, if fail information (Info_F) has a first logic level, the memory controller 110 can determine that at least one DRAM chip is a failure, and by providing a separate command to the semiconductor memory device 120, The fail bit (Fail [1: M]) stored in the device 120 can be read. The memory controller 110 can determine the position of the DRAM chip in which the fail of the chip unit is generated through the fail bit (Fail [1: M]) and the fail bit (Fail [1: M]) and the parity information ) Can be used to recover the data (DATA) of a failed DRAM chip.

3 is a diagram of a memory system in accordance with another exemplary embodiment of the present invention. In describing the configurations shown in FIG. 3, the same configurations as those shown in FIG. 1 and FIG. 2 are the same or similar in their operation, so a detailed description thereof will be omitted.

3, the memory system 200 may include a memory controller 210 and a semiconductor memory device 220, and the semiconductor memory device 220 may include M DRAM chips 221_1 to 221_M. have. In addition, the memory controller 210 may include an ECC engine 211_1. In addition, the semiconductor memory device 220 transmits the fail bit (Fail [1: M]) generated from the M DRAM chips 221_1 to 221_M to the memory controller 210 without an arithmetic operation for generating separate fail information Can be output.

Data (DATA) may be stored in M-1 DRAM chips among the M DRAM chips 221_1 to 221_M, and parity information (Info_PAR) may be stored in the remaining one DRAM chip. The semiconductor memory device 220 includes M ports for outputting data (DATA) or parity information (Info_PAR) read from each of the M DRAM chips 221_1 to 221_M to the memory controller 210, Each port may include a plurality of pins. If each of the DRAM chips 221_1 to 221_M outputs data (DATA) or parity information (Info_PAR) on a 4-bit basis, each port may include four pins.

As described above, the DRAM chip in which the detection code is stored in the semiconductor memory device 220 may be removed, so that the semiconductor memory device 220 further includes a port corresponding to the removed DRAM chip . That is, the semiconductor memory device 220 may include (M + 1) ports corresponding to the M DRAM chips 221_1 to 221_M. According to one embodiment, the fail bit (Fail [1: M]) may be provided to the memory controller 210 via an additional port corresponding to the removed DRAM chip. The memory controller 210 determines the position of the failed DRAM chip based on the fail bit (Fail [1: M]) and uses the fail bit (Fail [1: M]) and the parity information (Info_PAR) The data (DATA) of the failed DRAM chip can be recovered.

4 is a flowchart showing an operation method of a semiconductor memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the semiconductor memory device includes a plurality of DRAM chips, and an In DRAM ECC is employed in each of the plurality of DRAM chips, so that fail detection using the in-chip ECC can be performed (S11). As an example, each of the DRAM chips may determine that a corresponding DRAM chip is failed when an uncorrectable error occurs, and may generate a fail bit according to the failure. In addition, each DRAM chip can generate a fail bit corresponding to one bit as a result of fail detection, and a fail bit corresponding to M bits is generated in the semiconductor memory device as the semiconductor memory device includes M DRAM chips .

The semiconductor memory device performs calculation using the fail detection result and outputs fail information according to the calculation result to the memory controller (S12). For example, 1-bit fail information can be generated by performing an XOR operation on M-bit fail bits generated from M DRAM chips. If the fail information corresponds to the first logic state, at least one DRAM chip among the M DRAM chips is failed, and if the fail information corresponds to the second logic state, failures have not occurred in the M DRAM chips. Lt; / RTI >

The memory controller may selectively perform a recovery operation for recovering data of the fail chip based on the logic state of the fail information. When the fail information corresponds to the first logic state, the semiconductor memory device receives the fail bit from the memory controller (S13). A fail bit including the previously generated M bits may be temporarily stored in a predetermined storage circuit (e.g., a register) in the semiconductor memory device, and the semiconductor memory device may store the fail bit stored in the storage circuit in response to the request from the memory controller M-bit fail bits can be output to the memory controller (S14).

5 is a flowchart showing an operation method of a semiconductor memory device according to another exemplary embodiment of the present invention. In the embodiment of FIG. 5, the semiconductor memory device includes M DRAM chips, wherein data or parity information from each DRAM chip is output through one port, and the semiconductor memory device corresponds to M DRAM chips M + 1) ports. Also, it is assumed that parity information does not include a detection code according to an embodiment of the present invention.

Referring to FIG. 5, a semiconductor memory device may store a parity code used to recover data of a fail chip together with data. In one example, data is stored in (M-1) DRAM chips, The chip may store a parity code. In response to the read request from the memory controller, data and parity codes can be read from the M DRAM chips of the semiconductor memory device (S21).

Also, in the process of reading the data and the parity code, a fail may be detected depending on whether or not an uncorrectable error has occurred for each DRAM chip using the In DRAM ECC included in each of the M DRAM chips (S22). In addition, a 1-bit fail bit may be generated in each DRAM chip according to a result of detecting the occurrence of a fail, so that a fail bit corresponding to M bits can be generated in the semiconductor memory device (S23).

The data, the parity code and the generated fail bit may be output through (M + 1) ports. In one example, the data, the parity code and the fail bit are outputted in parallel through the (M + 1) . For example, data and parity codes from M DRAM chips provided in the semiconductor memory device may be output through the corresponding M ports (S24). On the other hand, the semiconductor memory device is provided with an additional port that does not correspond to the M DRAM chips, and the fail bit may be output through the additional one of the (M + 1) ports (S25). For example, each of the (M + 1) ports may include the same number of pins, and when one DRAM chip for storing a detection code according to the embodiment of the present invention is removed from the semiconductor memory device, The additional port may be a port corresponding to the DRAM chip removed from the semiconductor memory device.

Figure 6 is a block diagram illustrating a specific implementation of a memory system in accordance with an exemplary embodiment of the present invention.

6, the memory system 300 may include a memory controller 310 and a semiconductor memory device, wherein the semiconductor memory device includes M DRAM chips 321_1 to 321_M mounted on a module board And a memory module 320 coupled to the memory module. In addition, the memory controller 310 may include an ECC engine 311_1. The memory module 320 further includes a register clock driver 322 mounted on the module board and receiving a command and an address from the memory controller 310 and delivering the command and address to the M DRAM chips 321_1 to 321_M can do. According to one embodiment, the RCD 322 may be implemented as a separate semiconductor chip and mounted on a module board. In addition, the semiconductor chip in which the RCD is disposed may be referred to as a buffer chip in that it temporarily stores a command / address and / or a fail bit (Fail 1 to Fail M).

The memory module 320 may be implemented with various types of modules. As an example, the memory module 320 may correspond to a dual in-line memory module (DIMM) that is mainly used in a server. In addition, the memory module 320 may correspond to various kinds of DIMMs, and various types of DIMMs such as an FB-DIMM and an LR-DIMM may be applied to the memory module 320. Alternatively, the memory module 320 may correspond to a non-volatile DIMM (NVDIMM) equipped with a nonvolatile memory (e.g., flash memory, not shown) to compensate for the problem of volatile memory in which data is lost when the power is turned off have. However, embodiments of the present invention need not be limited thereto, and may be implemented in a single in-line memory module (SIMM), a small-outline DIMM (SO-DIMM), a unbuffered DIMM (UDIMM), a rank- Embodiments of the present invention may be applied to various memory modules such as a DIMM and a micro-DIMM.

As shown in FIG. 6, the memory controller 310 may generate data (DATA) and parity information and provide it to the memory module 320. In this embodiment, as the detection code is not stored in the memory module 320, only the parity code (Parity) can be selectively provided to the memory module 320 as parity information. The memory controller 310 may include M input / output ports (not shown) corresponding to the M DRAM chips 321_1 to 321_M. Data (DATA) and parity code (Parity) are stored in M DRAM chips 321_1 to 321_M and parity codes are stored in (M-1) DRAM chips 321_1 to 321_ M-1) of the failure of the chip unit.

Each of the M DRAM chips 321_1 to 321_M includes an In DRAM ECC (ECC), and the In DRAM ECC generates an uncorrectable error in data (DATA) or parity code (Parity) read from each corresponding DRAM chip The fail bit can be generated. As an example, the fail bits (Fail 1 to Fail M) having M bits from the M DRAM chips 321_1 to 321_M may be generated and provided to the RCD 322 through the wirings on the module board.

RCD 322 can generate fail information (Info_F) by performing arithmetic processing on the received fail bits (Fail 1 to Fail M). According to one embodiment, the fail information Info_F may be provided to the memory controller 310 via a separate terminal 323 corresponding to a report pin formed on the module board. Also, as an example, the separate terminal may include one pin for outputting one bit, and the RCD 322 may generate 1-bit fail information (Info_F And may provide it to the memory controller 310 through a separate terminal 323. [ According to one embodiment, when the memory module 320 corresponds to an NVDIMM, an error report pin defined in relation to the operation of the nonvolatile memory in the memory module of the NVDIMM type is used as the fail information (Info_F) according to the embodiment of the present invention. And may be used as the separate terminal 323 for outputting.

Meanwhile, as described above, the memory controller 310 may receive the fail information (Info_F) and perform an error correcting operation and / or a data restoring operation based thereon. As an example, it can be determined whether a chip unit failure has occurred according to the logic state of the fail information (Info_F). If no chip unit fail has occurred, the ECC engine 311_1 generates a general error A correction operation can be performed. On the other hand, when a chip unit failure is generated, the ECC engine 311_1 can perform a data recovery operation based on a system level error correction.

Figures 7 and 8 are block diagrams illustrating specific implementations of a memory system in accordance with another illustrative embodiment of the present invention.

7, the memory system 400 may include a memory controller 410 and a memory module 420, and M DRAM chips 421_1 to 421_M may be mounted on the module board of the memory module 420 . In addition, the memory controller 410 may include an ECC engine 411 and a command generator 412. In addition, the memory module 420 may further include an RCD 422, and the RCD 422 may include a register 422_1.

The RCD 422 receives the fail bits Fail 1 to Fail M from the M DRAM chips 421_1 to 421_M and the RCD 422 receives the fail bits Fail 1 to Fail M, The fail information Info_F may be provided to the memory controller 410 through an additional terminal 423 corresponding to a report pin formed on the module board.

The memory controller 410 may perform an error correction operation based on the received fail information Info_F and if it is determined that the fail chip does not exist as the fail information Info_F corresponds to the second logic state, The ECC engine 411 can perform a general error correction operation using a parity code (Parity). On the other hand, if it is determined that there is at least one fail chip as the fail information (Info_F) corresponds to the first logic state, the command generator 412 generates a register access for accessing the register 422_1 in the RCD 422 Command CMD_Reg to the memory module 420. [ Also, the fail bit (Fail 1 to Fail M) read from the register 422 _ 1 may be provided to the memory controller 410.

The memory module 420 may include M ports corresponding to the M DRAM chips 421_1 to 421_M and may further include a port 424 for transmitting and receiving signals between the RCD 422 and the memory controller 410 . The port 424 may include a plurality of pins and the aforementioned register access command CMD_Reg may be provided to the RCD 422 via port 424 and may also include a fail bit from the RCD 422, To Fail M may be provided to the memory controller 410 via the port 424.

The ECC engine 411 can determine the position of the failed chip based on the received fail bits (Fail 1 to Fail M) and can determine the position of the failed chip by using the fail bits (Fail 1 to Fail M) and the parity code The data (DATA) of the fail chip can be recovered through the recovery operation based on the system level error correction.

8 shows an example in which the path through which the fail bit (Fail [1: M]) is transmitted is modified in the above-described embodiment.

Referring to FIG. 8, an example in which a conventional DRAM chip storing a detection code for chip-level data recovery is removed from the memory module is shown. That is, a DRAM chip (for example, a detection code chip) in which a detection code indicating the position of a failing chip is stored is removed from the module board, and one port 425 corresponding to the DRAM chip storing the detection code And can be used as a port for transmitting one fail bit (Fail [1: M]). Accordingly, wirings for electrical connection between the RCD 422 and a plurality of pins included in the port 425 may be formed on the module board.

According to the embodiment of FIG. 8, the DRAM chip storing the detection code for recovering the data of the fail chip in the past can be removed, so that the manufacturing cost of the memory module can be reduced. In addition, since a separate port for providing a fail bit (Fail [1: M]) including a plurality of bits to the memory controller does not need to be formed on the module board, the number of ports formed on the module board is reduced It will be possible.

9 is a block diagram illustrating an embodiment of the RCD shown in FIG.

7 and 9, the RCD 422 may include a register 422_1, a fail information generator 422_2, and a command / address buffer 422_3. The command / address buffer 422_3 may receive and store the command CMD and address ADD provided from the memory controller 410 and store the stored command CMD and address ADD in the M DRAM chips 421_1 to 421_1, 421_M).

Fail bits (Fail 1 to Fail M) generated from the M DRAM chips 421_1 to 421_M may be provided to the register 422_1 and the fail information generator 422_2. Fail information generator 422_2 generates fail information (Info_F) through arithmetic operation through XOR or other various methods. The register 422_1 also receives an M-bit fail bit (Fail [1: M]) stored therein in response to a result of decoding the register access command CMD_Reg or the register access command CMD_Reg from the memory controller 410, Can be output.

10 is a flowchart showing an example of an error correction process in the memory controller.

Referring to FIG. 10, the memory controller may generate a parity code corresponding to a predetermined unit of data and write the parity code to a memory module including a plurality of DRAM chips. A parity code may be generated corresponding to a predetermined number of bits of data. For example, a parity code of 4 bits may be generated corresponding to 32 bits or 64 bits of data.

Further, the memory controller provides a command to the memory module to read the data and the corresponding parity code, and the memory controller can receive the read data and the parity code (S31). Also, according to the above-described embodiments, a fail bit is generated based on a chip level error detection result in each of the DRAM chips in the memory module, and fail information is generated through a calculation operation using the fail bit, The fail information can be received (S32).

The memory controller includes an ECC engine for performing system level error correction, and can selectively perform a recovery operation for recovering a failure of a chip unit according to the received fail information. For example, if it is determined that at least one DRAM chip is failed according to the fail information, the failing chip data is recovered using the received parity code (S33).

It is determined whether the data has been successfully recovered by the data recovery operation (S34). If the data is normally recovered, the recovered data can be provided to the host (S35). On the other hand, if the recovery of the data fails, the memory controller may generate a register access command to read the fail bit stored in the memory module and output it to the memory module (S36).

According to one embodiment, the memory controller may receive an M-bit fail bit corresponding to M memory chips (S37), and perform a data recovery operation using the received fail bit and parity code (S38). The data recovery operation corresponds to a recovery operation in a state where the position of the DRAM chip in which the fail is generated is determined based on the fail bit, thereby increasing the probability of recovery of the data of the DRAM chip in which the fail occurs. If the data of the failed DRAM chip is normally recovered according to the above procedure, the recovered data can be provided to the host (S35).

11 is a block diagram illustrating an embodiment of a memory module according to another exemplary embodiment of the present invention.

In the example of FIG. 11, parity information is generated corresponding to 64-bit data (DATA) as defined in the DDR4 specification. Also, according to one embodiment, the parity information stored in the memory module 500A may include only a 4-bit parity code except for the detection code. The first to seventeenth DRAM chips 510_1A to 510_17A may be mounted on the module board of the memory module 500A and each of the first to seventeenth DRAM chips 510_1A to 510_17A may include four bits X4 The first to the sixteenth DRAM chips 510_1A to 510_16A store the data DATA and the seventeenth DRAM chip 510_17A outputs the parity code Parity, Can be stored.

According to the above-described embodiments, since the detection code for indicating the position of the DRAM chip in which the failure occurs in the chip unit is not generated in the memory controller or is not stored in the memory module 500A, The DRAM chip for storing the detection code can be removed. The 64-bit data (DATA) and the corresponding 4-bit parity code are read from the first to seventeenth DRAM chips 510_1A to 510_17A, and the first to seventeenth DRAM chips (Fail [1:17]) of the memory cells 510_1A to 510_17A may be provided to the memory controller (not shown). Although not shown in FIG. 11, the fail information generated by computing the fail bit (Fail [1: 17]) before the fail bit (Fail [1:17]) is provided may be first provided to the memory controller.

The port 530A shown in Fig. 11 may be a port corresponding to a DRAM chip for storing a detection code removed from the above-described module board (or not mounted on the module board), and the port 530A may be a port (DATA) or a parity code (Parity). As an example, the fail bit (Fail [1: 17]) including seventeen bits may be provided to the memory controller through the port 530A sequentially by four bits.

12 is a block diagram illustrating an embodiment of a memory module according to another exemplary embodiment of the present invention. 12 shows an example in which parity information is generated corresponding to 32-bit data (DATA) as defined in the specification of the DDR5. In addition, according to one embodiment, the parity information stored in the memory module 500B may include only a 4-bit parity code excluding the detection code.

The first to ninth DRAM chips 510_1B to 510_9B may be mounted on the module board of the memory module 500B and each of the first to ninth DRAM chips 510_1B to 510_9B may have a 4 bit The first to eighth DRAM chips 510_1 to 510_8B store the data DATA and the ninth DRAM chip 510_9B stores the parity code Parity. . Further, the module board may be provided with a port 530B corresponding to the DRAM chip for storing the detection code removed from the module board (or not mounted on the module board), and the first to ninth DRAM chips (Fail [1: 9]) containing nine bits generated from the RCDs 510_1B to 510_9B are stored in the RCD 520B, and the RCD 520B stores the fail bits Fail [1: 9] May be sequentially provided to the memory controller through the port 530B.

13 is a block diagram illustrating an embodiment of a memory module according to another exemplary embodiment of the present invention. 13 shows an example in which parity information is generated corresponding to 64-bit data (DATA). In addition, according to one embodiment, the parity information stored in the memory module 500C may include only a 4-bit parity code excluding the detection code. The first to ninth DRAM chips 510_1C to 510_9C may be mounted on the module board of the memory module 500C and each of the first to ninth DRAM chips 510_1C to 510_9C may include eight bits X8, The first to eighth DRAM chips 510_1C to 510_8C may store the data DATA and the ninth DRAM chip 510_9C may store the parity code.

As each of the first to ninth DRAM chips 510_1C to 510_9C inputs and outputs information in 8-bit units, each of the first to eighth DRAM chips 510_1C to 510_8C stores data (DATA) in units of 8 bits, Can be released. On the other hand, according to an embodiment of the present invention, the parity information may include only a parity code corresponding to 4 bits. Accordingly, in the 8-bit write operation for the ninth DRAM chip 510_9C, The dummy data Dummy corresponding to the remaining 4 bits together with the parity code corresponding to the bit can be recorded together with the ninth DRAM chip 510_9C. The dummy data is arbitrary data irrelevant to the actual data (DATA) or the parity code (Parity). For example, the dummy data may have a value of "0"

In the above-described embodiment, 4-bit dummy data is written in the ninth DRAM chip 510_9C as information is input / output in units of 8 bits for each of the first to ninth DRAM chips 510_1C to 510_9C. The embodiments of the present invention need not be limited thereto. As an example, only a 4-bit parity code may be stored in the ninth DRAM chip 510_9C without generating separate dummy data (Dummy). Alternatively, in the ninth DRAM chip 510_9C, additional code information (for example, a random error or a correction code for correcting a multi-bit error) for improving the error correction capability is stored in addition to the 4-bit parity code .

On the other hand, when an existing detection code is used, the detection code can be stored in the ninth DRAM chip 510_9C together with the parity code, whereas in the embodiment of Fig. 13, Lt; RTI ID = 0.0 > 510_9C. ≪ / RTI > That is, in the embodiment of FIG. 13, the detection code is not stored in the DRAM chip separate from the parity code (Parity), and accordingly, there is no separate DRAM chip removed from the module board.

According to one embodiment, a fail bit (Fail [1: 9]) containing nine bits generated from the first to ninth DRAM chips 510_1C to 510_9C is stored in the RCD 520C, and the RCD 520C, May provide a fail bit (Fail [1: 9]) to the memory controller via a separate port 530C formed in the module board. For example, the module board may further include additional ports 530C corresponding to the RCD 520C with nine ports (not shown) corresponding to the first to ninth DRAM chips 510_1C to 510_9C , And RCD 520C may provide the fail bit (Fail [1: 9]) eight bits sequentially to the memory controller via the additional port 530C. As an alternative embodiment, the additional port 530C may include a different number of pins than the port that outputs data (DATA) or parity code (Parity) : 9] may be output sequentially by 4 bits through the additional port 530C.

In addition, the memory controller performs an error correction operation using the 64-bit data (DATA) read from the first to ninth DRAM chips 510_1C to 510_9C and the 4-bit parity code (or the fail- ) Can be performed. At this time, the dummy data (Dummy) is not read or may not be used by the memory controller even if it is read.

14 is a block diagram illustrating an embodiment of a memory module according to another exemplary embodiment of the present invention. In Fig. 14, an example is shown in which a DRAM chip for storing a detection code has not been removed from the module board. 14, the specific number of bits is omitted. However, parity information is generated corresponding to 64-bit data in the same or similar manner as in the above-described embodiments, or parity information corresponding to 32-bit data is generated .

14, M DRAM chips 510_1D through 510_MD may be mounted on the module board of the memory module 500D, and each of the M DRAM chips 510_1D through 510_MD may output information of a plurality of bits . For example, as described above, each of the M DRAM chips 510_1D to 510_MD may output information in units of 4 bits (X4) or 8 bits (X8). In this embodiment, the M DRAM chips 510_1D to 510_MD, It is assumed that each outputs 4-bit (X4) unit information.

Each of the first to (M-2) th DRAM chips 510_1D to 510_ (M-2) D may store and output data (DATA). In addition, the Mth DRAM chip 510_MD may store and output a parity code. In addition, the (M-1) th DRAM chip 510_ (M-1) D used for storing the detection code may store code information (Info_secded) for improving error detection and correction capability.

The RCD 520D may output the fail bits Fail [1: M] provided from the M DRAM chips 510_1D to 510_MD through the port 530D corresponding to the RCD 520D. The ECC engine (not shown) of the memory controller can recover the data (DATA) of the failed DRAM chip by using the fail bit (Fail [1: M]) and the parity code (Parity). The ECC engine of the memory controller can perform error detection and correction operation using the code information (Info_secded) read from the (M-1) th DRAM chip 510_ (M-1) Can be performed. For example, the ECC engine of the memory controller can correct random errors or correct multi-bit errors using code information (Info_secded).

According to one embodiment, the ECC engine of the memory controller stores the data (DATA) read from the first to M-2th DRAM chips 510_1D to 510_ (M-2) D using code information (Info_secded) A single error correction / double error detection (SEC / DED) operation can be performed. However, this is only an embodiment of the present invention, and the code information (Info_secded) may be information used for error detection and correction according to various types of error detection and correction algorithms.

In the case where a large amount of resources for storing the parity information is used for storing the detection code, it is possible to perform a general error correction in addition to restoring the data of the fail chip, or only one bit error can be corrected have. On the other hand, according to the embodiment as described above, the code information used for error detection and correction can be stored in the resource storing the existing detection code, so that the error detection and correction capability can be improved.

In the above-described embodiments, the DRAM chip mounted on the module board has an input / output unit corresponding to the data width of X4 or X8. However, the embodiment of the present invention is not limited thereto, It will be possible to change it into various forms.

15 is a block diagram illustrating an embodiment of a memory module according to another exemplary embodiment of the present invention. In Fig. 15, an example is shown in which the DRAM chip for storing the detection code is not removed from the module board as in the embodiment of Fig. 14 described above. In the embodiment of FIG. 15, it is assumed that each DRAM chip can input and output information as a unit having a plurality of bits, and each of the DRAM chips outputs information of 4 bits (X4) units.

15, M DRAM chips 510_1E to 510_ME may be mounted on the module board of the memory module 500E, and each of the M DRAM chips 510_1D to 510_MD may output information of a plurality of bits have. As an example, each of the first to (M-2) th DRAM chips 510_1E to 510_ (M-2) E may store and output data (DATA). In addition, the Mth DRAM chip 510_ME can store and output a parity code. The (M-1) DRAM chip 510_ (M-1) E used for storing the detection code has a CRC (cyclic redundancy check) code as a detection code indicating the position of the fail chip, (Info_secded) used for the detection / correction operation. Also, the RCD 520E may output the fail bit (Fail [1: M]) provided from the M DRAM chips 510_1E to 510_ME through the port 530E corresponding to the RCD 520E.

 According to the embodiment shown in FIG. 15, since the position of the DRAM chip in which a failure has occurred can be determined through the fail bit (Fail [1: M]), the (M- (Or the number of bits) of the cyclic redundancy check (CRC) code as the detection code stored in the memory 510_ (M-1) E can be minimized. Accordingly, a CRC code having a minimum number of bits (e.g., 1 or 2 bits) is stored in the (M-1) th DRAM chip 510_ (M-1) E and error correction capability Code information (Info_secded) which can be used for additional error detection / correcting operation to improve can be stored. That is, when a fail chip is generated, a recovery operation is performed using a fail bit (Fail [1: M]), a CRC code, and a parity code. Separately, a recovery operation is performed using code information (Info_secded) An operation for detecting / correcting an error that has occurred in the optical disc 100 can be further performed.

16 is a flowchart showing an operation method of the memory controller according to the modified embodiment of the present invention.

Referring to FIG. 16, a memory controller may receive data and parity codes from a semiconductor memory device (e.g., a memory module) including a plurality of DRAM chips (S41). In addition, the memory controller receives the fail bit used for data recovery of the fail chip, and generates a code used for an additional error detection / correction operation (for example, a random error correction or a multi-bit error correction operation) Information can be received (S42). Although not shown in FIG. 16, according to the above-described embodiments, the memory controller may calculate the fail bit having a plurality of bits to receive the generated fail information first, and the fail information may include logic indicating that at least one DRAM chip has failed Level, the memory controller can receive the fail bit by providing a separate command to the semiconductor memory device.

The memory controller can recover the data of the fail chip using the fail bit (S43). For example, the memory controller can determine the location of the DRAM chip where the fail occurred by referring to the fail bit, and recover the DRAM chip data generated through the recovery operation using the received parity code. Further, when the recovery operation is completed, an operation for detecting and correcting an error generated in the plurality of DRAM chips may be further performed, and an error may be detected and corrected using the received code information, for example S44).

17 is a block diagram illustrating a data processing system in accordance with one embodiment of the present invention. Data processing system 600 may include a data server 610 and one or more client computers 621 and 622. The data server 610 and the one or more client computers 621 and 622 may be interconnected via various networks such as the Internet or Wi-Fi. The data server 610 may correspond to a data center, an Internet data center, a cloud data center, or the like.

The data server 610 may include a database 611 and a host 612. The database 611 may include a semiconductor memory device according to the above-described embodiments. As an example, the database 611 may include a plurality of DRAM modules 611_1 according to the above-described embodiments. That is, the semiconductor memory device and the memory controller in the above-described embodiments can be used in a server system. The host 612 may store data in the database 611 and may read the data from the database 611 and provide it to the client computers 621 and 622. [

Host 612 may include a memory controller according to the embodiments described above. Accordingly, the host 612 can generate parity information used for error detection and correction together with the data, and can further store the parity information in the database 611. [ According to one embodiment, each of the memory modules 611_1 included in the database 611 includes a plurality of DRAM chips, and each of the plurality of DRAM chips uses the In DRAM ECC to determine whether failures of respective DRAM chips are generated Can generate the fail bit to indicate. In addition, each of the memory modules 611_1 provided in the database 611 can generate the fail information in the above-described embodiment through the arithmetic operation using the fail bit.

Data and parity information (or parity code) can be read and provided to the host 612 through a read operation on the database 611. [ Also, fail information and / or fail bits may be provided to the host 612 in accordance with the above described embodiments, so that the fail state generated in the database 611 may be reported to the host 612. [ The host 612 can recover the data of the DRAM chip on which the fail is generated by using the received various information.

As described above, exemplary embodiments have been disclosed in the drawings and specification. Although the embodiments have been described herein with reference to specific terms, it should be understood that they have been used only for the purpose of describing the technical idea of the present disclosure and not for limiting the scope of the present disclosure as defined in the claims . Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of protection of the present disclosure should be determined by the technical idea of the appended claims.

Claims (20)

First to Mth memory chips (M is an integer of 2 or more) mounted on the module board and storing data, respectively; And
And a (M + 1) -th memory chip mounted on the module board and storing a parity code for recovering data of a memory chip in which a chip unit fail is generated among the first to Mth memory chips,
Fail bits are generated from the first to (M + 1) th memory chips through an intra-chip error detection operation, and fail information according to a result of calculating fail bits from the first to (M + To the memory module. The method according to claim 1,
Further comprising a buffer chip mounted on the module board for receiving the fail bits from the first to (M + 1) -th memory chips, and calculating the fail bits to generate the fail information Memory modules. 3. The method of claim 2,
Wherein the buffer chip comprises a register for temporarily storing the received fail bits and for outputting the fail bits in response to an access command from a memory controller. 3. The method of claim 2,
The buffer chip receives the fail bits corresponding to (M + 1) bits from the first to (M + 1) th memory chips, and generates a fail bit corresponding to one bit And outputs the information. 5. The method of claim 4,
Wherein the memory module is a non-volatile DIMM (NVDIMM), and the fail information is output through an error report pin defined in association with the operation of the nonvolatile memory of the NVDIMM. The method according to claim 1,
Wherein the module board includes (M + 1) first ports and an additional second port corresponding to the first to (M + 1) -th memory chips, and the first port and the second port are connected to each other Comprising the same number of pins,
And the fail bit is output through the second port. The method according to claim 1,
Wherein code information for correcting at least one of a random error and a multi-bit error generated in the first to Mth memory chips is further stored in the (M + 1) th memory chip. The method according to claim 1,
(M + 2) memory chips mounted on the module board,
And code information for correcting at least one of a random error and a multi-bit error generated in the first to Mth memory chips is stored in the (M + 2) th memory chip. 9. The method of claim 8,
And a detection code indicating a position of a memory chip in which the chip unit fail is generated among the first to Mth memory chips is further stored in the (M + 2) th memory chip. M DRAM chips (M is an integer of 2 or more) each including an in-DRAM error correction circuit (In-DRAM ECC) and outputting a fail bit indicating whether or not a chip unit fails through an internal error detection; And
And a buffer chip for receiving the fail bits from the M DRAM chips and generating and outputting fail information through a calculation operation on the fail bits. 11. The method of claim 10,
Each of the M DRAM chips outputs a 1-bit fail bit having a logic state according to a result of detecting whether an uncorrectable error has occurred,
Wherein the buffer chip generates a 1-bit fail information by calculating a fail bit corresponding to M bits from the M DRAM chips. 11. The method of claim 10,
Wherein the buffer chip comprises a register for temporarily storing the fail bits received from the M DRAM chips and outputting the fail bits in response to an access command from the memory controller. 11. The method of claim 10,
Wherein the M DRAM chips include a plurality of first DRAM chips for storing data and at least one second DRAM chip for storing parity information for recovering failures on a chip-by-chip basis. 14. The method of claim 13,
Wherein the parity information includes only a parity code used for data recovery without a detection code indicating a position of a DRAM chip in which the fail is generated among the M DRAM chips. Receiving data from a plurality of memory chips and a corresponding parity code;
Receiving fail information indicating that at least one of the plurality of memory chips is failed;
Requesting provision of a fail bit indicating a position of a memory chip in which a failure has occurred among the plurality of memory chips; And
And recovering the data of the failed memory chip using the fail bit and the parity code. 16. The method of claim 15,
Selectively generating only a parity code used for recovering the data without generating a detection code indicating a position of the failed memory chip through an encoding process for data to be stored in the plurality of memory chips ; And
And controlling the generated parity code to be stored in one of the plurality of memory chips. 16. The method of claim 15,
Wherein requesting the provision of the fail bit is selectively performed when the received fail information has a first logic state indicating that at least one memory chip has failed. 16. The method of claim 15,
Wherein the requesting of the fail bit is selectively performed when data of the fail chip can not be recovered using the received parity code. 16. The method of claim 15,
Receiving code information for correcting a random error or a multi-bit error, in addition to the parity code for recovery of the fail chip; And
And performing an error correction operation using the code information after recovering the data of the fail chip. 16. The method of claim 15,
Wherein recovering the data is selectively performed when the received fail information has a first logic state indicating that at least one memory chip has failed.

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