KR20170049712A - Organic light emitting display panel, organic light emitting display device, and the method for driving the organic light emitting display device - Google Patents

Abstract

The present invention relates to an organic light emitting display panel, an organic light emitting display device, and a driving method thereof. The organic light emitting display panel having a light shielding pattern connection structure places a light shielding pattern in a lower part of each transistor in a sub-pixel to reduce a change in element characteristics of a transistor, and connects a light shielding pattern corresponding to the each transistor to a different point, thereby reducing a body effect that may occur in each transistor and preventing degradation of the sensing accuracy of characteristics values for a circuit element in each sub-pixel.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting display panel, an organic light emitting display device, and a method of driving the same. BACKGROUND ART [0002]

The present embodiments relate to an organic light emitting display panel, an organic light emitting display, and a driving method thereof.

2. Description of the Related Art Recently, an organic light emitting display device that has been spotlighted as a display device has advantages of high response speed, high luminous efficiency, high brightness, and a wide viewing angle by using an organic light emitting diode (OLED)

The organic light emitting display panel of the OLED display device includes an organic light emitting diode and various transistors for each subpixel.

In an organic light emitting display panel, a circuit element such as a transistor may be deteriorated due to deterioration of the circuit element due to driving time, but may be exposed to light (e.g., external light) to change the device characteristics.

As described above, when the device characteristics of the circuit elements of the organic light emitting display panel change according to the driving time, or when the device characteristics change due to exposure to external light, abnormal driving may be caused to cause a screen abnormal phenomenon.

It is an object of the present embodiments to provide an organic light emitting display panel, an organic light emitting display, and a driving method thereof having a light shielding pattern structure capable of reducing a change in device characteristics with respect to circuit elements in a subpixel.

It is another object of the present embodiments to provide a light emitting device capable of reducing the influence of a body effect that may be generated in a transistor while reducing a change in element characteristics of a transistor by placing a light shielding pattern under each transistor in the sub pixel An organic light emitting display panel having a light-shielding pattern connection structure, an organic light emitting display, and a driving method thereof.

Another object of the present invention is to provide a light emitting device and a light emitting device capable of reducing the influence of a body effect that may be generated in a transistor while reducing a change in element characteristics of the transistor, An organic light emitting diode (OLED) display panel, and a method of driving the OLED display, which have a light-shielding pattern connection structure capable of preventing deterioration of sensing accuracy of characteristic values for circuit elements in subpixels.

A further object of the present embodiments is to reduce the influence of a body effect which may be generated in a transistor by placing a light shielding pattern in a lower portion of each transistor in a subpixel and connecting the respective light shielding patterns to different points An organic light emitting diode (OLED) display panel, and a method of driving the OLED display. The OLED display device has a light-shielding pattern connection structure capable of preventing deterioration in sensing accuracy of characteristic values for circuit elements in each sub-pixel.

In one aspect, the present embodiments provide an organic light emitting diode display panel in which a plurality of data lines and a plurality of gate lines are arranged and in which a plurality of subpixels are arranged, a data driver for driving a plurality of data lines, An organic light emitting display device including a gate driver to be driven can be provided.

Each of the plurality of subpixels in the organic light emitting display includes an organic light emitting diode, a first transistor for driving the organic light emitting diode, a second transistor electrically connected between the first node of the first transistor and the data line, A third transistor electrically connected between the second node of the first transistor and the reference voltage line, and a storage capacitor electrically connected between the first node and the second node of the first transistor.

In such an organic light emitting display, a first light-shielding pattern may be located in a region of the first transistor, a second light-shielding pattern may be located in a region of the second transistor, and a third light-

The first light-shielding pattern, the second light-shielding pattern, and the third light-shielding pattern may be electrically connected to the first bias point, the second bias point, and the third bias point, respectively.

The first bias point, the second bias point, and the third bias point may be positions that are different from each other and are electrically disconnected from each other.

In another aspect, the present embodiments provide an organic light emitting display comprising: an organic light emitting diode; a first transistor for driving the organic light emitting diode; a second transistor electrically connected between the first node of the first transistor and the data line; A third transistor electrically connected between the second node and the reference voltage line and a storage capacitor electrically connected between the first node and the second node of the first transistor for each subpixel may be provided .

In the organic light emitting display panel, the first light-shielding pattern may be located in the first transistor region, the second light-shielding pattern may be located in the second transistor region, and the third light-shielding pattern may be located in the region of the third transistor.

In the OLED display panel, the first light-shielding pattern, the second light-shielding pattern, and the third light-shielding pattern may be electrically connected to the first bias point, the second bias point, and the third bias point, respectively.

Further, in the organic light emitting display panel, the first bias point, the second bias point, and the third bias point may be positions that are different from each other and electrically disconnected from each other (electrically separated).

In another aspect, the present embodiments provide an organic light emitting display comprising an organic light emitting diode, a first transistor for driving the organic light emitting diode, and a second transistor electrically connected between the first node of the first transistor and the data line. Panel can be provided.

In such an organic light emitting display panel, a first light-shielding pattern may be disposed under the first transistor, and a second light-shielding pattern may be disposed under the second transistor.

Also, in the organic light emitting display panel, first and second light emitting patterns may have different first and second bias voltages.

In another aspect, the present embodiments provide an organic light emitting display comprising: an organic light emitting diode; a first transistor for driving the organic light emitting diode; a second transistor electrically connected between the first node of the first transistor and the data line; A third transistor electrically connected between the second node and the reference voltage line and a storage capacitor electrically connected between the first node and the second node of the first transistor, Method can be provided.

A method of driving an OLED display device includes a first step of applying a data voltage and a reference voltage to a first node and a second node of a first transistor, a second step of floating a second node of the first transistor, And a third step of measuring a voltage of a second node of the first transistor through a reference voltage line after a lapse of a predetermined time.

A second light-shielding pattern located under the second transistor, a second light-shielding pattern disposed under the second transistor, and a second light-shielding pattern disposed under the first transistor, The third light-shielding pattern may be connected to different points.

In another aspect, the present embodiments provide an organic light emitting display comprising: an organic light emitting diode; a first transistor for driving the organic light emitting diode; a second transistor electrically connected between the first node of the first transistor and the data line; A third transistor electrically connected between the second node and the reference voltage line, and a storage capacitor electrically connected between the first node and the second node of the first transistor.

In the organic light emitting display panel, the first light-shielding pattern may be located in the first transistor region, the second light-shielding pattern may be located in the second transistor region, and the third light-shielding pattern may be located in the region of the third transistor.

Also, in the organic light emitting display panel, the first light-shielding pattern is electrically connected to the source or drain node of the first transistor, the second light-shielding pattern is electrically connected to the source or drain node of the second transistor, The shading pattern may be electrically connected to a source node or a drain node of the third transistor.

According to the exemplary embodiments of the present invention described above, it is possible to provide an organic light emitting display panel, an organic light emitting display, and a driving method thereof having a light shielding pattern structure capable of reducing variations in device characteristics with respect to circuit elements in subpixels .

In addition, according to the embodiments, a light-shielding pattern can be disposed under each transistor in the sub-pixel to reduce the influence of the body effect that may be generated in the transistor, An organic light emitting diode (OLED) display panel, and a driving method thereof.

In addition, according to the embodiments, a light-shielding pattern is disposed under each transistor in the sub-pixel to reduce the influence of the body effect that may be generated in the transistor while reducing variations in the device characteristics of the transistor, An organic light emitting display panel, an organic light emitting display, and a driving method thereof, each having a light-shielding pattern connection structure capable of preventing deterioration in sensing accuracy of characteristic values for circuit elements in subpixels.

In addition, according to the embodiments, the light-shielding pattern is positioned below each transistor in the sub-pixel, and the respective light-shielding patterns are connected to different points, thereby reducing the influence of the body effect that may be generated in the transistor An organic light emitting diode (OLED) display panel, and a method of driving the OLED display. The OLED display device has a light-shielding pattern connection structure capable of preventing deterioration in sensing accuracy of characteristic values for circuit elements in each sub-pixel.

1 is a system configuration diagram of an organic light emitting display according to the present embodiments.
FIG. 2 is a view illustrating a sub-pixel structure of an OLED display according to an embodiment of the present invention. Referring to FIG.
FIG. 3 is a diagram illustrating an example of a compensation circuit of the OLED display according to the present embodiments. Referring to FIG.
4 is a view for explaining a threshold voltage sensing driving method for the first transistor in the organic light emitting display according to the present embodiments.
5 is a diagram for explaining a mobility sensing driving method for the first transistor in the organic light emitting diode display according to the present embodiments.
6 is a view showing that a light blocking pattern LS is formed under the transistor in order to prevent the characteristic value of the transistor from changing due to light in the organic light emitting diode display 100 according to the present embodiments.
7 is a view illustrating an A-type light-shielding pattern connection structure in the OLED display according to the present embodiments.
8 is a view for explaining a disadvantage of the A-type light-shielding pattern connection structure in the organic light emitting display according to the present embodiments.
9 is a view illustrating a B-type light-shielding pattern connection structure in the OLED display according to the present embodiments.
10 and 11 are views for explaining a disadvantage of the B-type light-shielding pattern connection structure in the organic light emitting display according to the present embodiments.
12 is a view illustrating a C-type light-shielding pattern connection structure in the OLED display according to the present embodiments.
FIG. 13 is a view for explaining a disadvantage of the C-type light-shielding pattern connection structure in the organic light emitting display according to the present embodiments.
FIG. 14 is a view illustrating a connection structure of a D type light-shielding pattern in the OLED display according to the present embodiments.
FIG. 15 is a view for explaining a layer of light-shielding patterns and bias points under the D-type light-shielding pattern connection structure in the organic light emitting display according to the present embodiments.
FIGS. 16 to 17 are views for explaining an advantage of reducing the influence of the body effect of the D-type light-shielding pattern connection structure in the organic light emitting display according to the present embodiments.
FIGS. 18 to 19 are views for explaining the advantages of improving the sensing accuracy of the D-type light-shielding pattern connection structure in the organic light emitting display according to the present embodiments.
20 is a flowchart illustrating a method of driving an organic light emitting display according to an embodiment of the present invention.
FIG. 21 is a view schematically illustrating an organic light emitting display panel and its sub-pixel structure according to the present embodiments.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the components from other components, and the terms do not limit the nature, order, order, or number of the components. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

FIG. 1 is a system configuration diagram of an organic light emitting diode display 100 according to the present embodiments.

1, the OLED display 100 includes a plurality of data lines DL and a plurality of gate lines GL, a plurality of sub pixels (SP) A data driver 120 for driving the plurality of data lines DL; a gate driver 130 for driving the plurality of gate lines GL; a data driver 120 And a controller 140 for controlling the gate driver 130 and the like.

The controller 140 supplies various control signals to the data driver 120 and the gate driver 130 to control the data driver 120 and the gate driver 130.

The controller 140 starts scanning according to the timing implemented in each frame, switches the input image data input from the outside according to the data signal format used by the data driver 120, and outputs the converted image data , And controls the data driving at a suitable time according to the scan.

The controller 140 may be a timing controller used in a conventional display technology or a control device including a timing controller to perform other control functions.

The data driver 120 drives the plurality of data lines DL by supplying data voltages to the plurality of data lines DL. Here, the data driver 120 is also referred to as a 'source driver'.

The gate driver 130 sequentially supplies the scan signals to the plurality of gate lines GL to sequentially drive the plurality of gate lines GL. Here, the gate driver 130 is also referred to as a " scan driver ".

The gate driver 130 sequentially supplies a scan signal of an On voltage or an Off voltage to the plurality of gate lines GL under the control of the controller 140.

When a specific gate line is opened by the gate driver 130, the data driver 120 converts the image data received from the controller 140 into an analog data voltage and supplies the data voltage to a plurality of data lines DL.

1, the data driver 120 is located only on one side (e.g., on the upper side or the lower side) of the organic light emitting display panel 110, : Upper side and lower side).

1, the gate driver 130 is located only on one side (e.g., the left side or the right side) of the organic light emitting display panel 110. However, the gate driver 130 may be disposed on both sides of the organic light emitting display panel 110 For example, left and right).

The controller 140 described above is capable of outputting various kinds of signals including the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the input data enable signal (DE), and the clock signal (CLK) Timing signals from the outside (e.g., the host system).

The controller 140 outputs the converted image data by switching the input image data inputted from the outside in accordance with the data signal format used by the data driver 120 and outputs the converted image data to the data driver 120 and the gate driver 130, A timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input DE signal and a clock signal and generates various control signals to control the data driver 120 and the gate driver 130, .

For example, in order to control the gate driver 130, the controller 140 generates a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal GOE Gate Output Enable), and the like.

Here, the gate start pulse GSP controls the operation start timing of one or more gate driver integrated circuits constituting the gate driver 130. The gate shift clock GSC is a clock signal commonly input to one or more gate driver integrated circuits, and controls the shift timing of the scan signal (gate pulse). The gate output enable signal GOE specifies the timing information of one or more gate driver ICs.

In order to control the data driver 120, the controller 140 may further include a source start pulse (SSP), a source sampling clock (SSC), a source output enable signal (SOE) And outputs various data control signals (DCS: Data Control Signals).

Here, the source start pulse SSP controls the data sampling start timing of one or more source driver integrated circuits constituting the data driver 120. The source sampling clock SSC is a clock signal for controlling sampling timing of data in each of the source driver integrated circuits. The source output enable signal SOE controls the output timing of the data driver 120.

The data driver 120 may drive a plurality of data lines including at least one source driver integrated circuit (SDIC).

Each source driver integrated circuit (SDIC) is connected to a bonding pad of the organic light emitting display panel 110 by a tape automated bonding (TAB) method or a chip on glass (COG) Or may be directly disposed on the organic light emitting display panel 110, and may be integrated and disposed on the organic light emitting display panel 110, as the case may be. In addition, each source driver integrated circuit (SDIC) may be implemented by a chip on film (COF) method, which is mounted on a film connected to the organic light emitting display panel 110.

Each source driver integrated circuit (SDIC) may include a shift register, a latch circuit, a digital to analog converter (DAC), an output buffer, and the like.

Each source driver integrated circuit (SDIC) may further include an analog to digital converter (ADC), as the case may be.

The gate driver 130 may include at least one gate driver integrated circuit (GDIC).

Each gate driver integrated circuit GDIC may be connected to a bonding pad of the organic light emitting display panel 110 by a tape automated bonding (TAB) method or a chip on glass (COG) ) Type and may be directly disposed on the organic light emitting display panel 110 or may be integrated on the organic light emitting display panel 110 as the case may be. In addition, each gate driver IC (GDIC) may be implemented by a chip on film (COF) method, which is mounted on a film connected to the organic light emitting display panel 110.

Each gate driver IC (GDIC) may include a shift register, a level shifter, and the like.

The OLED display 100 according to the present embodiments includes at least one source printed circuit board (S-PCB) necessary for circuit connection to at least one source driver IC (SDIC) And a control printed circuit board (C-PCB) for mounting control components and various electric devices.

At least one source driver integrated circuit (SDIC) may be mounted on at least one source printed circuit board (S-PCB), or a film on which at least one source driver integrated circuit (SDIC) is mounted may be connected.

The control printed circuit board (C-PCB) is provided with a controller 140 for controlling the operation of the data driver 120 and the gate driver 130 and the like, and a controller 140 for controlling operations of the organic light emitting display panel 110, the data driver 120, A power controller for controlling various voltages or currents to supply or supply various voltages or currents to the battery 130, or the like.

The at least one source printed circuit board (S-PCB) and the control printed circuit board (C-PCB) may be circuitly connected via at least one connecting member.

Here, the connecting member may be a flexible printed circuit (FPC), a flexible flat cable (FFC), or the like.

At least one source printed circuit board (S-PCB) and a control printed circuit board (C-PCB) may be integrated into one printed circuit board.

Each sub-pixel SP disposed in the organic light emitting display panel 110 may include a circuit element such as a transistor.

For example, when the organic light emitting display panel 110 is an organic light emitting display panel, each sub pixel SP includes an organic light emitting diode (OLED) and a driving transistor for driving the organic light emitting diode Circuit elements.

The types and the number of the circuit elements constituting each subpixel SP can be variously determined depending on the providing function, the design method, and the like.

2 is an exemplary view of a sub-pixel structure of the OLED display 100 according to the present embodiments.

Referring to FIG. 2, in the OLED display 100 according to the present embodiment, each sub-pixel basically includes an organic light emitting diode (OLED) and an organic light emitting diode (OLED) (T2) for transferring a data voltage (Vdata) to a first node (N1) corresponding to a gate node of the first transistor (T1), a first transistor And a storage capacitor C1 for holding a data voltage corresponding to a video signal voltage or a voltage corresponding thereto for one frame time.

The organic light emitting diode OLED may include a first electrode (e.g., an anode electrode), an organic layer, and a second electrode (e.g., a cathode electrode).

The first transistor T1 is a driving transistor for driving the organic light emitting diode OLED and supplies driving current to the organic light emitting diode OLED to drive the organic light emitting diode OLED.

The first node N1 of the first transistor T1 may be electrically connected to the source node or the drain node of the second transistor T2 and may be a gate node. The second node N2 of the first transistor T1 may be electrically connected to the first electrode of the organic light emitting diode OLED and may be a source node or a drain node. The third node N3 of the first transistor T1 may be electrically connected to a driving voltage line DVL for supplying a driving voltage EVDD and may be a drain node or a source node.

The first transistor T1 and the second transistor T2 may be either n-type or p-type, as in the example of FIG.

The second transistor T2 is electrically connected between the data line DL and the first node N1 of the first transistor T1 and receives the scan signal SCAN through the gate line to control the gate node .

The second transistor T2 may be turned on by the scan signal SCAN to transfer the data voltage Vdata supplied from the data line DL to the first node N1 of the first transistor T1 .

The storage capacitor C1 may be electrically connected between the first node N1 and the second node N2 of the first transistor T1.

The storage capacitor C1 is not a parasitic capacitor (for example, Cgs or Cgd) which is an internal capacitor existing between the first node N1 and the second node N2 of the first transistor T1 And an external capacitor which is intentionally designed outside the first transistor T1.

On the other hand, in each subpixel SP disposed in the organic light emitting display panel 110 according to the present embodiment, the circuit elements such as the organic light emitting diode OLED and the first transistor Tl have unique characteristic values .

Here, the organic light emitting diode OLED has a characteristic value such as a threshold voltage, and the first transistor T1 corresponding to the driving transistor has a characteristic value such as a threshold voltage and a mobility.

As the driving time of each sub-pixel SP becomes longer, the degradation of circuit elements such as the organic light emitting diode OLED and the first transistor T1 can be progressed.

Accordingly, inherent characteristic values (e.g., threshold voltage, mobility, etc.) of circuit elements such as the organic light emitting diode OLED and the first transistor T1 can be changed.

A change in the characteristic value of a circuit element in the sub-pixel causes a change in luminance of the corresponding sub-pixel. Therefore, the change in the characteristic value of the circuit element can be used in the same concept as the change in luminance of the subpixel.

In addition, the change in the characteristic value of the circuit elements in the sub-pixels may differ depending on the degree of deterioration of the circuit elements.

Therefore, characteristic value deviations may occur between the circuit elements, and such characteristic deviation between the circuit elements causes a luminance deviation between the subpixels. Therefore, the characteristic value deviation between the circuit elements can be used in the same concept as the luminance deviation between the subpixels.

The above-described subpixel luminance variation and subpixel luminance variation are caused by variations in the characteristic values of the circuit elements and deviation of characteristic values between the circuit elements, resulting in degradation of the accuracy with respect to the luminance expressiveness of the subpixels, It can cause problems.

Here, the characteristic value of a circuit element (hereinafter also referred to as a "subpixel characteristic value") may include, for example, a threshold voltage and mobility of the first transistor T1, ). ≪ / RTI >

The OLED display 100 according to the present embodiment includes a sensing function for sensing a characteristic value of a subpixel and a compensation function for compensating a luminance variation of the subpixel and a luminance deviation between the subpixels using the sensing result .

The sensing of the characteristic value of the subpixel means sensing the characteristic value (for example, threshold voltage, mobility) of the first transistor T1 which is the driving transistor and sensing the characteristic value of the organic light emitting diode OLED, Lt; / RTI >

The sensing of the characteristic value (for example, the threshold voltage and the mobility) of the first transistor T1 which is the driving transistor is performed by sensing the characteristic value change of the first transistor T1, Lt; / RTI >

Sensing a characteristic value (for example, a threshold voltage) of the organic light emitting diode OLED may include sensing a characteristic value change of the organic light emitting diode OLED or sensing a characteristic value deviation between the organic light emitting diodes OLED .

The organic light emitting diode display 100 according to the present exemplary embodiment includes a sub pixel structure and a compensation circuit including a sensing and compensation structure to provide a sensing and compensating function for sensing and compensating the characteristic value of the sub pixel. .

3 is an exemplary view of a compensation circuit of the OLED display 100 according to the present embodiments.

Referring to FIG. 3, each sub-pixel disposed in the organic light emitting display panel 110 according to the present embodiment includes an organic light emitting diode (OLED), a first transistor T1, a second transistor T2, And a storage capacitor C1, a third transistor T3 may be further included.

The subpixel illustrated in FIG. 3 has a 3T (Transistor) 1C (Capacitor) structure in that it includes three transistors T1, T2, and T3 and one capacitor C1.

3, the third transistor T3 is connected between the second node N2 of the first transistor T1 and a reference voltage line RVL for supplying a reference voltage Vref And is electrically connected.

The third transistor T3 may be controlled by receiving a sensing signal SENSE, which is a kind of a scan signal, to the gate node.

The third transistor T3 is turned on by the sensing signal SENSE to apply the reference voltage Vref supplied through the reference voltage line RVL to the second node N2 of the first transistor T1 It does.

Also, the third transistor T3 may be utilized as one of the voltage sensing paths for the second node N2 of the first transistor T1.

Meanwhile, the scan signal SCAN and the sense signal SENSE may be separate gate signals. In this case, the scan signal SCAN and the sense signal SENSE may be respectively applied to the gate node of the second transistor T2 and the gate node of the third transistor T3 through different gate lines.

In some cases, the scan signal SCAN and the sense signal SENSE may be the same gate signal. In this case, the scan signal SCAN and the sense signal SENSE may be commonly applied to the gate node of the second transistor T2 and the gate node of the third transistor T3 through the same gate line.

3, the organic light emitting diode display 100 according to the present invention senses the characteristic values of the subpixel (i.e., the characteristic values of the first transistor T1 and the characteristic values of the organic light emitting diode OLED) A memory 320 for storing sensing data, and a compensation unit 330 for performing a compensation process for compensating the characteristic value of the subpixel using the sensing data.

The sensing unit 310 may include at least one analog-to-digital converter (ADC).

Each analog-to-digital converter (ADC) may be included inside the source driver integrated circuit (SDIC) and, in some cases, may be included outside the source driver integrated circuit (SDIC).

The compensation unit 330 may be included inside the controller 140 and, in some cases, may be included outside the controller 140.

The sensing data output from the sensing unit 310 may be, for example, a Low Voltage Differential Signaling (LVDS) data format.

The organic light emitting diode display 100 according to the present exemplary embodiment is configured to control the sensing operation of the organic light emitting diode display 100 according to the first embodiment of the present invention in which the voltage application state of the second node N2 of the first transistor T1 in the sub- And may further include a first switch SW1 and a second switch SW2 for controlling the state required for sensing the characteristic value.

The supply of the reference voltage Vref to the reference voltage line RVL can be controlled through the first switch SW1.

When the first switch SW1 is turned on, the reference voltage Vref is supplied to the reference voltage line RVL and is supplied to the second node T1 of the first transistor T1 through the third transistor T3, (N2).

On the other hand, when the voltage of the second node N2 of the first transistor T1 becomes a voltage state reflecting the characteristic value of the subpixel, a reference potential that may be equal to the second node N2 of the first transistor T1 The voltage of the voltage line RVL may also be a voltage state reflecting the sub-pixel characteristic value. At this time, the line capacitor formed on the reference voltage line RVL may be charged with a voltage reflecting the sub-pixel characteristic value.

When the voltage of the second node N2 of the first transistor T1 becomes a voltage state reflecting the subpixel characteristic value, the second switch SW2 is turned on and the sensing unit 310 and the reference voltage line RVL ) Can be connected.

Accordingly, the sensing unit 310 senses the voltage of the reference voltage line RVL, that is, the voltage of the second node N2 of the first transistor T1, which reflects the subpixel characteristic value. Here, the reference voltage line RVL is also referred to as a "sensing line ".

The reference voltage lines RVL may be arranged, for example, one for each sub-pixel column, or one for each of two or more sub-pixel columns.

For example, when one pixel is composed of four subpixels (red subpixel, white subpixel, green subpixel, and blue subpixel), the reference voltage line RVL is divided into four subpixel columns , A white subpixel column, a green subpixel column, and a blue subpixel column).

When the sensing unit 310 is connected to the reference voltage line RVL, the voltage of the second node N2 of the first transistor T1 (the voltage of the reference voltage line RVL or the voltage of the reference voltage line RVL) Voltage charged in the line capacitor).

The voltage sensed by the sensing unit 310 may be a voltage value (Vdata-Vth or Vdata-? Vth) including a threshold voltage Vth or a threshold voltage deviation? Vth of the first transistor T1, T1) of the mobile terminal.

In the following, the threshold voltage sensing driving and the mobility sensing driving for the first transistor T1 will be briefly described.

4 is a diagram for explaining a threshold voltage sensing driving method for the first transistor T1 in the OLED display 100 according to the present embodiments.

4, when the threshold voltage sensing operation of the first transistor Tl is performed, the first node N1 and the second node N2 of the first transistor T1 respectively receive the threshold voltage sensing driving data voltage Vdata and the reference voltage Vref.

Thereafter, the first switch SW1 is turned off and the second node N2 of the first transistor T1 is floated.

Accordingly, the voltage of the second node N2 of the first transistor T1 rises. The voltage of the second node N2 of the first transistor T1 rises for a predetermined time, and then the rising width thereof gradually decreases and becomes saturated.

The saturated voltage of the second node N2 of the first transistor T1 may correspond to the difference between the data voltage Vdata and the threshold voltage Vth or the difference between the data voltage Vdata and the threshold voltage deviation Vth have.

Here, the threshold voltage Vth of the first transistor T1 may be a positive threshold voltage or a negative threshold voltage.

The sensing unit 310 senses the saturated voltage of the second node N2 of the first transistor T1 when the voltage of the second node N2 of the first transistor T1 is saturated.

The voltage Vsense sensed by the sensing unit 310 is a voltage Vdata-Vth obtained by subtracting the threshold voltage Vth from the threshold voltage sensing driving data voltage Vdata or a voltage Vdata- (Vdata -? Vth) obtained by subtracting the threshold voltage deviation (? Vth).

5 is a view for explaining a mobility sensing driving method for the first transistor T1 in the OLED display 100 according to the present embodiments.

Referring to FIG. 5, in the mobility sensing operation, the first node N1 and the second node N2 of the first transistor T1 are initialized to the data voltage for the mobility sensing operation and the reference voltage Vref .

The mobility sensing operation may proceed after the threshold voltage compensation. In this case, the data voltage for mobility sensing operation may be a form (Vdata + Vth_comp) in which the data voltage Vth_comp for threshold voltage compensation is added.

Thereafter, the first switch SW1 is turned off and the second node N2 of the first transistor T1 is floated.

Accordingly, the voltage of the second node N2 of the first transistor T1 rises.

Here, the voltage rising rate (change amount DELTA V with respect to time) with respect to the second node N2 of the first transistor T1 indicates the current capability, i.e., the mobility, of the first transistor T1.

Therefore, the voltage of the second node N2 of the first transistor T1 rises more steeply as the first transistor T1 having a higher current capability (mobility) is.

The sensing unit 310 senses an increased voltage of the second node N2 of the first transistor T1, that is, the second node N2 of the first transistor T1, after the voltage is raised for a predetermined period of time, The voltage of the reference voltage line RVL is increased.

4 and 5, the sensing unit 310 converts the sensed voltage Vsense to a digital value for threshold voltage sensing or mobility sensing according to the threshold voltage or mobility sensing driving described above, And outputs the generated sensing data.

The sensing data output from the sensing unit 310 may be stored in the memory 320 or may be provided to the compensating unit 330.

The compensation unit 330 may store characteristic values (e.g., threshold voltage, mobility) of the first transistor T1 in the corresponding subpixel or characteristics of the first transistor T1 in the corresponding subpixel based on the sensing data stored in the memory 320 or provided by the sensing unit 310 (For example, a change in threshold voltage and a change in mobility) of the characteristic values of the first and second transistors T1 and T1.

Here, the change in the characteristic value of the first transistor T1 means that the current sensing data is changed based on the previous sensing data, or the current sensing data is changed based on the reference sensing data.

Here, when comparing the characteristic value or the characteristic value change between the first transistors T1, the characteristic value deviation between the first transistors T1 can be grasped. When the characteristic value change of the first transistor T1 means that the current sensing data is changed with reference to the reference sensing data, the deviation of the characteristic value between the first transistors T1 from the characteristic value change of the first transistor T1 Luminance deviation) can be grasped.

The characteristic value compensation process may include a threshold voltage compensation process for compensating the threshold voltage of the first transistor T1 and a mobility compensation process for compensating the mobility of the first transistor T1.

The threshold voltage compensation process may be performed by calculating a compensation value for compensating for a threshold voltage or a threshold voltage deviation (threshold voltage change), storing the calculated compensation value in the memory 320, For example.

The mobility compensation process calculates a compensation value to compensate for mobility or mobility deviation (mobility change), stores the calculated compensation value in the memory 320, or stores the corresponding image data Data as the calculated compensation value, For example.

The compensation unit 330 may change the image data Data through the threshold voltage compensation process or the mobility compensation process and supply the changed data to the corresponding source driver integrated circuit (SDIC) in the data driver 120.

Accordingly, the source driver integrated circuit (SDIC) converts the changed data into the data voltage and supplies the data voltage to the corresponding subpixel by using the digital-to-analog converter 340 so that the subpixel characteristic value compensation (threshold voltage compensation, mobility compensation ) Is actually realized.

By compensating for the subpixel characteristic value, luminance deviation between the subpixels is reduced or prevented, thereby improving the image quality.

As described above, the transistor such as the first transistor T1 corresponding to the driving transistor may deteriorate as the driving time becomes longer, and the characteristic value may change.

Not only the driving time but also the characteristic value of the transistor can be changed by the light.

For example, when external light touches a transistor (particularly, a channel region), a phenomenon occurs in which the threshold voltage or the threshold voltage variation is shifted in the negative (-) direction, and the transistor device characteristics deteriorate.

6 is a view showing that a light blocking pattern LS is formed under the transistor in order to prevent the characteristic value of the transistor from changing due to light in the organic light emitting diode display 100 according to the present embodiments.

Referring to FIG. 6, the transistor may be formed of a source node S, a drain node D, and a gate node G.

When light is irradiated on such a transistor (in particular, a channel region of the transistor), the device characteristics (e.g., threshold voltage, etc.) of the transistor may be changed.

Therefore, according to the present embodiments, the light-shielding pattern LS is formed below the transistor.

Thus, even if the transistor is irradiated with light, it is possible to prevent the device characteristics of the transistor from being changed.

The light-shielding pattern LS may be made of a metal material capable of blocking the transmission of light.

On the other hand, the light shielding pattern LS is located under the gate node (gate electrode) of the transistor with the insulating layer interposed therebetween, and can serve as the body B of the transistor.

Therefore, a bias voltage is applied to the light-shielding pattern LS serving as the body B, and thus, the light-shielding pattern LS can be connected to other surrounding voltage patterns.

In the following, various types of structures in which the light-shielding pattern LS located at the bottom of the transistor is connected to the surrounding pattern will be exemplified.

However, the connection structure between the light-shielding pattern LS and the peripheral pattern is referred to as a "light-shielding pattern connection structure ", and the sub-pixel structure of FIG. 3 will be described as an example.

7 is a view illustrating an A-type light-shielding pattern connection structure in the OLED display 100 according to the present embodiments.

Referring to FIG. 7, the organic light emitting diode display 100 according to the present embodiment has the first light-shielding pattern LS1 only in the region of the first transistor T1, which is the driving transistor, A type light-shielding pattern connection structure.

The first light-shielding pattern LS1 located in the region of the first transistor T1 (which may be a lower region located under the gate insulating layer) is connected to the source node (or drain node) of the first transistor T1, Lt; RTI ID = 0.0 > N2. ≪ / RTI >

Since the first light-shielding pattern LS1 exists on a different layer from the second node N2 of the first transistor T1, the first light-shielding pattern LS1 is connected to the second node N2 of the first transistor T1, (N2) and the contact hole (Contact Hole).

8 is a view for explaining a disadvantage of the A-type light-shielding pattern connection structure in the OLED display 100 according to the present embodiments.

Referring to FIG. 8, as described above with reference to FIG. 7, a first light-shielding pattern (not shown) electrically connected to the second node N2 of the first transistor T1 only in a region of the first transistor T1 The second transistor T2 and the third transistor T3 may be exposed to light (which may be external light that is input from the outside) since the transistor LS1 is present.

Accordingly, unlike the first transistor T1, the second transistor T2 and the third transistor T3 may undergo a change in device characteristics due to light.

A change in the device characteristics of the second transistor T2 and the third transistor T3 may cause a problem in switching performance, resulting in abnormal display driving, which may result in a screen abnormal phenomenon.

In order to overcome the disadvantage of the A-type light-shielding pattern connection structure, the second light-shielding pattern LS2 and the third light-shielding pattern LS2 are formed in the regions of the second transistor T2 and the third transistor T3 as well as the first transistor T1, Three types (B, C and D types) of light-shielding pattern connection structures in which a pattern LS3 is formed are proposed.

9 is a view illustrating a B-type light-shielding pattern connection structure in the OLED display 100 according to the present embodiments.

9, the organic light emitting diode display 100 according to the present embodiment includes a first light-shielding pattern LS1 (first light-shielding pattern) LS1, a second light-emitting pattern LS2 The first light-shielding pattern LS1 and the second transistor T2 located in a region (lower portion) of the first transistor T1 respectively have a first light-shielding pattern LS2, a second light-shielding pattern LS2 and a third light- The second light-shielding pattern LS2 located in the lower region of the third transistor T3 and the third light-shielding pattern LS3 located in the lower region of the third transistor T3 are electrically connected together at one bias point PV1 Type B-type shielding pattern connecting structure.

9, the bias point PV1, to which the first light-shielding pattern LS1, the second light-shielding pattern LS2 and the third light-shielding pattern LS3 are electrically connected, is connected to the source node of the first transistor T1, (Or a second node N2 corresponding to a drain node).

10 and 11 are views for explaining a disadvantage of the B-type light-shielding pattern connection structure in the organic light emitting diode display 100 according to the present embodiments.

Referring to FIG. 10, according to the light-blocking pattern connecting structure of the B type, the bias voltage V1 applied to the bias point PV1 can be considerably increased by the driving state, the threshold voltage of the organic light emitting diode OLED,

That is, according to the B-type light-shielding pattern connection structure, the first light-shielding pattern LS1 located in the region (lower portion) of the first transistor T1, the second light- A considerably high bias voltage V1 is applied to the light blocking pattern LS2 and the third light blocking pattern LS3 located in the region (lower portion) of the third transistor T3.

In this case, even if the scan signal SCAN of the turn-off gate voltage VGL is applied to the gate node of the second transistor T2 to turn off the second transistor T2 in accordance with the driving situation, LS2 may function as another gate node (also referred to as a back gate node), so that the second transistor T2 may be turned on. This phenomenon is called "body effect ".

This body effect turns on when the second transistor T2 corresponding to the switching transistor is to be turned off and the data voltage Vdd is applied to the first node N1, which is the gate node of the first transistor T1, (Vdata) is applied.

Therefore, the subpixel becomes an undesired display drive, and may cause a screen abnormal phenomenon.

The above-described body effect and thus abnormal display drive and screen abnormal phenomenon can occur in the same manner with respect to the third transistor T3.

11 is a graph showing a threshold voltage change (? Vth) of a corresponding transistor with respect to a bias voltage (LS Bias) applied to a light shielding pattern serving as a body.

Referring to FIG. 11, as the bias voltage (LS Bias) applied to the shielding pattern increases, the threshold voltage change (? Vth) of the transistor can be increased in the negative (-) direction.

That is, as the bias voltage (LS Bias) applied to the shielding pattern increases, the absolute value of the threshold voltage change (? Vth) having a minus (-) value can become larger.

This is because the threshold voltage Vth of the transistor shifts in the negative direction (-) as the bias voltage (LS Bias) applied to the shielding pattern increases.

Due to the negative shift of the threshold voltage in accordance with the bias voltage (LS Bias) applied to the shading pattern, the transistor can be easily turned on at a lower gate voltage.

In other words, even when the bias voltage applied to the light-shielding pattern that can operate as a back gate node is not so high, the transistor can be easily turned on. That is, the "body effect" described with reference to Fig. 10 can be more easily generated.

In this point of view, in the case of the B-type light-shielding pattern connection structure, the bias voltage V1 commonly applied to the first light-shielding pattern LS1, the second light-shielding pattern LS2 and the third light- Because of this, body effects can occur very easily and to a serious degree.

Hereinafter, a C-type shielding pattern connecting structure and a D-type shielding pattern connecting structure capable of solving the problem of the B-type shielding pattern connecting structure will be described below.

12 is a view illustrating a C-type light-shielding pattern connection structure in the OLED display 100 according to the present embodiments.

12, the organic light emitting diode display 100 according to the present embodiment includes a first light-shielding pattern LS1 (first light-shielding pattern) LS1, a second light-emitting pattern LS2 The first light-shielding pattern LS1 located in a region (lower portion) of the first transistor Tl is the first light-shielding pattern LS1, the second light-shielding pattern LS2, and the third light-shielding pattern LS3. The second light-shielding pattern LS2 electrically connected to the first bias point PV1 corresponding to the second node N2 of the second transistor T2 and the second light- The third light blocking pattern LS3 located in the lower region of the first transistor T1 is connected to the first bias point PV1 corresponding to the second node N2 which is the source node (or drain node) Type light-shielding pattern connection structure electrically connected together to the second bias point PV2 at the other side.

According to the C-type light-shielding pattern connection structure, the second light-shielding pattern LS2 located in the lower region of the second transistor T2 and the third light-shielding pattern LS2 located in the region The second bias point PV2 to which the pattern LS3 is electrically connected together can be either one point on the reference voltage line RVL or the drain node (or source node) of the third transistor T3 have.

13 is a view for explaining a disadvantage of the C-type light-shielding pattern connection structure in the OLED display 100 according to the present embodiments.

Referring to FIG. 13, in the C-type light-shielding pattern connection structure, the second light-shielding pattern LS2 located in the lower region of the second transistor T2 and the lower region of the third transistor T3 The second bias voltage V2 applied to the third light-emitting pattern LS3 positioned is a voltage corresponding to the reference voltage Vref and is a voltage corresponding to the first light- Is substantially lower than the first bias voltage V1 applied to the first node LS1.

As described above, the second light-shielding pattern LS2 and the bias voltage V2 applied to the third light-shielding pattern LS3 according to the C-type light-shielding pattern connection structure are formed by the second light- Is lower than the bias voltage V1 applied to the third light-shielding pattern LS2 and the third light-shielding pattern LS3. Therefore, when the C-type light-shielding pattern connection structure is applied, the bias voltage and the threshold voltage negative shift phenomenon The body effect and the resulting screen anomaly can be greatly reduced as compared with the B type light-shielding pattern connection structure.

However, the number of electrical plates (Plate, LS2, LS3) connected to the reference voltage line (RVL) increases, and the parasitic capacitance (Cp) of the reference voltage line (RVL) may increase.

Since the reference voltage line RVL is utilized as a sensing line as described above with reference to FIGS. 3 to 5, an increase in the parasitic capacitance Cp of the reference voltage line RVL is greater than that of the reference voltage line RVL. There is a high possibility that an error of the sensing voltage Vsense occurs.

That is, the C-type light-shielding pattern connection structure may cause a decrease in sensing accuracy due to an increase in the parasitic capacitance Cp of the reference voltage line RVL.

Accordingly, the OLED display 100 according to the present embodiments can have a D-type shielding pattern connecting structure that reduces the body effect and the influence thereof and does not deteriorate the sensing accuracy.

In the following, the D type light-shielding pattern connecting structure will be described in more detail.

FIG. 14 is a view illustrating a connection structure of a D type light-shielding pattern in the OLED display 100 according to the present embodiments.

14, a first light-shielding pattern LS1, a second light-shielding pattern LS2 and a third light-shielding pattern LS3 are formed in the regions of the first transistor T1, the second transistor T2 and the third transistor T3. And the third light-shielding pattern LS3 are divided and connected to different points PV1, PV2, and PV3, respectively, of the first light-shielding pattern LS1, the second light-shielding pattern LS2, Pattern connection structure.

More specifically, the first light-shielding pattern LS1 is located in a region of the first transistor T1 (for example, the lower portion) and the second light-shielding pattern LS2 (for example, And the third light-shielding pattern LS3 may be located in a region (e.g., a lower portion) of the third transistor T3.

The first light-shielding pattern LS1, the second light-shielding pattern LS2 and the third light-shielding pattern LS3 are formed on the first bias point PV1, the second bias point PV2 and the third bias point PV3 And can be electrically connected.

The first bias point PV1, the second bias point PV2, and the third bias point PV3 may be positions that are different from each other and that are electrically disconnected from each other.

According to the D-type light-shielding pattern connection structure illustrated in FIG. 14, the body effect and the influence thereof can be greatly reduced, and deterioration in sensing accuracy can be prevented.

Compared with other types, the D-type shielding pattern connection structure has a significantly improved sensing effect compared to the C-type shielding pattern connection structure, while greatly reducing the body effect and its influence compared to the A- and B- Can be prevented.

As described above, the first bias point PV1, the second bias point PV2, and the third bias point PV3 are possible if they are positions that are different from each other and are electrically isolated.

For example, the first bias point PV1 may be the second node N2 of the first transistor T1, which may be the source node (or drain node). The second bias point PV2 may be a drain node or a source node of the second transistor T2 electrically connected to the data line DL or may be a point on the data line DL. The third bias point PV3 may be a drain node or a source node of the third transistor T3 electrically connected to the reference voltage line RVL or may be a point on the reference voltage line RVL.

In the case where the positions for the first bias point PV1, the second bias point PV2 and the third bias point PV3 are defined, a light-shielding pattern connection structure suitable for the 3T1C sub-pixel structure as shown in FIG. 3 is provided can do.

15 is a sectional view of the organic light emitting diode display 100 according to the exemplary embodiment of the present invention in which the light blocking patterns LS1, LS2, and LS3 and the bias points PV1, PV2, and PV3 (Layer).

15, there may be a Light Shield (LS) layer 1510 on which a first light-shielding pattern LS1, a second light-shielding pattern LS2, and a third light-shielding pattern LS3 can be placed on a substrate .

The gate insulating film 1520 may be located on the LS layer 150.

A gate material layer 1530 may be positioned on the gate insulating layer 1520 and an interlayer insulating layer 1540 may be located on the gate material layer 1530 on which the source- Can come.

The stacking of the layers 1510, 1520, 1530, 1540, 1540 and 1550 shown in FIG. 15 is performed by using layers of the light blocking patterns LS1, LS2 and LS3 and the bias points PV1, PV2 and PV3, , There may be at least one other layer between the two layers.

Referring to FIG. 15, the first bias point PV1, the second bias point PV2 and the third bias point PV3 are connected in series between the drain node of the source-drain material N2, T2, The first bias point PV1, the second bias point PV2 and the third bias point PV3 are patterned in the source-drain layer 1550 since the first bias point PV1, the second bias point PV2 and the third bias point PV3 can be connected to the source-drain layers 1550 Can be located.

The first light-shielding pattern LS1, the second light-shielding pattern LS2 and the third light-shielding pattern LS3 connected to the first bias point PV1, the second bias point PV2 and the third bias point PV3, May be located in a different layer (1510) than the source-drain layer (1550).

The first bias point PV1, the second bias point PV2 and the third bias point PV3 are connected to the first light-shielding pattern LS1, the second light-shielding pattern LS2, (LS3) and can be electrically connected.

The layers of the light-shielding patterns LS1, LS2, and LS3 and the bias points PV1, PV2, and PV3 can be designed without greatly changing the stack structure of the existing layers.

The first light-shielding pattern LS1 that can be positioned below the first transistor T1 is a body node of the first transistor T1 to which the first bias voltage V1 is applied, The second light-shielding pattern LS2 that can be positioned below the third transistor T3 is a body node of the second transistor T2 to which the second bias voltage V2 is applied, The third light-shielding pattern LS3 may be a body node of the third transistor T3 to which the third bias voltage V3 is applied.

As described above, the first light-shielding pattern LS1 is the body node of the first transistor T1, the second light-shielding pattern LS2 is the body node of the second transistor T2, Second, and third transistors T1, T2, and T3 are turned on according to the first, second, and third bias voltages V1, V2, and V3, respectively, since the third transistor T3 is used as a body node of the third transistor T3. It is possible to control the body effect for each of them.

FIGS. 16 to 17 are views for explaining the advantages of reducing the influence of the body effect of the D-type light-shielding pattern connection structure in the OLED display 100 according to the present embodiments.

16, a second transistor T2 serving as a switching transistor for transferring a data voltage Vdata to a first node N1 serving as a gate node of a first transistor T1, which is a driving transistor, The second bias voltage V2 applied to the second light blocking pattern LS2 may be lower than the first bias voltage V1 applied to the first light blocking pattern LS1 located below the first transistor T1.

Therefore, even though the turn-off gate voltage VGL is applied to the gate node of the second transistor T2, it is possible to prevent the second transistor T2 from turning on due to the body effect. Thus, when the turn-off gate voltage VGL is applied to the gate node of the second transistor T2, the data voltage Vdata at the data line DL is applied to the first node T1 of the first transistor T1 N1 from being unnecessarily transmitted.

Referring to FIG. 17, a third transistor (serving as a switching transistor) for transferring a reference voltage Vref to a second node N2 that is a source node (or a drain node) of the first transistor T1 The third bias voltage V3 applied to the third light-shielding pattern LS3 located below the first transistor T1 is applied to the first light-emitting pattern LS1, which is located below the first transistor T1, V1).

Therefore, even though the turn-off gate voltage VGL is applied to the gate node of the third transistor T3, it is possible to prevent the third transistor T3 from turning on due to the body effect. Therefore, when the turn-off gate voltage VGL is applied to the gate node of the third transistor T3, the reference voltage Vref in the reference voltage line RVL is applied to the second node T3 of the first transistor T1, It is possible to prevent unnecessary transmission to the node N2.

16, since the second bias voltage V2 is lower than the first bias voltage V1, when the second transistor T2 is to be turned off, due to the body effect, And the data voltage Vdata is unnecessarily transmitted to the first node N1 of the first transistor T1.

17, since the third bias voltage V3 is lower than the first bias voltage V1, the third transistor T3 is turned off due to the body effect when the third transistor T3 is to be turned off, It is possible to prevent a situation where the voltage Vref is unnecessarily transmitted to the second node N2 of the first transistor T1.

As a result, according to the D-type light-shielding pattern connection structure, the influence of the body effect can be reduced, thereby preventing the abnormal image driving due to the body effect and the abnormal screen abnormal phenomenon.

FIGS. 18 to 19 are diagrams for explaining the advantages of improving the sensing accuracy of the D-type light-shielding pattern connection structure in the OLED display 100 according to the present embodiments.

18, only one of the first light-shielding pattern LS1, the second light-shielding pattern LS2 and the third light-shielding pattern LS3 is connected to the reference voltage line RVL ).

Therefore, according to the D-type light-shielding pattern connecting structure, the parasitic capacitance Cp of the reference voltage line RVL can be made smaller than that of the C-type light-shielding pattern connecting structure.

The reduction of the parasitic capacitance Cp of the reference voltage line RVL can accurately measure the sensing voltage Vsense at the time of sensing using the reference voltage line RVL as the sensing line, It is possible.

FIG. 19 is a graph showing the sensing voltage achievement ratio (%) at which the sensing voltage Vsense reaches a desired sensing voltage (Desired Vsense) with respect to a case where the parasitic capacitance Cp is relatively large and a case where the parasitic capacitance Cp is relatively small.

Referring to FIG. 19, when the reference voltage line RVL has a large parasitic capacitance Cp at a specific sensing time (sensing time), the sensing voltage achieving rate is approximately 90%, but the reference voltage line RVL is large With a parasitic capacitance (Cp), it achieves a sensing voltage achievement rate of approximately 95%.

Therefore, it can be seen that a more accurate sensing voltage can be obtained as the parasitic capacitance Cp of the reference voltage line RVL becomes smaller.

Hereinafter, a driving method of the OLED display 100 related to the sensing driving described with reference to FIGS. 3 to 5 will be briefly described.

20 is a flowchart of a driving method of the OLED display 100 according to the present embodiments.

20, a driving method of an organic light emitting diode display 100 according to the present invention includes driving a data voltage Vdata to a first node N1 and a second node N2 of a first transistor T1, A second step S2020 of floating the second node N2 of the first transistor T1 and a second step S2020 of applying a reference voltage Vref to the first transistor T1, A third step S2030 of measuring the voltage of the second node N2 of the first transistor T1 through the reference voltage line RVL, and the like.

During the first, second and third steps S2010, S2020 and S2030, the first light-shielding pattern LS1 located below the first transistor T1 and the first light-shielding pattern LS1 located below the second transistor T2 And the third light-shielding pattern LS3 located below the third transistor T3 are connected to different points PV1, PV2 and PV3.

The parasitic capacitance Cp of the reference voltage line RVL can be reduced because the D type light-blocking pattern connection structure is designed by applying the driving method as described above, The accuracy of the sensing voltage obtained by measuring the voltage of the second node N2 can be improved.

FIG. 21 is a view schematically illustrating the structure of the organic light emitting display panel 110 and its subpixels SP according to the present embodiments.

Referring to FIG. 21, a plurality of subpixels SP are disposed in the organic light emitting display panel 110 according to the present invention. Each subpixel SP includes two transistors T1 and T2 and one May have a basic 2T1C structure with a capacitor C1 or a 3T1C structure with three transistors T1, T2 and T3 and a capacitor C1 and may be designed with other structures Do.

Referring to FIG. 21, each subpixel SP in the organic light emitting display panel 110 according to the present embodiments may have a 2T1C structure, a 3T1C structure, or another structure (e.g., 3T2C, 4T1C, 4T2C, 5T1C, A first transistor T1 for driving the organic light emitting diode OLED and a first transistor T1 for driving the organic light emitting diode OLED and a second transistor T1 for electrically connecting between the first node N1 and the data line DL of the first transistor T1. A second transistor T2 connected thereto, and the like.

The first light-shielding pattern LS1 may be positioned below the first transistor T1 and the second light-shielding pattern LS2 may be located below the second transistor T2.

The first bias voltage V1 and the second bias voltage V2 may be applied to the first light-blocking pattern LS1 and the second light-blocking pattern LS2.

Here, the first bias voltage V1 and the second bias voltage V2 may have different voltage values.

For example, the second bias voltage V2 applied to the second light-shielding pattern LS2 may be lower than the first bias voltage V1 applied to the first light-shielding pattern LS1.

According to this, since the second bias voltage V2 is lower than the first bias voltage V1, when the second transistor T2 is to be turned off, the second transistor T2 is turned on due to the body effect The situation in which the data voltage Vdata is unnecessarily transmitted to the first node N1 of the first transistor T1 can be greatly reduced.

Accordingly, the possibility of abnormal image driving and sensing driving can be greatly reduced, and image quality can be improved.

21, a subpixel SP designed with a structure having three or more transistors T1, T2, T3,... Such as 3T1C is connected to the second node N2 of the first transistor T1, And a third transistor T3 electrically connected between the reference voltage line RVL and the reference voltage line RVL.

In this case, the third light-shielding pattern LS3 may be positioned below the third transistor T3.

A third bias voltage V3 different from the first bias voltage V1 may be applied to the third light-emitting pattern LS3.

For example, the third bias voltage V3 may be lower than the first bias voltage V1.

According to this, since the third bias voltage V3 is lower than the first bias voltage V1, when the third transistor T3 must be turned off, the third transistor T3 is turned on due to the body effect The situation where the reference voltage Vref is unnecessarily transmitted to the second node N2 of the first transistor T1 can be greatly reduced.

Accordingly, the possibility of abnormal image driving and sensing driving can be greatly reduced, and image quality can be improved.

21, a first light-shielding pattern LS1 is located in a region of the first transistor T1 and a first light-shielding pattern LS1 is located in a region of the second transistor T2. The second light-shielding pattern LS2 is located on the third transistor T3 and the third light-shielding pattern LS3 is located on the area of the third transistor T3.

At this time, the first light-shielding pattern LS1, the second light-shielding pattern LS2, and the third light-shielding pattern LS3 are connected to different points PV1, PV2, and PV3.

The first light-shielding pattern LS1 is electrically connected to the source or drain node of the first transistor T1 and the second light-shielding pattern LS2 is electrically connected to the source or drain node of the second transistor T2. And the third light-shielding pattern LS3 may be electrically connected to a source node or a drain node of the third transistor T3.

Therefore, the first light-shielding pattern LS1, the second light-shielding pattern LS2, and the third light-shielding pattern LS3 corresponding to the first transistor T1, the second transistor T2 and the third transistor T3 are connected to each other By being dispersedly connected to the other points PV1, PV2, and PV3, the body effect and the influence thereof can be greatly reduced, and deterioration in sensing accuracy can be prevented.

According to the embodiments as described above, it is possible to reduce the variation in the device characteristics (for example, threshold voltage change) with respect to circuit elements (e.g., transistors) in the subpixel SP Emitting display panel 110, the OLED display 100, and a driving method thereof.

In addition, according to the present embodiments, the light-shielding pattern is disposed under each of the transistors T1, T2, and T3 in the sub-pixel SP to reduce variations in device characteristics of the transistors T1, T2, and T3, An OLED display panel 110 having a light-shielding pattern connection structure that can reduce the influence of a body effect that may be generated in each of the transistors T1, T2, and T3, an OLED display 100, A driving method can be provided.

In addition, according to the present embodiments, the light-shielding pattern is disposed under each of the transistors T1, T2, and T3 in the sub-pixel SP to reduce variations in device characteristics of the transistors T1, T2, and T3, The influence of the body effect which may be generated in each of the transistors T1, T2 and T3 can be reduced and the characteristic values for the circuit elements (for example, transistors, organic light emitting diodes, etc.) An organic light emitting diode (OLED) display panel 100, and a method of driving the organic light emitting display panel 100. The organic light emitting display device 100 may include a light-shielding pattern connection structure that can prevent degradation of sensing accuracy of light,

In addition, according to the present embodiments, a light-shielding pattern is placed under each of the transistors T1, T2, T3 in the subpixel SP, and the respective light-shielding patterns are connected to different points, An organic light emitting display panel 110 having a light-shielding pattern connection structure that reduces the influence of a body effect and can prevent degradation of sensing accuracy of characteristic values for circuit elements in each sub-pixel, ) And a driving method thereof.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. , Separation, substitution, and alteration of the invention will be apparent to those skilled in the art. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: organic light emitting display
110: organic light emitting display panel
120: Data driver
130: gate driver
140: controller
T1, T2, T3: First, second, and third transistors
LS1, LS2, and LS3: first, second, and third light-shielding patterns
PV1, PV2, PV3: first, second and third bias points
V1, V2, V3: first, second and third bias voltages

Claims (16)

An organic light emitting display panel in which a plurality of data lines and a plurality of gate lines are arranged and a plurality of subpixels are arranged;
A data driver for driving the plurality of data lines; And
And a gate driver for driving the plurality of gate lines,
Each of the plurality of sub-
A first transistor for driving the organic light emitting diode; a second transistor electrically connected between a first node of the first transistor and the data line; a second transistor electrically connected between the second node of the first transistor and the reference voltage line, And a storage capacitor electrically connected between a first node and a second node of the first transistor,
The first light-shielding pattern is located in the region of the first transistor, the second light-shielding pattern is located in the region of the second transistor, the third light-shielding pattern is located in the region of the third transistor,
The first light-shielding pattern, the second light-shielding pattern, and the third light-shielding pattern are electrically connected to a first bias point, a second bias point, and a third bias point,
Wherein the first bias point, the second bias point, and the third bias point are positions that are different from each other and are electrically disconnected from each other. The method according to claim 1,
Wherein the first bias point is a second node of the first transistor,
The second bias point is a drain node or a source node of the second transistor electrically connected to the data line, or is a point on the data line,
Wherein the third bias point is a drain node or a source node of the third transistor electrically connected to the reference voltage line, or is a point on the reference voltage line. The method according to claim 1,
The first bias point, the second bias point, and the third bias point are located at a source-drain layer,
Wherein the first light-shielding pattern, the second light-shielding pattern, and the third light-shielding pattern are located on a layer different from the source-drain layer. The method according to claim 1,
The first light-shielding pattern is a body node of the first transistor to which a first bias voltage is applied,
The second light-shielding pattern is a body node of the second transistor to which a second bias voltage is applied,
And the third light-shielding pattern is a body node of the third transistor to which a third bias voltage is applied. 5. The method of claim 4,
Wherein each of the second bias voltage and the third bias voltage is lower than the first bias voltage. The method according to claim 1,
Wherein only one of the first light-shielding pattern, the second light-shielding pattern, and the third light-shielding pattern is electrically connected to the reference voltage line. Organic light emitting diodes;
A first transistor for driving the organic light emitting diode;
A second transistor electrically coupled between a data line and a first node of the first transistor;
A third transistor electrically connected between a second node of the first transistor and a reference voltage line; And
And a storage capacitor electrically coupled between a first node and a second node of the first transistor,
The first light-shielding pattern is located in the region of the first transistor, the second light-shielding pattern is located in the region of the second transistor, the third light-shielding pattern is located in the region of the third transistor,
The first light-shielding pattern, the second light-shielding pattern, and the third light-shielding pattern are electrically connected to a first bias point, a second bias point, and a third bias point,
Wherein the first bias point, the second bias point, and the third bias point are positions that are different from each other and are electrically disconnected from each other. 8. The method of claim 7,
Wherein the first bias point is a second node of the first transistor,
The second bias point is a drain node or a source node of the second transistor, or a point on the data line,
Wherein the third bias point is a drain node or a source node of the third transistor or a point on the reference voltage line. 8. The method of claim 7,
The first light-shielding pattern is a body node of the first transistor to which a first bias voltage is applied,
The second light-shielding pattern is a body node of the second transistor to which a second bias voltage is applied,
And the third light-shielding pattern is a body node of the third transistor to which a third bias voltage is applied. 10. The method of claim 9,
Wherein each of the second bias voltage and the third bias voltage comprises:
Wherein the first bias voltage is lower than the first bias voltage. Organic light emitting diodes;
A first transistor for driving the organic light emitting diode; And
And a second transistor electrically coupled between a data line and a first node of the first transistor,
A first light-shielding pattern is disposed under the first transistor, a second light-shielding pattern is disposed under the second transistor,
And a first bias voltage and a second bias voltage different from each other are applied to the first light-shielding pattern and the second light-shielding pattern. 12. The method of claim 11,
And the second bias voltage applied to the second light-shielding pattern is lower than the first bias voltage applied to the first light-shielding pattern. 12. The method of claim 11,
Further comprising a third transistor electrically connected between a second node of the first transistor and a reference voltage line,
A third light-shielding pattern is disposed under the third transistor,
And a third bias voltage different from the first bias voltage is applied to the third light-shielding pattern. 14. The method of claim 13,
Wherein the third bias voltage is lower than the first bias voltage. A first transistor for driving the organic light emitting diode; a second transistor electrically connected between a first node of the first transistor and the data line; a second transistor electrically connected between the second node of the first transistor and the reference voltage line, And a storage capacitor electrically connected between a first node and a second node of the first transistor, the driving method comprising the steps of:
A first step of applying a data voltage and a reference voltage to a first node and a second node of the first transistor;
A second step of floating the second node of the first transistor; And
And a third step of measuring a voltage of a second node of the first transistor through the reference voltage line after a lapse of a predetermined time,
During the first step, the second step and the third step,
Wherein a first light-shielding pattern located below the first transistor, a second light-shielding pattern located below the second transistor, and a third light-shielding pattern located below the third transistor are connected to different points, . Organic light emitting diodes;
A first transistor for driving the organic light emitting diode;
A second transistor electrically coupled between a data line and a first node of the first transistor;
A third transistor electrically connected between a second node of the first transistor and a reference voltage line; And
And a storage capacitor electrically coupled between a first node and a second node of the first transistor,
The first light-shielding pattern is located in the region of the first transistor, the second light-shielding pattern is located in the region of the second transistor, the third light-shielding pattern is located in the region of the third transistor,
Wherein the first light-shielding pattern is electrically connected to a source node or a drain node of the first transistor, the second light-shielding pattern is electrically connected to a source node or a drain node of the second transistor, Wherein the third transistor is electrically connected to a source node or a drain node of the third transistor.

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