KR20170033627A - Semiconductor Integrated Circuit Device For Protecting Electrostatic Discharge - Google Patents

Semiconductor Integrated Circuit Device For Protecting Electrostatic Discharge Download PDF

Info

Publication number
KR20170033627A
KR20170033627A KR1020150131611A KR20150131611A KR20170033627A KR 20170033627 A KR20170033627 A KR 20170033627A KR 1020150131611 A KR1020150131611 A KR 1020150131611A KR 20150131611 A KR20150131611 A KR 20150131611A KR 20170033627 A KR20170033627 A KR 20170033627A
Authority
KR
South Korea
Prior art keywords
well
region
junction region
pad
conductivity type
Prior art date
Application number
KR1020150131611A
Other languages
Korean (ko)
Inventor
김종수
이동근
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020150131611A priority Critical patent/KR20170033627A/en
Publication of KR20170033627A publication Critical patent/KR20170033627A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66121—Multilayer diodes, e.g. PNPN diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66136—PN junction diodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The present technology relates to a semiconductor integrated circuit device including an ESD preventing unit. The integrated circuit device according to the present invention includes a peripheral circuit region on which power pads are arranged and the ESD preventing unit which is formed on the peripheral circuit region to overlap with the power pad and prevents the discharge of static electricity which is inputted with a reverse bias state, when the static electricity is inputted from the power pad. Accordingly, the present invention can improve area efficiency and prevent the static electricity.

Description

Technical Field [0001] The present invention relates to a semiconductor integrated circuit device having an electrostatic discharge protection device,

The present invention relates to a semiconductor integrated circuit device, and more particularly, to an electrostatic discharge (ESD) protection device of a semiconductor integrated circuit device.

ESD is a phenomenon in which a large current flows instantaneously due to a large voltage difference between objects when separated objects touch.

A semiconductor integrated circuit device generally includes an ESD protection circuit between an input / output pad and an internal circuit in order to prevent damage to an insulating film and a channel formed in an internal circuit by ESD.

The internal circuit damage due to ESD is caused by Joule heat due to high current and electric field in the junction region, device breakdown due to secondary breakdown due to high temperature, increase in integration degree and thinning of oxide film, Destruction of the oxide film due to the application, and destruction of the metal wiring caused by high current flow in the metal wiring and thinning of the wiring due to the temperature rise in the weak part. A device that is damaged by ESD may change its operating characteristics, increase the leakage current, and lower the ESD threshold voltage, resulting in loss of function as a device.

Accordingly, the ESD prevention circuit must be built in all the systems in which the semiconductor integrated circuit is mounted as well as the semiconductor integrated circuit. However, as the integration density of semiconductor integrated circuits increases, the area of the ESD prevention circuit also serves as an obstacle to increase the integration density.

An object of the present invention is to provide a semiconductor integrated circuit device having an ESD prevention part capable of improving area efficiency.

A semiconductor integrated circuit device according to an embodiment of the present invention includes: a peripheral circuit region in which power pads are arranged; And an ESD prevention part formed on the peripheral circuit area so as to overlap with the power pad, and configured to be in a reverse bias state when static electricity flows from the power pad, and to prevent a discharge of the introduced static electricity.

According to another aspect of the present invention, there is provided a semiconductor integrated circuit device including a semiconductor substrate having a bank region and a peripheral region defined therein, a first well of a first conductivity type formed in the semiconductor substrate of the peripheral region, A first junction region of the second conductivity type formed on the first well surface, a second junction region of the second conductivity type formed on the first well surface, a second junction region of the second conductivity type formed on the second well surface, A first power pad formed to be electrically connected to the first junction region and overlapped with the first junction region, and a second power pad formed to be electrically connected to the second junction region, And a second power pad formed to overlap with the second junction region.

According to the present invention, even if an NP diode is constructed under the VDD pad and a PN diode is formed under the VSS so that overshooting static electricity (+) and undershoot static electricity (-) are transmitted through the power pads, Lt; / RTI >

In addition, the NP diode (N junction region) and the PN diode (P junction region) for ESD prevention are located at the lower ends of the VDD power pad and the VSS power pad, respectively. As described above, the ESD prevention circuit is formed in the peripheral circuit area less affected by the area, thereby improving the integration density.

In addition, when the VDD power pad and the VSS power pad are disposed adjacent to each other, the NPNP diode is constructed between the VDD power pad and the VSS power pad, so that the static electricity can be more stably shielded.

1 is a schematic plan view of a semiconductor integrated circuit device according to an embodiment of the present invention.
FIG. 2 is an enlarged plan view of the pads of FIG. 1. FIG.
3 is a cross-sectional view taken along line III-III 'of FIG.
4 is a cross-sectional view taken along the line IV-IV 'in Fig.
5 is a plan view of power pads of a semiconductor integrated circuit device according to another embodiment of the present invention.
6 is a cross-sectional view taken along the line VI-VI 'of FIG.
7 is a schematic isometric view of a mobile computing platform using an IC according to embodiments of the present invention.
8 is a functional block diagram of a semiconductor system according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The dimensions and relative sizes of layers and regions in the figures may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout the specification.

Referring to FIG. 1, the semiconductor integrated circuit device 100 may include a bank circuit portion 110 and a peripheral circuit portion 120.

The bank circuit portion 110 may include an up bank circuit portion 110u and a down bank circuit portion 110d. The up-bank circuit portion 110u and the down-bank circuit portion 110d may each include a plurality of banks.

The peripheral circuit section 120 may be located between the up-bank circuit section 110u and the down-bank circuit section 110d. The peripheral circuitry 120 may include circuits (not shown) and a plurality of pads 121a, 121b, 123, 125 for controlling the banks. The plurality of pads 121a, 121b, 123 and 125 may include, for example, power pads 121a and 121b, signal pads 123 and probe pads 125, The signal pads 123 and the probe pads 125 may be arranged at predetermined intervals along the edges of the peripheral circuit unit 120 facing the bank circuit units 110u and 110d. At this time, since the peripheral circuit portion 120 has a lower integrated density than the bank circuit portion 110, the pads 121a, 121b, 123, and 125 may be spaced apart with sufficient spacing.

Here, the power pad 121a may be a pad (VDD pad) provided with VDD, and the power pad 121b may be a pad (hereinafter, VSS pad) provided with VSS.

Referring to FIG. 2, impurity regions 210 and 215 (hereinafter, junction regions) for preventing static electricity are formed under the VDD pad 121a and the VSS pad 121b of the present embodiment.

More specifically, as shown in FIGS. 2 and 3, a first conductivity type, for example, a P-well 205 is formed in the semiconductor substrate 200. A junction region 210 of a second conductivity type, for example, a high concentration N-type, is formed on the upper surface of the P-well 205. The VDD pad 121a is disposed above the high concentration n-type junction region 210. [ Thereby, an NP junction composed of the high-concentration N-type junction region 210 and the P-well 205 is formed under the VDD pad 121a.

At this time, (+) charged static electricity can be introduced through the VDD pad 121a to which a positive voltage of a certain level is applied. Such static electricity may be generated during use of the device, or may be artificially injected for static testing. In this case, since a reverse bias state is established between the N-type junction region 210 and the P-well 205, no current flows between the NP junctions. That is, a depletion capacitor is formed between the N-type junction region 210 and the P-well 205 to block the introduction of static electricity into the semiconductor substrate 200 (case I).

On the other hand, if a negative charge is provided through the VDD pad 121a, the NP junction may be in a forward bias state to discharge negative charge (Case II). That is, since a positive voltage of a certain level is inputted to the VDD pad 121a, even if (-) static electricity is inputted, the VDD pad 121a is offset from the VDD level, and discharge is possible without affecting the circuit element.

2 and 4, a P-well 205 is formed in the semiconductor substrate 200. The P- An N well 208 is formed in the P well 205 and a high concentration P junction region 215 is formed on the surface of the N well 208. [ The VSS pad 121b is disposed above the high-concentration P-type junction region 215. [ Thereby, a PN junction composed of the high-concentration P-type junction region 215 and the N-well 208 is formed under the VSS pad 121b.

At this time, a negative bias is applied between the P-type junction region 215 and the N-well 208 when negative (-) charged static electricity flows through the VSS pad 121b to which a negative voltage of a certain level is applied. So that no current flows between the PN junctions. In other words, a depletion capacitor is formed between the P-type junction region 215 and the N-well 208 to block the flow of the (-) static electricity into the semiconductor substrate 200 (case I).

On the other hand, when a positive charge is provided through the VSS pad 121b, the PN junction becomes a forward bias state and can discharge the positive charge (Case II). Since a negative voltage of a certain level is inputted to the VSS pad 121b, even if (+) static electricity is inputted, the VSS pad 121b is offset from the VSS level and can be easily discharged without affecting the circuit element.

5 and 6, when the VDD pad 121a and the VSS 121b are disposed adjacent to each other, an NPNP diode may be formed between the VDD pad 121a and the VSS pad 121b .

As shown in FIG. 6, a deep P-well 205 is formed on the semiconductor substrate 200. An N well 208 is formed in a region where the VSS pad 121b is to be formed in the P well 205 in a known manner.

Then, a high-concentration N-type junction region 210 is formed in the P-well 205 region and a high-concentration P-type junction region 215 is formed in the N-well 208 region. The VDD pad 121a and the VSS pad 121b are formed by using interconnection lines (not shown) on the high-concentration N-type junction region 210 and the high-concentration P-type junction region 215, respectively.

As described above, when the VDD pad 121a and the VSS pad 121b are disposed adjacent to each other, the high-concentration N-type junction region 210, the P-well 205, the N-well 208 and the high- 215 are connected in series with each other.

When the (+) charged static electricity flows through the VDD pad 121a, the NP junction between the N-type junction region 210 and the P-well 205 is reverse biased and the flow of static electricity is blocked .

On the other hand, when negative (-) charged static electricity flows through the VSS pad 121b, the PN junction between the P-type junction region 215 and the N-well 208 becomes a reverse bias state, Is blocked.

According to the present invention, an NP diode is constructed under the VDD pad and a PN diode is formed under the VSS so that even if at least one of the overshoot static electricity (+) and the undershoot static electricity (-) is transmitted through the power pads , Static electricity can be blocked.

In addition, the NP diode (N junction region) and the PN diode (P junction region) for ESD prevention are located at the lower ends of the VDD power pad and the VSS power pad, respectively. As described above, the ESD prevention circuit is formed in the peripheral circuit area less affected by the area, thereby improving the integration density.

In addition, when the VDD power pad and the VSS power pad are disposed adjacent to each other, the NPNP diode is constructed between the VDD power pad and the VSS power pad, so that the static electricity can be more stably shielded.

7 is a schematic isometric view of a mobile computing platform 700 using an IC in accordance with embodiments of the present invention. Mobile computing platform 700 may be any portable device configured for electronic data display, electronic data processing, and wireless electronic data transmission, respectively. For example, the mobile computing platform 700 may be any of a tablet, a smart phone, a laptop computer, etc. In an exemplary embodiment, a display screen 705 that is a touch screen (capacitive, inductive, resistive, etc.) , A chip-level (SoC) or package-level integration system 710, and a battery 713.

The integration system 710 is further illustrated in an enlarged view 720. In an exemplary embodiment, the packaged device 777 includes at least one memory chip (e.g., RAM), and / or at least one having a core circuit coupled to an I / O and an ESD protection device according to this embodiment (For example, a multi-core microprocessor and / or a graphics processor), and a core circuit in which the I / O and the ESD protection circuit of this embodiment are combined is disposed therebetween. The ESD protection circuit of the present embodiment may be configured to form a junction region under the power pad to block the current when static electricity flows. The packaged device 777 may include a power management integrated circuit (PMIC) 715, a broadband wireless (RF) transmitter and / or a receiver (e.g., including a digital baseband, Substrate, or interposer 260, along with one or more of a radio frequency (RF) integrated circuit (RFIC) 725 and their controller 711. The integrated circuit 700 further includes a low noise amplifier on the receive path. Lt; / RTI > As illustrated, the interfaces of each of these ICs include the ESD protection circuit of this embodiment. In other embodiments, the circuitry utilized in the packaged device 777 may also include the ESD protection circuit of the present embodiment described above.

Functionally, the PMIC 715 has an output that performs battery power adjustment, DC-to-DC conversion, etc., to provide an input coupled to the battery 713 and a current supply to all other function modules. As further illustrated, in the exemplary embodiment, the RFIC 725 may be a Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE) Including but not limited to 3G, 4G, 5G or above, as well as derivatives thereof, as well as derivatives of HSPA +, HSDPA +, HSUPA +, EDGE, GSM, GPRS, CDMA, TDMA, DECT, And has an output coupled to the antenna to provide for implementation of any of the wireless standards or protocols. In alternate implementations, each of these board-level modules may be integrated on a separate ICs coupled to the package substrate of the packaged device 777 or in a single IC (SoC) coupled to the package substrate of the packaged device 777 .

FIG. 8 is a functional block diagram of a computing device 1000 in accordance with an embodiment of the present invention. The computing device 1000 may be found within, for example, a mobile computing platform 700 and may be, but is not limited to, a processor 1004 (e.g., an application processor) and at least one communication chip 1006 And further includes a board 1002 hosting a plurality of components. In embodiments, at least one of the processor 1004 and the communication chip 1006 is applied with the ESD protection circuit portion of the present embodiment. The processor 1004 is physically and electrically coupled to the board 1002. Processor 1004 includes an integrated circuit die packaged within processor 1004. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory for converting electronic data into registers and / or other electronic data that may be stored in memory have.

In some implementations, at least one communication chip 1006 is also physically and electrically coupled to the board 1002. In other implementations, the communications chip 1006 is part of the processor 1004. Depending on those applications, the computing device 1000 may include other components that may or may not be physically and electrically coupled to the board 1002. These other components may include volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processor, digital signal processor, crypto processor, chipset, antenna, touch screen display, (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and (hard disk drives, solid state drives (SSDs), compact discs (CDs), digital But are not limited to, mass storage devices (such as multi-function disks (DVD), etc.).

At least one of the communication chips 1006 may enable wireless communication for transmission of data to and from the computing device 1000. The term " wireless "and its derivatives are used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that are capable of communicating data through the use of modulated electromagnetic radiation through a non- Lt; / RTI > This term does not imply that the associated devices do not include any wires, but in some embodiments, the associated devices may include any wires. The communications chip 1006 may implement any of a number of wireless standards or protocols, including but not limited to those described elsewhere herein. The computing device 1000 may include a plurality of communication chips 1006. [ For example, the first communication chip 1006 may be dedicated to short-range wireless communication such as Wi-Fi and Bluetooth and the second communication chip 1006 may be dedicated to GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev- DO and the like. Each of the above-mentioned elements can be applied to the ESD circuit portion of the present embodiment.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but variations and modifications may be made without departing from the scope of the present invention. Do.

121a: VDD pad 121b: VSS pad
210: N-type junction region 215: P-type junction region

Claims (13)

A peripheral circuit region in which the power pads are arranged; And
And an ESD prevention part formed on the peripheral circuit area so as to overlap with the power pad and configured to be in a reverse bias state when static electricity flows from the power pad to cut off the discharge of the static electricity flowing into the semiconductor integrated circuit device. The method according to claim 1,
Wherein the power pad includes a VDD pad and a VSS pad. 3. The method of claim 2,
Wherein the ESD prevention portion comprises:
A first well of a first conductivity type formed in the peripheral circuit region corresponding to the VDD pad; And
And a first junction region of a second conductivity type opposite to the first conductivity type formed on the surface of the first well. The method of claim 3,
Wherein the first well is a P well,
Wherein the first junction region is an N-type impurity region. The method of claim 3,
Wherein the ESD prevention portion comprises:
A second well of the second conductivity type formed in the peripheral circuit region corresponding to the VSS pad; And
And a second junction region of the first conductivity type formed on the surface of the second well. 6. The method of claim 5,
The second well is an N well,
And the second junction region is a P-type impurity region. 6. The method of claim 5,
And the second well is formed in the first well in the peripheral circuit region. A semiconductor substrate having a bank region and a peripheral region defined therein;
A first well of a first conductivity type formed in the semiconductor substrate of the peripheral region;
A second well of a second conductivity type opposite to the first conductivity type formed in a predetermined portion of the first well;
A first junction region of the second conductivity type formed on the surface of the first well;
A second junction region of the first conductivity type formed on the surface of the second well;
A first power pad formed to be electrically connected to the first junction region, the first power pad being formed to overlap with the first junction region; And
And a second power pad formed to be electrically connected to the second junction region and overlapping with the second junction region. 9. The method of claim 8,
The first power pad is a VDD pad,
And the second power pad is a VSS pad. 9. The method of claim 8,
Wherein the first conductive type is a P type and the second conductive type is an N type. 9. The method of claim 8,
The conductivity type of the first junction region and the conductivity of the first well are determined so as to be in a reverse bias state between the first junction region and the first well when static electricity flows through the first power pad. 9. The method of claim 8,
The conductivity type of the first junction region and the conductivity of the first well are determined so as to be in a reverse bias state between the second junction region and the second well when static electricity flows through the second power pad. 9. The method of claim 8,
The first well region, the second well region, and the second junction region between the first power pad and the second power pad, the two diodes having mutually opposite junction structures are connected in series The impurity type of the first junction region, the first well, the second well, and the second junction region is determined so that a connected form can be established.
KR1020150131611A 2015-09-17 2015-09-17 Semiconductor Integrated Circuit Device For Protecting Electrostatic Discharge KR20170033627A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020150131611A KR20170033627A (en) 2015-09-17 2015-09-17 Semiconductor Integrated Circuit Device For Protecting Electrostatic Discharge

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020150131611A KR20170033627A (en) 2015-09-17 2015-09-17 Semiconductor Integrated Circuit Device For Protecting Electrostatic Discharge

Publications (1)

Publication Number Publication Date
KR20170033627A true KR20170033627A (en) 2017-03-27

Family

ID=58496792

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020150131611A KR20170033627A (en) 2015-09-17 2015-09-17 Semiconductor Integrated Circuit Device For Protecting Electrostatic Discharge

Country Status (1)

Country Link
KR (1) KR20170033627A (en)

Similar Documents

Publication Publication Date Title
US10103542B2 (en) Extended drain non-planar MOSFETs for electrostatic discharge (ESD) protection
KR102435672B1 (en) Electrostatic discharge (ESD) protection circuit and integrated circuit including the same
US9318479B2 (en) Electrostatic discharge (ESD) silicon controlled rectifier (SCR) with lateral gated section
US8217462B2 (en) Transient voltage suppressors
US8665571B2 (en) Apparatus and method for integrated circuit protection
US8368116B2 (en) Apparatus and method for protecting electronic circuits
US8680620B2 (en) Bi-directional blocking voltage protection devices and methods of forming the same
US9799641B2 (en) Electrostatic discharge protection device and electronic device having the same
US9343458B2 (en) Isolation structure for ESD device
US20170271322A1 (en) Area-efficient and robust electrostatic discharge circuit
JP5519308B2 (en) Semiconductor integrated circuit and data processing system
US20090072315A1 (en) Semiconductor Manufacturing Process Charge Protection Circuits
CN111668207B (en) Distributed electrical overstress protection for high density and high data rate communication applications
US20120176708A1 (en) Esd protection devices and methods for forming esd protection devices
US20120176709A1 (en) Esd protection devices and methods for forming esd protection devices
JP5603488B2 (en) Apparatus and method for integrated circuit protection
KR101890981B1 (en) Apparatuses and method for over-voltage event protection
EP3503184A1 (en) Device and method for electrostatic discharge (esd) protection
KR20170033627A (en) Semiconductor Integrated Circuit Device For Protecting Electrostatic Discharge
US9019672B2 (en) Chip with electrostatic discharge protection function
US8605396B2 (en) ESD protection devices and methods for forming ESD protection devices
US20130044396A1 (en) Electrostatic discharge (esd) protection element and esd circuit thereof
KR101679347B1 (en) Semiconductor device
US7550820B2 (en) Reverse-biased PN diode decoupling capacitor
US20130050884A1 (en) Electrostatic discharge (esd) protection element and esd circuit thereof