KR20160093387A - Integrated DSP with CPU of Digital RF Repeater - Google Patents

Abstract

The present invention relates to a digital RF repeater comprising a control unit-combined DSP device, which receives a base station signal from a donor ANT, which performs low-noise amplification of the received RF signal by using an LNA, and which converts the RF signal into an intermediate frequency (IF) in an RF down converter. The RF down converter performs frequency conversion by using a local signal generated in an RF IC, converts the IF signal into a digital signal by using an AD converter, performs DSP processing in an FPGA, performs RF conversion of a DSP-processed digital I/Q signal by using the RF IC, amplifies the signal in a power AMP, and outputs the amplified signal to a service ANT via a duplex filter. The RF IC connects a signal, desirably decreased before final output by using a CPL, to a feedback (F/B) path of the RF IC by feeding back the signal, converts two signals, adapted to have an identical frequency with and without 90-degree phase transition, in a time domain into signals in a frequency domain via an FFT block by performing the DSP processing, transmits data, obtained by the conversion, to an MCU, and performs a waveform monitoring function by displaying the data on a GUI. The FPGA comprises: a DSP block which performs the DSP processing; and a control unit which processes an access signal via the RF IC and a user interface, and performs signal processing adapted to perform the waveform monitoring function in conjunction with the DSP block.

Description

[0001] The present invention relates to a digital RF repeater having an integrated D / A device,

[0001] The present invention relates to a digital RF repeater having a controller integrated diesemap device, and more particularly, to a digital RF repeater having a controller integrated diese device in which a conventional control unit (CPU) This is a new type of control unit integrated DESSU device that can reduce the size of the product by reducing the number of chips for the control unit and can respond to customer's needs by changing the software structure without requiring any change according to the application (product) It is about the RF repeater.

Currently, digital RF repeaters are being used in repeater applications.

1 is a block diagram schematically showing a conventional digital RF repeater.

As shown in Fig. 1, a base station signal is received from a donor ANT. The input RF signal is low-noise amplified using LNA, then converted from RF down-converter to intermediate frequency (IF). At this time, a separate oscillator (Oscillator) and PLL (PLL) are used to generate the local signal for the intermediate frequency conversion.

At this time, the IF frequency is generally several tens MHz to 250 MHz.

The IF signal is converted into a digital signal using an AD converter. Then, the DSP performs DSP processing on the FPGA. Then convert it to IF frequency using DA converter. At this time, the IF frequency is the same as the frequency of the down-converter. And then converted from RF up-converter to RF. At this time, the RF frequency is the same as the LNA input frequency.

The power amplifier then amplifies the signal. Then output it to the service ANT through the Duplex Filter.

Such a conventional digital RF repeater has a problem in that it requires a lot of parts such as an oscillator and a PLL and that it requires a lot of manufacturing cost, and has a problem in that it is difficult to manufacture due to the complicated circuit structure.

In addition, there is a problem that a filter for removing an image signal must be separately used at the output of the DA converter.

To solve this problem, the applicant of the present invention has proposed a technique as shown in Fig. 2 for an optical repeater using a device including a DSS module implemented by an RF IC and an FPGA.

Meanwhile, in a conventional optical repeater, a control chip composed of a separate CPU is implemented in a separate PCB device (not shown), and accordingly, there is a need to change the configuration of the control unit into an integral type in order to control the performance of the optical repeater.

[Prior Art Literature]

Korean Patent Registration No. 10-1120749 (registered on Feb. 20, 2012, many heterogeneous / DSS bus alignment systems)

SUMMARY OF THE INVENTION It is an object of the present invention to provide a digital RF repeater having a control unit integrated type Desef apparatus of a new type capable of responding to a request of a customer by changing a software structure without requiring a change according to an application (product).

According to a preferred embodiment of the present invention,

A digital RF repeater having a control unit integrated D / A unit for receiving a base station signal from a donor ANT, low noise amplifying the input RF signal using an LNA and converting the RF signal into an intermediate frequency (IF)

The RF down-converter performs frequency conversion using the local signal generated by the RF IC,

The IF signal is converted into a digital signal using an AD converter,

Perform DSP processing on the FPGA,

The DSP-processed digital I / Q signal is RF-converted using an RF IC,

Power AMP amplifies the signal and outputs it through the duplex filter as service ANT,

The RF IC feeds back a predetermined attenuated signal through the CPL to the F / B path of the RFIC before final output,

Thereafter, the DSP process is performed to convert the two signals having the same frequency / 90 degrees phase shifted into signals in the frequency domain through the FFT block, transmit the converted data to the MCU, display them on the GUI, Perform monitoring functions,

The FPGA

A diese block for performing DSP processing,

And a controller for processing an access signal through an RF IC and a user interface and performing a signal processing for performing a waveform monitoring function in connection with the DESPE block, wherein the digital RF repeater includes a controller integrated Desep device, / RTI >

The control unit may include a flash controller (NOR, NAND, SRAM, Quad SPI), a multiport DRAM controller (DDR2, DDR3L, DDR2), a processing input / output mux, various modules (SPI, I2C, , DMA). The central core control unit includes various engines, a cache, a memory, and a controller. The central core controller is connected to the diespe block through an interconnect. The interconnect is responsible for connection to various devices. (RSA) is configured to perform encryption, and the user can access the control unit through the input / output mux of the control unit through the user interface, and the RF IC can access the control unit through the input / output mux.

As described above, according to the digital AR repeater including the control unit integrated type D / A device according to the present invention, the interface between the CPU and the DSP block is implemented inside the chip by implementing a CPU and a DSP block in one chip, It is possible to reduce development time and development risk (RISK) by eliminating data distortion and errors due to lines.

In addition, by reducing the number of chips, it is possible to reduce the size of the product, to change the software structure without changing according to the application (product), and to respond quickly according to the demand of the customer.

Figure 1 schematically illustrates a digital RF repeater in accordance with the prior art;
2 is a schematic diagram of a digital RF repeater in accordance with the present invention;
FIG. 3 is a detailed block diagram showing the DSP block portion of FIG. 2 in detail.
FIGS. 4 to 8 are waveform graphs of captured data of the ADC in FIG.
9 is a block diagram schematically showing a control unit integrated type D / A unit for a digital RF receiver according to the present invention.

Hereinafter, a digital RF repeater according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a schematic view of a digital RF repeater according to the present invention, and FIG. 3 is a detailed block diagram of FIG.

Referring to FIG. 2, a base station signal is received from a donor ANT. The input RF signal is low-noise amplified using LNA, then converted from RF down-converter to intermediate frequency (IF). The frequency conversion is performed using the local signal generated by the RF IC. At this time, the IF frequency is generally several tens MHz to 250 MHz.

The IF signal is converted into a digital signal using an AD converter. And then performs DSP processing in an FPGA (representing a DSP or DSP block). DSP-processed digital I / Q signals are RF-converted using RF ICs. At this time, the RF frequency is the same as the LNA input frequency.

The power amplifier then amplifies the signal. Then output it to the service ANT through the Duplex Filter.

According to the digital RF repeater of the present invention, since a local signal is generated in an RF IC, it is not necessary to use a separate oscillator and a PLL (Phase Locked Loop), thereby reducing the number of parts used, reducing the circuit size, Simplification of wiring in PCB (Printed Circuit Board) design and signal crosstalk and interference in local signal line are minimized.

In addition, since the output of the RF IC is RF, a separate RF up-converter circuit configuration is not required, which simplifies the circuit and thereby reduces the circuit size.

Also, it is not necessary to separately use a filter for image signal attenuation unlike the conventional method in which a filter for eliminating image signals is used separately at the output of the DA converter.

Referring to FIG. 3, an RF signal converted from RF to IF through a down-converter is applied to the ADC (c) and is generated as a digital signal by the ADC clk. The generated digital signal is stored in the DSP block in the FIFO (d). The data stored by the ADC clk is outputted to the internal clock of the DSP module 60 in order to operate as a DSP internal clock. The DDC (Digital Down Converter) block is a block that generates the NCO (f) frequency to down-convert the ADC data to the frequency for filtering in the DSP, and multiplies the input signal by the frequency generated from the NCO.

The frequencies generated in the NCO (f) are two identical frequencies and produce a quadrature signal whose phase is shifted by 90 degrees.

The signal passed through the DDC block has the same frequency (0 Hz), and the 90-degree phase shifted signal is passed to the decimation (g) step.

The sampling rate of the signal applied to the decimation (g) is the same as the rate output from the FIFO (d).

Decimation (g) is used to lower the sampling rate. When the sampling rate is high, many coefficients can not be used in the next Fir filter (h) stage, which affects filter rejection.

By decimating the drive clock of the Fir, it is possible to implement a sharper, sharp filter. Also, it is possible to use less FPGA capacity.

After removing the unwanted signal in addition to the modulated signal down to 0 Hz, the user passes through a gain block (h), which can raise and lower the gain as desired.

It can control the gain by receiving the control value from the MCU through SPI communication, which determines the coverage of the repeater service.

And passes the interpolation / FIR to recover the decimated signal to its original sampling rate.

And the signal that has been gain-converted by the user is further up-converted through a DUC (Digital Up Converter).

The converted signal is added to the signal of the same frequency and 90 degrees phase shifted through the adder (n), and the signal is sent to DA (o).

Converted into an RF signal through a Mixer (p) built in the RFIC 50, and wirelessly transmitted through the PA (r).

(F / B) (s) through the CPL (q) before the final output is connected to the F / B path of the RFIC.

A through h pass the same routine.

Two signals of the same frequency / 90 degrees phase shifted are converted into signals of the time-> frequency domain through the FFT block (k).

This data can be transmitted to the MCU and displayed on the GUI to configure the waveform monitoring function.

FIGS. 4 to 8 are waveform graphs of captured data of the ADC in FIG.

Figure 4 is a waveform graph captured by Fs / 2 as ADC data.

5 is a waveform graph that captures ADCed data that is reversed by Fs / 2 in FIG.

FIG. 6 is a waveform graph showing a state in which the same signal generated in the Fs / 2 period goes down to the baseband when the ADC data is lowered to the base band through the NCO.

FIGS. 7 and 8 are waveform graphs showing a state in which only a desired signal remains after filtering a signal down to the baseband.

Referring to FIG. 9, a digital RF repeater having a control unit integrated D / A unit according to the present invention includes an FPGA (i.e., a module 60) and a control unit (i.e., a CPU and a chip) (I.e., a control unit and a D / A unit-integrated FPGA).

The RF IC 50 is the same as that described above with reference to FIG. 3, and therefore will not be described.

Reference numeral 110 denotes a user interface device.

Reference numeral 120 denotes a control unit, i.e., SoC. The control unit 120 is generally called a processing system and includes a flash controller (NOR, NAND, SRAM, Quad SPI), a multiport DRAM controller (DDR2, DDR3L, DDR2), a processing input / output mux, , UART, GPIO, and DMA). The central core controller 1210 includes various engines, a cache, a memory, and a controller.

Diese block 130 via an interconnect. Interconnect is responsible for connecting to various devices. A security processing unit (RSA) is configured between the D / A block 130 and the control unit 120 to perform encryption and the like.

The user can access the control unit 120 through the processor input / output mux via the user interface. The RFIC can access the control unit 120 through the input / output mux.

Referring to FIG. 10, the control unit 120 operating in conjunction with the DESPE block performs a Linux driver and OS (operating system) porting in the Soc block to complete the operation of the basic OS level, and then programs the application. The main program controls the status of the control / status in Raw Data and DSP block of waveform monitoring in real time and check the status (Amplitude / Channel Power / Filter Coefficient / Gain Control / DDS Freq). That is, since the controller 120 is integrated with the DESPE block 130, various control elements for the waveform monitoring function to be implemented by the present invention can be programmed in the controller 120.

According to the digital AR repeater having the control unit integrated D / A device according to the present invention, the interface between the CPU and the DSP block is implemented in a chip by implementing a CPU and a DSP block in one chip, and data distortion And errors can be eliminated to reduce the development period and development risk (RISK).

In addition, by reducing the number of chips, it is possible to reduce the size of the product, to change the software structure without changing according to the application (product), and to respond quickly according to the demand of the customer.

50: RFIC
110: User interface
120:
130: Dice Block

Claims (2)

A digital RF repeater having a control unit integrated D / A unit for receiving a base station signal from a donor ANT, low noise amplifying the input RF signal using an LNA, and converting the RF signal into an intermediate frequency (IF)
The RF down-converter performs frequency conversion using the local signal generated by the RF IC,
The IF signal is converted into a digital signal using an AD converter,
Perform DSP processing on the FPGA,
The DSP-processed digital I / Q signal is RF-converted using an RF IC,
Power AMP amplifies the signal and outputs it through the duplex filter as service ANT,
The RF IC feeds back a predetermined attenuated signal through the CPL to the F / B path of the RFIC before final output,
Thereafter, the DSP process is performed to convert the two signals having the same frequency / 90 degrees phase shifted into signals in the frequency domain through the FFT block, transmit the converted data to the MCU, display them on the GUI, Perform monitoring functions,
The FPGA
A diese block for performing DSP processing,
And a controller for processing the access signal through the RF IC and the user interface and performing signal processing for performing the waveform monitoring function in conjunction with the DESPE block.
2. The system as claimed in claim 1, wherein the controller comprises a flash controller (NOR, NAND, SRAM, Quad SPI), a multiport DRAM controller (DDR2, DDR3L, DDR2), a processing input / output mux, , GPIO, and DMA). The central core controller includes various engines, a cache, a memory, and a controller. The central core controller is connected to the D / A block through an interconnect. The interconnect is responsible for connection to various devices. A security processing unit (RSA) is configured between the control units to perform encryption. The user can access the control unit through the input / output mux of the control unit through the user interface and access the control unit through the input / output mux. A digital RF repeater having a control unit integrated type diskette device.

Images