KR20150087683A - Embedded printed circuit substrate - Google Patents

Embedded printed circuit substrate Download PDF

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Publication number
KR20150087683A
KR20150087683A KR1020140007906A KR20140007906A KR20150087683A KR 20150087683 A KR20150087683 A KR 20150087683A KR 1020140007906 A KR1020140007906 A KR 1020140007906A KR 20140007906 A KR20140007906 A KR 20140007906A KR 20150087683 A KR20150087683 A KR 20150087683A
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South Korea
Prior art keywords
insulating layer
printed circuit
sensor
circuit board
cavity
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KR1020140007906A
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Korean (ko)
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KR102167597B1 (en
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안윤호
이상명
정원석
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엘지이노텍 주식회사
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Priority to KR1020140007906A priority Critical patent/KR102167597B1/en
Priority to PCT/KR2015/000645 priority patent/WO2015111922A1/en
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
    • G01J5/02—Constructional details
    • G01J5/0225—Shape of the cavity itself or of elements contained in or suspended over the cavity
    • G01J5/024—Special manufacturing steps or sacrificial layers or layer structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06—Thermal details
    • H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09881—Coating only between conductors, i.e. flush with the conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0502—Patterning and lithography
    • H05K2203/0514—Photodevelopable thick film, e.g. conductive or insulating paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H05K2203/1469—Circuit made after mounting or encapsulation of the components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

The present invention relates to an embedded printed circuit board, which comprises: an insulation substrate which includes a cavity; an element which is placed in the cavity; and an insulation layer which is formed of a heat and ultraviolet ray curable material on the insulation substrate, and includes an opening unit for exposing part of the element. Therefore, the embedded printed circuit board can form the opening unit without damage to the printed circuit board or the element, can prevent exfoliation of the insulation layer from the element, and can provide a minimized defect rate and high reliability.

Description

임베디드 인쇄회로기판{EMBEDDED PRINTED CIRCUIT SUBSTRATE}EMBEDDED PRINTED CIRCUIT SUBSTRATE < RTI ID = 0.0 >

본 발명의 실시예는 임베디드 인쇄회로기판에 관한 것이다.An embodiment of the present invention relates to an embedded printed circuit board.

최근에는 휴대 단말에 다양한 기능이 추가되고 있으며, 그에 따라 휴대 단말에 다양한 센서 소자가 추가되고 있다.In recent years, various functions have been added to portable terminals, and various sensor elements have been added to portable terminals accordingly.

휴대 단말에 포함되는 인쇄회로기판(PCB; Printed Circuit Board)에 센서 소자를 실장 시에는 상기 인쇄회로기판의 제한된 면적으로 인하여 새로운 센서 소자의 추가가 어려운 실정이다.When a sensor element is mounted on a printed circuit board (PCB) included in a mobile terminal, it is difficult to add a new sensor element due to the limited area of the printed circuit board.

한편, 인쇄회로기판(PCB; Printed Circuit Board)은 전기 절연성 기판에 전도성 재료로 인쇄회로를 인쇄한 것으로, 여러 종류의 많은 소자를 평판 위에 밀집 탑재시키기 위하여 각 소자의 장착 위치를 확정하고, 소자를 연결하는 회로 라인을 평판 표면에 인쇄하여 고정하는 구조로 구성된다.On the other hand, a printed circuit board (PCB) is a printed circuit printed on an electrically insulating substrate with a conductive material. In order to densely mount many kinds of devices on a flat plate, the mounting position of each device is determined, And the circuit line to be connected is printed and fixed on the surface of the flat plate.

종래에는 절연 기판 내에 캐비티를 형성하고 캐비티 내에 소자를 실장하여 임베디드 인쇄회로기판을 구성하므로 소자가 외부로 노출되지 않는다.Conventionally, a cavity is formed in an insulating substrate and an element is mounted in a cavity to constitute an embedded printed circuit board, so that the device is not exposed to the outside.

따라서, 상기 소자가 센서 소자인 경우에는 상기 센서 소자가 노출되는 개구부를 형성하기 위하여 레이저 드릴을 이용하였으나, 상기 레이저 드릴에 의하여 인쇄회로기판 또는 소자가 손상되는 문제점이 발생하였다.Accordingly, when the element is a sensor element, a laser drill is used to form an opening through which the sensor element is exposed. However, the laser drill may damage the printed circuit board or the element.

본 발명은 전술한 문제를 해결하기 위해 안출된 것으로서, 인쇄회로기판에 임베디드되는 소자의 일부를 노출하는 개구부가 형성되는 절연층을 열 및 자외선 경화 특징이 있는 감광성 자재를 사용하여, 인쇄회로기판 또는 소자의 손상 없이 개구부의 형성이 보다 용이하도록 하고자 한다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a method of manufacturing a printed circuit board or a printed circuit board using the photosensitive material having heat and ultraviolet curing characteristics, So that it is easier to form openings without damaging the device.

또한, 본 발명은 소자를 둘러싸는 절연층을 소자의 열팽창률과 유사한 재료를 사용하여, 소자로부터 절연층이 박리되지 않도록 하고, 제조 시에 불량률을 최소화하고 신뢰도 높은 임베디드 인쇄회로기판을 제공하고자 한다.The present invention also provides a highly reliable embedded printed circuit board by using a material similar to the thermal expansion coefficient of the element surrounding the element so that the insulation layer is not peeled from the element and the defect rate during manufacturing is minimized .

전술한 문제를 해결하기 위한 본 실시예에 따른 임베디드 인쇄회로기판은 캐비티를 포함하는 절연 기판; 상기 캐비티에 배치되는 소자; 및 상기 절연 기판 상에 열 및 자외선 경화 재료로 형성되며, 상기 소자의 일부를 노출하는 개구부를 포함하는 절연층;을 포함한다.According to an embodiment of the present invention, there is provided an embedded printed circuit board including: an insulating substrate including a cavity; An element disposed in the cavity; And an insulating layer formed on the insulating substrate, the insulating layer being formed of a thermal and ultraviolet curing material and including an opening exposing a part of the device.

본 발명의 다른 일실시예에 따르면, 상기 절연층은 상기 캐비티의 측벽에 형성될 수 있다.According to another embodiment of the present invention, the insulating layer may be formed on a sidewall of the cavity.

본 발명의 다른 일실시예에 따르면, 상기 절연층은 상기 소자의 단자가 배치되는 일면에 형성되는 제1 절연층; 및 상기 소자의 타면에 형성되는 제2 절연층;을 포함할 수 있다.According to another embodiment of the present invention, the insulating layer includes a first insulating layer formed on one surface of the device, And a second insulating layer formed on the other surface of the device.

본 발명의 다른 일실시예에 따르면, 상기 절연층은 상기 개구부를 제외한 상기 소자의 주변부를 둘러쌀 수 있다.According to another embodiment of the present invention, the insulating layer may surround the periphery of the device except for the opening.

본 발명의 다른 일실시예에 따르면, 상기 개구부는 상기 소자의 단자들과 연결되는 금속 비아들 간의 사이 공간에 배치될 수 있다.According to another embodiment of the present invention, the opening may be disposed in a space between the metal vias connected to the terminals of the device.

본 발명의 다른 일실시예에 따르면, 상기 소자는 상기 노출되는 면의 일부에 상기 절연층이 배치될 수 있다.According to another embodiment of the present invention, the insulating layer may be disposed on a part of the exposed surface of the element.

본 발명의 다른 일실시예에 따르면, 상기 절연층은 120 ℃ 내지 160 ℃의 유리전이온도인 재료를 포함할 수 있다.According to another embodiment of the present invention, the insulating layer may include a material having a glass transition temperature of 120 ° C to 160 ° C.

본 발명의 다른 일실시예에 따르면, 상기 절연층은 열팽창 계수가 10 ppm/℃ 내지 20 ppm/℃인 재료를 포함할 수 있다.According to another embodiment of the present invention, the insulating layer may include a material having a thermal expansion coefficient of 10 ppm / ° C to 20 ppm / ° C.

본 발명의 다른 일실시예에 따르면, 상기 소자는 적외선 센서, 근조도 센서, 온도 센서, 습도 센서, 가스 센서, 이미지 센서, RGB 센서 및 제스처 센서 중에서 어느 하나일 수 있다.According to another embodiment of the present invention, the device may be any one of an infrared sensor, a muscle-tactility sensor, a temperature sensor, a humidity sensor, a gas sensor, an image sensor, an RGB sensor and a gesture sensor.

본 발명의 다른 일실시예에 따르면, 상기 소자의 감지부를 노출할 수 있다.According to another embodiment of the present invention, the sensing portion of the device may be exposed.

본 발명의 일실시예에 따르면 인쇄회로기판에 임베디드되는 소자의 일부를 노출하는 개구부가 형성되는 절연층을 열 및 자외선 경화 특징이 있는 감광성 자재를 사용하여, 인쇄회로기판 또는 소자의 손상 없이 개구부의 형성이 보다 용이하다.According to an embodiment of the present invention, an insulating layer having an opening for exposing a part of a device embedded in a printed circuit board is formed using a photosensitive material having heat and ultraviolet curing characteristics, It is easier to form.

또한, 본 발명의 일실시예에 따르면 소자를 둘러싸는 절연층을 소자의 열팽창률과 유사한 재료를 사용하여, 소자로부터 절연층이 박리되지 않도록 할 수 있으며, 임베디드 인쇄회로기판의 제조 시에 불량률을 최소화하고 보다 신뢰도 높은 임베디드 인쇄회로기판을 제공할 수 있다.According to an embodiment of the present invention, the insulating layer surrounding the device can be made of a material similar to the thermal expansion coefficient of the device, so that the insulating layer can be prevented from being peeled from the device, and the defect rate And provide a more reliable embedded printed circuit board.

도 1 내지 도 9는 본 발명의 일실시예에 따른 임베디드 인쇄회로기판 구조 및 그 제조 방법을 설명하기 위한 도면이다.1 to 9 are views for explaining a structure of an embedded printed circuit board and a method of manufacturing the same according to an embodiment of the present invention.

이하에서는 첨부한 도면을 참조하여 바람직한 본 발명의 일실시예에 대해서 상세히 설명한다. 다만, 실시형태를 설명함에 있어서, 관련된 공지 기능 혹은 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우 그에 대한 상세한 설명은 생략한다. 또한, 도면에서의 각 구성요소들의 크기는 설명을 위하여 과장될 수 있으며, 실제로 적용되는 크기를 의미하는 것은 아니다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail to avoid unnecessarily obscuring the subject matter of the present invention. In addition, the size of each component in the drawings may be exaggerated for the sake of explanation and does not mean a size actually applied.

도 1 내지 도 9는 본 발명의 일실시예에 따른 임베디드 인쇄회로기판의 제조 방법을 설명하기 위한 도면이다.1 to 9 are views for explaining a method of manufacturing an embedded printed circuit board according to an embodiment of the present invention.

도 1 내지 도 9를 참조하여 본 발명의 일실시예에 따른 임베디드 인쇄회로기판의 제조 방법을 설명하기로 한다.1 to 9, a method of manufacturing an embedded printed circuit board according to an embodiment of the present invention will be described.

도 1에 도시된 바와 같이 본 발명의 일실시예에 따른 임베디드 인쇄회로기판은, 먼저 절연 기판(110)에 캐비티(cavity: 111)를 형성한다.As shown in FIG. 1, an embedded printed circuit board according to an embodiment of the present invention firstly forms a cavity 111 in an insulating substrate 110.

이때, 상기 절연 기판(110)은 절연 재료로 형성될 수 있으며, 예를 들어 유리 섬유와 수지재를 포함하여 형성될 수 있다. 또한, 상기 캐비티(111)는 레이저 드릴 또는 기계적 드릴을 사용하여 형성할 수 있다.At this time, the insulating substrate 110 may be formed of an insulating material, for example, glass fiber and a resin material. The cavity 111 may be formed using a laser drill or a mechanical drill.

이후에는 도 2에 도시된 바와 같이 상기 절연 기판(110)의 일면에 임시층(115)을 형성할 수 있으며, 상기 임시층(115)은 폴리이미드(Polyimide) 재료로 형성될 수 있다.2, a temporary layer 115 may be formed on one side of the insulating substrate 110, and the temporary layer 115 may be formed of a polyimide material.

상기 임시층(115)은 상기 절연 기판(110) 내의 캐비티(111) 상에 소자(120)를 안정적으로 실장하기 위한 부재이다.The temporary layer 115 is a member for stably mounting the element 120 on the cavity 111 in the insulating substrate 110.

이후, 도 3에 도시된 바와 같이 상기 절연 기판(110)의 캐비티(111) 내에 소자(120)를 배치한다.Then, as shown in FIG. 3, the device 120 is disposed in the cavity 111 of the insulating substrate 110.

이때, 상기 캐티비(111)에는 상기 소자(120)가 배치된 이후에 상기 소자(120)와 상기 캐비티(111)의 측벽 간에는 여유 공간(112)이 형성될 수 있다.At this time, after the device 120 is disposed in the cavity 111, an empty space 112 may be formed between the device 120 and the side wall of the cavity 111.

한편, 본 발명의 일실시예에 따른 상기 소자(120)는 적외선 센서, 근조도 센서, 온도 센서, 습도 센서, 가스 센서, 이미지 센서, RGB 센서 및 제스처 센서 중에서 어느 하나일 수 있다.Meanwhile, the device 120 according to an exemplary embodiment of the present invention may be any one of an infrared sensor, a muscle strength sensor, a temperature sensor, a humidity sensor, a gas sensor, an image sensor, an RGB sensor, and a gesture sensor.

이후에는 도 4에 도시된 바와 같이 절연 기판(110) 및 소자(120) 상에 제1 절연층(131)을 형성한다. 상기 제1 절연층(131)은 열 및 자외선에 의해 경화되는 재료를 사용하여 상기 소자(120)의 일부를 노출하는 개구부(135)를 포함하도록 형성한다.Thereafter, a first insulating layer 131 is formed on the insulating substrate 110 and the device 120, as shown in FIG. The first insulating layer 131 is formed to include an opening 135 exposing a part of the device 120 using a material that is cured by heat and ultraviolet rays.

보다 상세하게 설명하면, 상기 제1 절연층(131)은 감광성(photosensitive) 재료로서 도 4에 도시된 바와 같이 자외선에 노광되어, 도 5에 도시된 바와 같이 열처리 되어 경화될 수 있다.More specifically, the first insulating layer 131 is exposed to ultraviolet rays as shown in FIG. 4 as a photosensitive material, and can be heat-treated and cured as shown in FIG.

이때, 상기 제1 절연층(131)은 120 ℃ 내지 160 ℃의 유리전이온도를 가지는 재료를 사용하여 자외선 가공과 열처리 가공을 하여 형성할 수 있다.At this time, the first insulating layer 131 may be formed by ultraviolet processing and heat treatment using a material having a glass transition temperature of 120 ° C to 160 ° C.

상기 도 4에 도시된 바와 같이 제1 절연층(131)은 60 ℃ 내지 100 ℃의 온도 상태에서 자외선 가공하고, 이후에 도 5에 도시된 바와 같이 제1 절연층(131)을 160 ℃ 내지 200 ℃의 온도로 열처리하여 경화할 수 있다.4, the first insulating layer 131 is ultraviolet-processed at a temperature of 60 ° C. to 100 ° C., and then the first insulating layer 131 is etched at 160 ° C. to 200 ° C. Lt; RTI ID = 0.0 > C, < / RTI >

또한, 본 발명의 일실시예에 따르면 상기 제1 절연층(131)은 상기 소자(120)의 열팽창률과 유사하도록 하기 위하여, 열팽창 계수가 10 ppm/℃ 내지 20 ppm/℃인 재료를 사용하여 형성하여, 소자(120)로부터 제1 절연층(131)이 박리되는 문제점이 발생하지 않도록 할 수 있다.According to an embodiment of the present invention, the first insulating layer 131 may be formed of a material having a thermal expansion coefficient of 10 ppm / ° C. to 20 ppm / ° C. so as to be similar to the thermal expansion coefficient of the device 120 So that the problem of peeling off of the first insulating layer 131 from the element 120 can be prevented.

또한, 상기 절연층(131)은 캐비티(111) 내의 측벽에 접하는 공간(133)에 일부가 형성될 수 있다.The insulating layer 131 may be partially formed in the space 133 that is in contact with the side wall of the cavity 111.

도 5에 도시된 바와 같이 상기 제1 절연층(131)을 열처리하여 경화한 이후에는, 도 6에 도시된 바와 같이 상기 임시층(115)을 제거하고, 상기 임시층(115)이 제거된 면에 제2 절연층(132)을 형성된다.After the first insulating layer 131 is cured by heat treatment as shown in FIG. 5, the temporary layer 115 is removed as shown in FIG. 6, and the temporary layer 115 is removed The second insulating layer 132 is formed.

이때, 상기 제1 절연층(131) 상에는 비아(134)가 형성될 수 있다.At this time, a via 134 may be formed on the first insulating layer 131.

상기 제2 절연층(132)은 상기 제1 절연층(131)과 동일한 재료를 이용하여 형성된다.The second insulating layer 132 is formed using the same material as the first insulating layer 131.

즉, 제2 절연층(132)은 상기 제1 절연층(131)과 동일하게 열 및 자외선에 의해 경화되는 재료를 사용하여 형성되며, 120 ℃ 내지 160 ℃의 유리전이온도를 가지는 재료로서, 소자(120)의 열팽창률과 유사하게 열팽창 계수가 10 ppm/℃ 내지 20 ppm/℃인 재료를 사용하여 형성할 수 있다.That is, the second insulating layer 132 is formed using a material that is cured by heat and ultraviolet rays in the same manner as the first insulating layer 131, and has a glass transition temperature of 120 ° C to 160 ° C. A material having a coefficient of thermal expansion of 10 ppm / ° C to 20 ppm / ° C similar to the coefficient of thermal expansion of the substrate 120 may be used.

상기와 같이 구성되는 제2 절연층(132)은 도 6에 도시된 바와 같이 자외선에 노광되고, 도 7에 도시된 바와 같이 열처리 되어 경화될 수 있으며, 그에 따라 상기 절연층(130)은 개구부(135)를 제외한 상기 소자(120)의 주변부를 둘러싸도록 형성될 수 있다.6, the second insulating layer 132 may be exposed to ultraviolet rays as shown in FIG. 6, and may be heat treated and cured as shown in FIG. 7, 135 may be formed so as to surround the peripheral portion of the device 120.

이후에는 도 8에 도시된 바와 같이 임베디드 인쇄회로기판 상에 관통홀(Through Hole: 140)을 형성하고, 상기 비아(134)와 관통홀(140)에 도금을 하여 소자(120)의 단자와 연결되는 도전성 비아(133)와, 도전성 단자(141)를 형성할 수 있다.Thereafter, as shown in FIG. 8, a through hole 140 is formed on the embedded printed circuit board, and the via 134 and the through hole 140 are plated to connect the terminal of the device 120 The conductive vias 133 and the conductive terminals 141 can be formed.

이후, 도 9에 도시된 바와 같이 임베디드 인쇄회로기판의 양면에 각각 보호층(150)을 형성할 수 있다.Then, as shown in FIG. 9, the passivation layer 150 may be formed on both sides of the embedded printed circuit board.

이상에서 설명한 바와 같이, 본 발명의 일실시예에 따르면 인쇄회로기판에 임베디드되는 소자의 일부를 노출하는 개구부(111)가 형성되는 절연층을 열 및 자외선 경화 특징이 있는 감광성 자재를 사용하므로, 인쇄회로기판 또는 소자(120)의 손상 없이 개구부(111)의 형성이 보다 용이하다.
As described above, according to the embodiment of the present invention, since the insulating layer having the openings 111 for exposing a part of the elements embedded in the printed circuit board is used as the photosensitive material having heat and ultraviolet curing characteristics, It is easier to form the opening 111 without damaging the circuit board or the element 120. [

이후부터는 도 9를 참조하여 본 발명의 일실시예에 따른 임베디드 인쇄회로기판의 구성을 설명하기로 한다.Hereinafter, the configuration of an embedded printed circuit board according to an embodiment of the present invention will be described with reference to FIG.

도 9에 도시된 바와 같이 본 발명의 일실시예에 따른 임베디드 인쇄회로기판은 절연 기판(110), 소자(120) 및 절연층(130)을 포함한다.As shown in FIG. 9, an embedded printed circuit board according to an embodiment of the present invention includes an insulating substrate 110, a device 120, and an insulating layer 130.

상기 절연 기판(110)은 캐비티(111)를 포함하고, 소자(120)는 상기 캐비티(111)에 배치되어 실장된다.The insulating substrate 110 includes a cavity 111 and the device 120 is disposed and mounted on the cavity 111.

이때, 상기 절연 기판(110)은 절연 재료로 형성될 수 있으며, 예를 들어 유리 섬유와 수지재를 포함하여 형성될 수 있다.At this time, the insulating substrate 110 may be formed of an insulating material, for example, glass fiber and a resin material.

한편, 본 발명의 일실시예에 따른 상기 소자(120)는 적외선 센서, 근조도 센서, 온도 센서, 습도 센서, 가스 센서, 이미지 센서, RGB 센서 및 제스처 센서 중에서 어느 하나일 수 있다.Meanwhile, the device 120 according to an exemplary embodiment of the present invention may be any one of an infrared sensor, a muscle strength sensor, a temperature sensor, a humidity sensor, a gas sensor, an image sensor, an RGB sensor, and a gesture sensor.

상기 절연층(130)은 상기 절연 기판(110) 상에 열 및 자외선 경화 재료로 형성되며, 상기 소자(120)의 일부를 노출하는 개구부(135)를 포함한다.The insulating layer 130 is formed of a heat and ultraviolet curing material on the insulating substrate 110 and includes an opening 135 exposing a part of the device 120.

보다 상세하게 설명하면, 상기 절연층(130)은 소자(120)의 단자(121)가 배치되는 일면에 형성되는 제1 절연층(131)과, 상기 소자(120)의 타면에 형성되는 제2 절연층(132)을 포함할 수 있다.The insulating layer 130 may include a first insulating layer 131 formed on one surface of the element 120 on which the terminal 121 is disposed and a second insulating layer 130 formed on the other surface of the element 120. [ And may include an insulating layer 132.

또한, 상기 절연층(130)은 120 ℃ 내지 160 ℃의 유리전이온도를 가지는 재료로서 60 ℃ 내지 100 ℃의 온도 상태에서 자외선 가공할 수 있으며, 160 ℃ 내지 200 ℃의 온도로 열처리하여 경화할 수 있는 재료를 사용하여 형성할 수 있다.The insulating layer 130 is a material having a glass transition temperature of 120 ° C to 160 ° C and may be ultraviolet-cured at a temperature of 60 ° C to 100 ° C and can be cured by heat treatment at a temperature of 160 ° C to 200 ° C. And the like.

한편, 상기 절연층(130)은 상기 캐비티(111)의 측벽에도 일부가 형성될 수 있으며, 상기 절연층(130)의 개구부(135)는 상기 소자(120)의 단자(121)들과 연결되는 금속 비아(133)들 간의 사이 공간에 배치될 수 있다. 즉, 상기 소자(120)의 노출되는 면의 일부 영역(136)에 상기 절연층(130)이 배치될 수 있다.The opening 135 of the insulating layer 130 is connected to the terminals 121 of the device 120. The openings 135 of the insulating layer 130 may be formed on the side walls of the cavity 111, And may be disposed in a space between the metal vias 133. [ That is, the insulating layer 130 may be disposed on a portion 136 of the exposed surface of the device 120.

그에 따라, 상기 절연층(130)은 개구부(135)를 제외한 상기 소자(120)의 주변부를 둘러싸도록 형성될 수 있다.Accordingly, the insulating layer 130 may be formed so as to surround the periphery of the device 120 except for the opening 135.

또한, 본 발명의 일실시예에 따른 임베디드 인쇄회로기판은 도전성 비아(133), 관통홀(140) 및 도전성 단자(131)를 포함할 수 있다.Also, the embedded printed circuit board according to an embodiment of the present invention may include a conductive via 133, a through hole 140, and a conductive terminal 131.

따라서, 본 발명의 일실시예에 따르면 임베디드된 소자의 일부를 노출하는 개구부(111)가 형성되는 절연층을 열 및 자외선 경화 특징이 있는 감광성 자재를 사용하여, 인쇄회로기판 또는 소자(120)의 손상 없이 개구부(111)의 형성이 보다 용이하다.Therefore, according to one embodiment of the present invention, the insulating layer on which the opening 111 is formed to expose a part of the embedded device is formed by using a photosensitive material having heat and ultraviolet curing characteristics, It is easier to form the opening 111 without damaging it.

그뿐만 아니라, 본 발명의 일실시예에 따르면 소자(120)를 둘러싸는 절연층(130)을 소자(120)의 열팽창률과 유사한 재료를 사용하여, 소자(120)로부터 절연층(130)이 박리되지 않도록 할 수 있으며, 임베디드 인쇄회로기판의 제조 시에 불량률을 최소화하고 보다 신뢰도 높은 임베디드 인쇄회로기판을 제공할 수 있다.In addition, according to one embodiment of the present invention, the insulating layer 130 surrounding the element 120 may be formed of a material similar to the thermal expansion coefficient of the element 120, And it is possible to minimize the defect rate in manufacturing the embedded printed circuit board and to provide a highly reliable embedded printed circuit board.

전술한 바와 같은 본 발명의 상세한 설명에서는 구체적인 실시예에 관해 설명하였다. 그러나 본 발명의 범주에서 벗어나지 않는 한도 내에서는 여러 가지 변형이 가능하다. 본 발명의 기술적 사상은 본 발명의 전술한 실시예에 국한되어 정해져서는 안 되며, 특허청구범위뿐만 아니라 이 특허청구범위와 균등한 것들에 의해 정해져야 한다.In the foregoing detailed description of the present invention, specific examples have been described. However, various modifications are possible within the scope of the present invention. The technical spirit of the present invention should not be limited to the above-described embodiments of the present invention, but should be determined by the claims and equivalents thereof.

110: 절연 기판
111: 캐비티
112: 여유 공간
115: 임시층
120: 소자
130: 절연층
131: 제1 절연층
132: 제2 절연층
133: 도전성 비아
134: 비아
135: 개구부
141: 도전성 단자
150: 보호층110: insulating substrate
111: cavity
112: Free space
115: Temporary layer
120: element
130: insulating layer
131: first insulating layer
132: second insulating layer
133: conductive vias
134: Via
135: opening
141: Conductive terminal
150: protective layer

Claims (10)

캐비티를 포함하는 절연 기판;
상기 캐비티에 배치되는 소자; 및
상기 절연 기판 상에 열 및 자외선 경화 재료로 형성되며, 상기 소자의 일부를 노출하는 개구부를 포함하는 절연층;
임베디드 인쇄회로기판.An insulating substrate including a cavity;
An element disposed in the cavity; And
An insulating layer formed on the insulating substrate, the insulating layer being formed of a thermal and ultraviolet curing material and including an opening exposing a part of the device;
Embedded printed circuit board. 청구항 1에 있어서,
상기 절연층은,
상기 캐비티의 측벽에 형성되는 임베디드 인쇄회로기판.The method according to claim 1,
Wherein the insulating layer
Wherein the cavity is formed on a sidewall of the cavity. 청구항 1에 있어서,
상기 절연층은,
상기 소자의 단자가 배치되는 일면에 형성되는 제1 절연층; 및
상기 소자의 타면에 형성되는 제2 절연층;
을 포함하는 임베디드 인쇄회로기판.The method according to claim 1,
Wherein the insulating layer
A first insulating layer formed on one surface of the device where the terminals are disposed; And
A second insulating layer formed on the other surface of the device;
≪ / RTI > 청구항 1에 있어서,
상기 절연층은,
상기 개구부를 제외한 상기 소자의 주변부를 둘러싸는 임베디드 인쇄회로기판.The method according to claim 1,
Wherein the insulating layer
And surrounding the periphery of the element except the opening. 청구항 1에 있어서,
상기 개구부는,
상기 소자의 단자들과 연결되는 금속 비아들 간의 사이 공간에 배치되는 임베디드 인쇄회로기판.The method according to claim 1,
The opening
And a plurality of metal vias connected to the terminals of the device. 청구항 1에 있어서,
상기 소자는,
상기 5노출되는 면의 일부에 상기 절연층이 배치되는 임베디드 인쇄회로기판.The method according to claim 1,
The device comprises:
And the insulating layer is disposed on a part of the five exposed surfaces. 청구항 1에 있어서,
상기 절연층은,
120 ℃ 내지 160 ℃의 유리전이온도인 재료를 포함하는 임베디드 인쇄회로기판.The method according to claim 1,
Wherein the insulating layer
Lt; RTI ID = 0.0 > 120 C < / RTI > to < RTI ID = 0.0 > 160 C. < / RTI > 청구항 1에 있어서,
상기 절연층은,
열팽창 계수가 10 ppm/℃ 내지 20 ppm/℃인 재료를 포함하는 임베디드 인쇄회로기판.The method according to claim 1,
Wherein the insulating layer
An embedded printed circuit board comprising a material having a coefficient of thermal expansion of 10 ppm / ° C to 20 ppm / ° C. 청구항 1에 있어서,
상기 소자는,
적외선 센서, 근조도 센서, 온도 센서, 습도 센서, 가스 센서, 이미지 센서, RGB 센서 및 제스처 센서 중에서 어느 하나인 임베디드 인쇄회로기판.The method according to claim 1,
The device comprises:
An embedded printed circuit board that is any one of an infrared sensor, a muscle strength sensor, a temperature sensor, a humidity sensor, a gas sensor, an image sensor, an RGB sensor, and a gesture sensor. 청구항 1에 있어서,
상기 개구부는,
상기 소자의 감지부를 노출하는 임베디드 인쇄회로기판.
The method according to claim 1,
The opening
And exposing a sensing portion of the device.
KR1020140007906A 2014-01-22 2014-01-22 Embedded printed circuit substrate KR102167597B1 (en)

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