KR20140141031A - Dummy substrate and package substrate manufacturing method utilizing the same - Google Patents
Dummy substrate and package substrate manufacturing method utilizing the same Download PDFInfo
- Publication number
- KR20140141031A KR20140141031A KR20130062256A KR20130062256A KR20140141031A KR 20140141031 A KR20140141031 A KR 20140141031A KR 20130062256 A KR20130062256 A KR 20130062256A KR 20130062256 A KR20130062256 A KR 20130062256A KR 20140141031 A KR20140141031 A KR 20140141031A
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- KR
- South Korea
- Prior art keywords
- dummy
- package substrate
- dummy substrate
- substrate
- package
- Prior art date
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- 239000000758 substrate Substances 0.000 title claims abstract description 217
- 238000004519 manufacturing process Methods 0.000 title description 35
- 238000000465 moulding Methods 0.000 claims description 56
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 26
- 229920006336 epoxy molding compound Polymers 0.000 claims description 20
- 239000012778 molding material Substances 0.000 claims description 18
- 239000011889 copper foil Substances 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 229920005989 resin Polymers 0.000 claims description 4
- 239000011347 resin Substances 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 17
- 239000010949 copper Substances 0.000 description 13
- 229910052802 copper Inorganic materials 0.000 description 12
- 230000002950 deficient Effects 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 239000010931 gold Substances 0.000 description 4
- 238000005452 bending Methods 0.000 description 3
- 239000000470 constituent Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
Abstract
Description
The present invention relates to a dummy substrate and a method of manufacturing the same, and more particularly, to a method of manufacturing a dummy substrate, Lt; / RTI > substrate. The present invention relates to a new dummy substrate and a method for manufacturing a package substrate therefrom, which can expect a favorable result such as resource saving and cost reduction by preventing expensive material wastes through realization of a substitute product for an expensive package substrate for producing a package substrate will be.
Generally, in order to form a plurality of semiconductor chips by performing various semiconductor processes on a wafer, and to mount each of the semiconductor chips on a printed circuit board, a wafer is subjected to a packaging process to form a semiconductor package Respectively. At this time, a wire bonding method using a wire is widely used as an electrical connection method for connecting a function of a semiconductor chip to the outside during a semiconductor package assembling process. Is a wire bonding method using a gold (Au) wire. The gold (Au) wire has a lower bonding force than aluminum (Al) wire or copper (Cu) wire, but can produce a ball with a geometric shape that is less prone to oxidation and contamination and can be finely machined. Which is the most widely used in semiconductor package assembly process. The package substrate includes a conductive wire (gold wire) for electrically connecting the semiconductor chip and the package substrate, and a molding member formed on the package substrate and covering the conductive wires, on which the semiconductor chip and the semiconductor chip are mounted. The molding member mainly employs an epoxy molding compound (EMC), which can be formed using a mold die having two cavities for receiving a package substrate. Specifically, a molding material (i.e., an epoxy molding compound) can be fed into the cavities through the mold gates of the mold die to form a molding member. That is, a plurality of semiconductor elements are wire-bonded to a package substrate on which semiconductor chips are mounted, and then an epoxy molding compound (EMC) is applied to protect the wire-bonded semiconductor elements from external environment such as impact, moisture, And a molding process for sealing the mold with a mold.
On the other hand, in the process of manufacturing a package substrate, it is common not to manufacture only one or two package substrates, but to manufacture a large number of package substrates. In the case of manufacturing such a large number of package substrates, (Such as a molding cover portion formed by an epoxy molding compound, etc.) when the package substrate is directly put into the package manufacturing apparatus or the like in the initial manufacturing step, Etc. are not properly formed. In this case, there is a problem that a defective package substrate is mass-produced. Particularly, as described above, the package substrate is wire-bonded with a gold wire or the like, and the semiconductor chips are mounted on the package substrate, which is quite expensive. If such a high price of the package substrate is incurred, economical and resource-wise losses are incurred.
It is an object of the present invention to provide a new dummy substrate which is advantageous in terms of cost and resources by preventing an expensive package substrate from being mass-produced in defective in a package substrate manufacturing step and preventing an expensive package substrate from being defective. The present invention is an invention capable of replacing a package substrate (original substrate) with a disposable dummy substrate. Since the expensive package substrate is not discarded, the main object of the present invention is to provide a dummy substrate which is very advantageous in terms of economy and resource saving . It is another object of the present invention to provide a dummy substrate for preventing generation of a defective mass due to copper burrs by etching the periphery of a router and a hole of a package substrate.
According to an aspect of the present invention, there is provided a semiconductor device comprising: a dummy substrate body; And a dummy pattern portion provided on a surface of the dummy substrate body and having a condition corresponding to a condition of a pattern portion implemented in the package substrate.
The pattern portion may include a chip mounted on the surface of the package substrate, and the dummy pattern portion may have a volume (area and height) corresponding to the volume of the chip.
And the dummy pattern portion is formed of a pad attached to a surface of the dummy substrate body.
And the pad is composed of a silicon pad provided on the surface of the dummy substrate body so as to have a volume and position corresponding to the volume and position of the chip mounted on the surface of the package substrate.
And the pad is formed of a silicon tape attached to the surface of the dummy substrate body.
The dummy substrate body includes: a core plate made of a resin; And a lower copper layer formed on both sides of the core plate. The dummy substrate body is provided with a hole penetrating the upper and lower surfaces, and the inner peripheral surface of the hole is provided with a treatment surface from which burrs are removed by etching.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: placing a dummy substrate having a dummy pattern portion on a surface of a dummy substrate body, Injecting a molding material (epoxy molding compound) into the cavity in the mold to form a molding member covering the pattern unit; A step of injecting an original substrate into the cavity in the mold according to a forming condition of the molding member on the dummy substrate body of the dummy substrate; And injecting a molding material into the cavity in a state where the package substrate is inserted into the cavity in the mold to cover the pattern portion provided on the surface of the package substrate with the molding member. A substrate manufacturing method is provided.
Wherein the mold is provided with a runner communicating with the cavity, the pusher coupled to the mold is arranged to be able to move up and down, and the molding material injected into the runner is pressed by the pusher, And the amount of the molding member provided on the surface of the package substrate is adjusted by adjusting the amount.
The dummy substrate includes an upper copper foil layer and a lower copper foil layer formed on both surfaces of the core plate. The hole is formed in the dummy substrate body to pass through the upper and lower surfaces, and the burr formed around the hole is removed by etching. do.
Stressing the package substrate in advance by bending the package substrate to the other surface opposite to the one surface of the molding member, and then forming the molding member on one surface of the package substrate.
In the present invention, the test for the possibility of mass production before production in the memory and non-memory production was tested with an original substrate. However, the present invention is based on the fact that a volume of a package substrate (Dummy Substrate), which contains epoxy resin and epoxy resin, is expected to have a high effect on cost reduction of epoxy molding compound through realization of substitute product. Etching around routers and hole machining, It is effective to prevent the occurrence of mass production failure. In other words, the present invention realizes a product similar to an on-chip volume condition on an original substrate (a package substrate), that is, a position and volume similar to a chip form using a silicon-based (Maker: 3M) pad Condition formation is attached. A silicon-based double-sided tape is attached and formed to a size corresponding to the chip size, and the volume condition of the dummy pattern portion is similar to the volume of the chip provided on the package substrate, thereby reducing the volume of the epoxy molding compound cost by volume . In addition, in the present invention, the generation of copper burrs is removed in advance by etching the outer side of the dummy substrate body and the peripheries of the holes, thereby preventing the occurrence of poor quality production due to copper burrs.
1 is a perspective view showing an upper surface of a dummy substrate according to an embodiment of the present invention;
FIG. 2 is a perspective view showing a state in which a molding member is formed on the upper surface of the dummy substrate shown in FIG.
FIG. 3 is a perspective view schematically showing a state in which a molding member is formed on the upper surface of the dummy substrate shown in FIG. 1,
FIG. 4 is a perspective view schematically showing a process of forming a molding member on the dummy substrate shown in FIG. 3,
5 is a perspective view showing a top surface of a dummy substrate according to another embodiment of the present invention;
FIG. 6 is a perspective view showing a state in which a molding member is formed on the upper surface of the dummy substrate shown in FIG.
7 is a perspective view schematically showing a state in which a molding member is formed on the upper surface of the dummy substrate shown in Fig. 5,
8 is a perspective view schematically showing a process of forming a molding member on the dummy substrate shown in Fig. 5,
9 is a perspective view showing an example of a package substrate manufactured using the dummy substrate of the present invention,
10 is a perspective view showing the upper surface of the package substrate shown in Fig.
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The objects, features and advantages of the present invention will be more readily understood by reference to the accompanying drawings and the following detailed description. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.
In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the constituent elements from other constituent elements, and the terms do not limit the nature, order or order of the constituent elements. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; coupled "or" connected "
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The present invention should not be construed as limited to the embodiments described in Figs.
Referring to the drawings, a
FIG. 1 is a perspective view of a
The
A
A
The
Therefore, the
The
The
In summary, the inventors of the present invention have tested the possibility of mass production before production in the memory and non-memory production with an original substrate (original substrate). However, Layer dummy substrate 10 (dummy substrate) containing the volume of the chip of the
Further, according to the present invention, a method of manufacturing a package substrate utilizing the
And injecting a molding material (epoxy molding compound) into the cavity of the mold to form a
And a step of injecting the original substrate into the cavity in the mold according to the forming condition of the
Next, a molding material (epoxy molding compound) is injected into the cavity in a state where the
On the other hand, pre-stress is applied to bend the
FIG. 5 is a perspective view of a
5 and 6, the
A
It is to be understood that the terms "comprises", "comprising", or "having" as used in the foregoing description mean that a component can be implanted unless specifically stated to the contrary, But should be construed as further including other elements. All terms, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise defined. Commonly used terms, such as predefined terms, should be interpreted to be consistent with the contextual meanings of the related art, and are not to be construed as ideal or overly formal, unless expressly defined to the contrary.
The foregoing description is merely illustrative of the technical idea of the present invention, and various changes and modifications may be made by those skilled in the art without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.
Therefore, it should be understood that the above-described embodiments are provided so that those skilled in the art can fully understand the scope of the present invention. Therefore, it should be understood that the embodiments are to be considered in all respects as illustrative and not restrictive, The invention is only defined by the scope of the claims.
In other words, while the description of the dummy substrate of the present invention has been described in conjunction with the accompanying drawings, it is to be understood that the best mode embodiment of the present invention has been described by way of illustration and not as a limitation of the present invention, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the present invention.
2. Package substrate 4. Pattern part
7.
10.
12a.
12c. Lower copper foil layer 12h. hall
14. The dummy pattern portion
Claims (10)
And a dummy pattern portion (14) provided on a surface of the dummy substrate body (12) and having a condition corresponding to a condition of a pattern portion (4) implemented in the package substrate (2) (10).
Wherein the pattern unit includes a chip mounted on the surface of the package substrate and the dummy pattern unit has a volume corresponding to the volume of the chip. 10).
Wherein the dummy pattern portion (14) comprises a pad attached to the surface of the dummy substrate body (12).
Characterized in that the pad comprises a silicon pad provided on the surface of the dummy substrate body (12) so as to have a volume and position corresponding to the volume and position of the chip mounted on the surface of the package substrate (2) ).
Wherein the pad is comprised of a silicon tape attached to a surface of the dummy substrate body.
The dummy substrate body (12)
A core plate 12a made of resin;
An upper copper foil layer 12b and a lower copper foil layer 12c formed on both sides of the core plate 12a,
Characterized in that the dummy substrate body (12) is provided with a hole (12h) penetrating to the upper and lower surfaces thereof and the inner peripheral surface of the hole (12h) is provided with a treatment surface (16a) (10).
Forming a molding member (8) covering the pattern unit (4) by injecting a molding material (epoxy molding compound) into the cavity in the mold;
Injecting a package substrate (2) into the cavity in the mold according to a forming condition of the molding member (8) in the dummy substrate body (12) of the dummy substrate (10);
The molding material is injected into the cavity in a state where the package substrate 2 is inserted into the cavity in the mold so that the pattern part 4 provided on the surface of the package substrate 2 is covered with the molding member 8 The method of claim 1, further comprising:
Wherein the mold is provided with a runner communicating with the cavity, the pusher coupled to the mold is arranged to be able to move up and down, and the molding material injected into the runner is pressed by the pusher, Wherein the amount of the molding material (8) provided on the surface of the package substrate (2) is adjusted by adjusting the amount of the molding material (8).
The dummy substrate 10 includes an upper copper foil layer 12b and a lower copper foil layer 12c formed on both sides of the core plate 12a and a hole 12h is formed in the dummy substrate body 12 And the burr formed around the hole (12h) is removed by an etching process.
Stress is applied to bend the package substrate 2 in advance to the other surface opposite to the one surface of the molding member 8 and then the molding member 8 is formed on one surface of the package substrate 2 Wherein the dummy substrate is made of a metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020130062256A KR101524603B1 (en) | 2013-05-31 | 2013-05-31 | Dummy substrate and package substrate manufacturing method utilizing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020130062256A KR101524603B1 (en) | 2013-05-31 | 2013-05-31 | Dummy substrate and package substrate manufacturing method utilizing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20140141031A true KR20140141031A (en) | 2014-12-10 |
| KR101524603B1 KR101524603B1 (en) | 2015-06-01 |
Family
ID=52458650
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020130062256A KR101524603B1 (en) | 2013-05-31 | 2013-05-31 | Dummy substrate and package substrate manufacturing method utilizing the same |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR101524603B1 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4012621B2 (en) * | 1998-03-25 | 2007-11-21 | ヤマハ発動機株式会社 | Tool for inspecting component mounting status |
| KR100654085B1 (en) * | 2005-08-09 | 2006-12-06 | 주식회사 신화테크 | Process for the production of printedwiring board |
-
2013
- 2013-05-31 KR KR1020130062256A patent/KR101524603B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR101524603B1 (en) | 2015-06-01 |
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