KR20140125151A - Multilayer ceramic capacitor - Google Patents

Multilayer ceramic capacitor Download PDF

Info

Publication number
KR20140125151A
KR20140125151A KR1020130042957A KR20130042957A KR20140125151A KR 20140125151 A KR20140125151 A KR 20140125151A KR 1020130042957 A KR1020130042957 A KR 1020130042957A KR 20130042957 A KR20130042957 A KR 20130042957A KR 20140125151 A KR20140125151 A KR 20140125151A
Authority
KR
South Korea
Prior art keywords
crack
n3
length
layer
ceramic body
Prior art date
Application number
KR1020130042957A
Other languages
Korean (ko)
Other versions
KR101994710B1 (en
Inventor
임진형
이교광
장태진
김두영
정해석
Original Assignee
삼성전기주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전기주식회사 filed Critical 삼성전기주식회사
Priority to KR1020130042957A priority Critical patent/KR101994710B1/en
Publication of KR20140125151A publication Critical patent/KR20140125151A/en
Application granted granted Critical
Publication of KR101994710B1 publication Critical patent/KR101994710B1/en

Links

Images

Abstract

The present invention relates to a multi-layered ceramic capacitor. In order to provide a propagation path of a crack in a ceramic body due to an external shock, the capacitor comprises: a ceramic body; a pair of external electrode terminals which are provided in both side ends of the ceramic body; a plurality of internal electrode layers which are laminated on a central portion of the ceramic body at predetermined intervals and of which one end is connected to any one of the external electrode terminals and the other end is spaced apart from the opposite external electrode terminal by predetermined intervals (L1); and a crack diffusion preventing layer, a crack inducing layer, and a crack guiding layer which are laminated on at least one of an upper end portion and a lower end portion of the ceramic body at predetermined intervals and are formed on at least one side end of the both side ends of the ceramic body. The multi-layered ceramic capacitor satisfies the following equation 1. [Equation 1] n3 > L1, L2 >a1, a2 ≠ 0 (n3 is a length of the crack guiding layer, L2 is a value obtained by subtracting L1 from n3, a1 is a value obtained by subtracting n3 from a length of the crack diffusion preventing layer (n1), a2 is a value obtained by subtracting a length of the crack guiding layer (n2) from n3.).

Description

[0001] MULTILAYER CERAMIC CAPACITOR [0002]

The present invention relates to a multilayer ceramic capacitor, and more particularly, to a multilayer ceramic capacitor multilayer ceramic capacitor provided with a crack preventing member therein.

In general, an electronic component using a ceramic material such as a capacitor, an inductor, a piezoelectric element, a varistor or a thermistor includes a ceramic body made of a ceramic material, an internal electrode layer formed inside the body, and an external electrode Respectively.

The multilayer ceramic capacitor in the ceramic electronic component includes a plurality of laminated ceramic sheets, an inner electrode layer arranged to face each other with the one ceramic sheet interposed therebetween, and an outer electrode terminal electrically connected to the inner electrode layer.

The multilayer ceramic capacitor is widely used as a component of a mobile communication device such as a computer, a PDA, and a mobile phone due to its small size, high capacity, and ease of mounting.

In recent years, miniaturization and multifunctionalization of electronic products have led to the tendency that the chip components are also downsized and highly functional. Therefore, a multilayer ceramic capacitor is required to have a large-capacity high-capacity product with a small size.

Korean Patent Application Laid-Open No. 10-2011-0122008 discloses a method of manufacturing a multilayer ceramic capacitor, in which a ceramic green sheet is manufactured and an internal electrode layer is formed by printing a conductive paste on a ceramic green sheet. A ceramic green sheet having an internal electrode layer is stacked up to several tens to several hundred layers to form a green ceramic laminate. Thereafter, the green ceramic laminate is pressed at high temperature and high pressure to produce a rigid green ceramic laminate, and a green chip is produced through a cutting process. Thereafter, the green chip is subjected to calcination, firing and polishing, and external electrodes are formed to complete the multilayer ceramic capacitor.

However, in the thus-fabricated multilayer ceramic capacitor, the internal electrode layer made of metal is liable to shrink and expand as compared with the ceramic material, and the stress due to the difference in the thermal expansion coefficient acts on the ceramic laminate to cause cracks.

A ferroelectric material such as barium titanate having a relatively high dielectric constant is generally used as a ceramic material constituting the ceramic body. In the case of such a ferroelectric material, since it has piezoelectricity and electrostrictive properties, the ferroelectric material exhibits vibrations due to stress and mechanical deformation Cracks may occur.

The multilayer ceramic capacitor is used in a state of being mounted on a wiring board, and is electrically connected to the external electrodes of the multilayer ceramic capacitor by soldering with a conductive land formed on the wiring board. When the multilayer ceramic capacitor is mounted on the wiring board by soldering or when the wiring board on which the multilayer ceramic capacitor is mounted is cut, thermal shock and shear stress are applied to the multilayer ceramic capacitor. Cracks can be generated by such thermal shock and shear stress.

Recently, as the size and capacity of multilayer ceramic capacitors have been reduced, thinner and multilayered ceramic multilayer bodies have been attempted. As the frequency of occurrence of cracks increases due to such thinning and multilayering, there is a great demand for improvement of the multilayer ceramic capacitors.

Korean Patent Application Publication No. 10-2011-0122008

The present invention provides a multilayer ceramic capacitor in which a crack preventing member is provided in a ceramic body to effectively suppress the occurrence rate of cracks and to prevent the internal electrode layer from reaching a propagating path even if cracks are generated to thereby ensure reliability and stability of the product I want to.

The present invention, which is provided to achieve the above object, includes a ceramic body; A pair of external electrode terminals provided on both ends of the ceramic body; A plurality of internal electrode layers stacked at a predetermined distance in a central portion of the ceramic body, the internal electrode layers having one end connected to one of the external electrode terminals and the other end spaced apart from the external electrode terminal at a predetermined interval (L1); And a crack guide layer formed on at least one side of both ends of the ceramic body, the crack guide layer and the crack guide layer being stacked on at least one of an upper end portion and a lower end portion of the ceramic body at a predetermined interval, A multilayer ceramic capacitor satisfying Expression (1) is provided.

Figure pat00001

(where n3 is the length of the crack guide layer, L2 is a value obtained by subtracting L1 from n3, a1 is a value obtained by subtracting n3 from the length (n1) of the crack diffusion preventing layer, and a2 is a value obtained by subtracting the length (n2) )

Here, the crack guide layer is laminated on the crack guide layer, and the crack diffusion barrier layer is laminated on the crack guide layer.

In addition, a predetermined interval (L1) between the outer electrode terminal and the inner electrode layer spaced apart from the inner electrode layer of the pair of outer electrode terminals, and a length (n3) of the crack guide layer satisfy the following expression Thereby providing a multilayer ceramic capacitor.

Figure pat00002

The length (n2) of the crack inducing layer and the length (n1) of the crack diffusion preventing layer satisfy the following formula (3).

Figure pat00003

Further, the length (n3) of the crack guide layer and the length (n2) of the crack inducing layer satisfy the following formula (4).

Figure pat00004

According to the multilayer ceramic capacitor of the present invention, it is possible to suppress the occurrence of cracks in the inside of the multilayer ceramic capacitor due to an external impact, a difference in thermal expansion coefficient between materials, thermal deformation during processing and the like, The crack can be prevented from reaching the internal electrode layer.

1 is a perspective view of a multilayer ceramic capacitor according to the present invention.
2 is a cross-sectional view of a multilayer ceramic capacitor according to the present invention.
FIGS. 3 to 8 are views for explaining propagation paths of cracks according to the lengths of the crack diffusion preventing layer, the crack inducing layer, and the crack guide layer included in the present invention. FIG.
9 is a graph showing a change in characteristic value according to L1 / n3.
10 is a graph showing a change in characteristic value according to n2 / n1.
11 is a graph showing a change in characteristic value according to n3 / n2.

The advantages and features of the present invention and the techniques for achieving them will be apparent from the following detailed description taken in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The present embodiments are provided so that the disclosure of the present invention is not only limited thereto, but also may enable others skilled in the art to fully understand the scope of the invention. Like reference numerals refer to like elements throughout the specification.

The terms used herein are intended to illustrate the embodiments and are not intended to limit the invention. In this specification, the singular forms include plural forms unless otherwise specified in the text. The terms 'comprise', and 'comprising' as used herein do not exclude the presence or addition of one or more other elements, steps, operations, and elements, .

Hereinafter, the configuration and operation effects of the present invention will be described in more detail with reference to the accompanying drawings.

FIG. 1 is a perspective view of a multilayer ceramic capacitor according to the present invention, and FIG. 2 is a cross-sectional view of a multilayer ceramic capacitor according to the present invention. In addition, the components of the drawings are not necessarily drawn to scale; for example, the dimensions of some of the components of the drawings may be exaggerated relative to other components to facilitate understanding of the present invention.

1 and 2, a multilayer ceramic capacitor 100 according to the present invention includes a ceramic body 110 and a pair of external electrode terminals 120 provided on both ends of the ceramic body 110 can do.

The ceramic body 110 is formed by stacking and pressing a plurality of ceramic sheets composed of a ferroelectric material such as barium titanate (TiBa 1 ), for example, and then sintering the ceramic body 110. So that it can not be distinguished. Accordingly, it is also shown in the drawing that the ceramic sheets are integrally shown without being distinguished from each other.

The ceramic body 110 may be divided into an upper portion and a lower portion by a position and a central portion between the upper and lower ends. In the center portion, a plurality of internal electrode layers 111 are stacked at a predetermined interval, .

The internal electrode layer 111 is made of a metal thin film obtained by sintering a metal paste. As the metal paste, a metal material such as Ni, Pd, Ag-Pd, or Cu is used as a main component.

The internal electrode layers 111 may be alternately connected to the pair of external electrode terminals 120 with different interlayer directions.

For example, the odd-numbered internal electrode layers 111 may be connected to any one of the external electrode terminals 120 of the pair of external electrode terminals 120 to provide a positive polarity, The electrode layer 111 may be connected to the other external terminal 120 and may be given a negative polarity. Of course, the (-) polarity may be given to the internal electrode layer 111 of the odd-numbered layer and the (+) polarity may be given to the internal electrode layer 111 of the even-numbered layer.

One end of the internal electrode layer 111 connected to one of the external electrode terminals 120 of the pair of external electrode terminals 120 is exposed at a side end surface of the ceramic body 110 and electrically connected to the external electrode terminal 120 And the other end is spaced apart from the other external electrode terminal 120 by a predetermined distance L1.

The feature of the present invention resides in a crack diffusion preventing layer 112, a crack inducing layer 113, and a crack guide layer 114 which are stacked at a predetermined distance on at least one of an upper end portion and a lower end portion of the ceramic body 110. The crack diffusion preventing layer 112, the crack inducing layer 113, and the crack guide layer 114 are placed on the lower end of the ceramic body 110 for clarification.

The crack propagation preventing layer 112, the crack inducing layer 113 and the crack guide layer 114 may be provided on the opposite ends of at least one of the opposite ends of the ceramic body 110, The crack inducing layer 113 and the crack diffusion preventing layer 112 may be sequentially stacked on top of the crack inducing layer 113 and the crack inducing layer 113, respectively.

When the length of the crack diffusion preventing layer 112 is n1, the length of the crack inducing layer 113 is n2, and the length of the crack guide layer 114 is n3, the following expression (1) can be satisfied.

[Equation 1]

Figure pat00005

Here, L2 is a value obtained by subtracting L1 from n3, a1 is a value obtained by subtracting n3 from n1, and a2 is a value obtained by subtracting n2 from n3.

The correlation between the crack diffusion preventing layer 112, the crack inducing layer 113, and the crack guide layer 114 according to the equation (1) is obtained through experiments. The crack propagation path Here is the following.

3 through 7 illustrate the relationship between the length n1 of the crack diffusion preventing layer 112, the length n2 of the crack inducing layer 113 and the length n3 of the crack guide layer 114, 3 and 4, when the value of n3 is equal to or smaller than the value of L1, it can be seen that the crack propagates in the vertical direction and reaches the internal electrode layer 111. As shown in FIG. 4, when the value of n3 is smaller than the value of L1, the crack diffusion preventing layer 112, the crack inducing layer 113, and the crack guide layer 114 fail to function as a crack preventing member at all, It can be seen that progress is made.

5, even if the value of n3 is larger than the value of L1, it is confirmed that the value of n3 is equal to the value of n1 and n2, and when the values of a1 and a2 are 0, the crack propagates in the diagonal direction and reaches the internal electrode layer 111 have.

However, as shown in FIGS. 6 and 7, when the value of n3 is larger than the value of L1, the value of n1 is larger than the value of n3 and the value of a1 is not 0 (FIG. 6) (Fig. 7), it is confirmed that the propagation of the crack in the vertical direction is suppressed.

In this case, however, a more stable design is required because the crack proceeds in the horizontal direction parallel to the arrangement direction of the internal electrode layers 111. Accordingly, if the value of n2 is designed to be smaller than the value of n3 and the value of a2 is not 0 as in Equation (1), it can be confirmed that the crack is guided toward the inside with the crack inducing layer 113 as shown in FIG.

On the other hand, for a finer control, the relationship between the L1 value and the n3 value can be designed to satisfy the following expression (2).

&Quot; (2) "

Figure pat00006

Table 1 below shows the characteristic values according to L1 / n3. FIG. 9 shows the graphs. As the L1 / n3 value is larger, the occurrence rate of cracks decreases and the total capacity of the capacitor increases. However, Since there is a side effect, it is preferable that L1 / n3 is designed so as to satisfy the numerical range of the above-mentioned formula (2).

Figure pat00007

The relationship between the n2 value and n1 can be designed so as to satisfy the following expression (3).

&Quot; (3) "

Figure pat00008

FIG. 10 is a graph showing a crack occurrence rate and an internal penetration rate according to n2 / n1, and FIG. 10 is a graph showing crack propagation paths when n2 / n1 is 1 or more, N1 / n1 is designed to satisfy the numerical range of the formula (3) because the internal penetration rate of the crack is increased because it is difficult to be guided to the crack 113 and, on the other hand, .

Figure pat00009

The relationship between the n3 value and n2 can be designed so as to satisfy the following expression (4).

&Quot; (4) "

Figure pat00010

Table 3 below is a table showing the incidence rate and the limit length of cracks according to n3 / n2, and FIG. Here, the critical length means the bending depth of the substrate when a crack is generated in vibration due to the piezoelectric property in the substrate to which the capacitor element is attached.

As shown in Table 3 and FIG. 11, as the value of n3 / n2 increases, that is, the difference between the length n3 of the crack guide layer and the length n2 of the crack guide layer increases, the cracking rate decreases and the critical length increases . However, if the value of n3 is too large, the length n3 of the crack guide layer 114 becomes equal to or exceeds the length n1 of the crack diffusion preventing layer 112, and it becomes difficult to induce a crack into the inside. Therefore, it is desirable that n3 / n2 is designed so as to satisfy the numerical range of the above-mentioned formula (4).

Figure pat00011

The foregoing detailed description is illustrative of the present invention. It is also to be understood that the foregoing is illustrative and explanatory of preferred embodiments of the invention only, and that the invention may be used in various other combinations, modifications and environments. That is, it is possible to make changes or modifications within the scope of the concept of the invention disclosed in this specification, the disclosure and the equivalent scope thereof, and the skill or knowledge of the art. The foregoing embodiments are intended to illustrate the best mode contemplated for carrying out the invention and are not intended to limit the scope of the present invention to other modes of operation known in the art for utilizing other inventions such as the present invention, Various changes are possible. Accordingly, the foregoing description of the invention is not intended to limit the invention to the precise embodiments disclosed. It is also to be understood that the appended claims are intended to cover such other embodiments.

100: Multilayer Ceramic Capacitor
110: Ceramic body
120: external electrode terminal
111: internal electrode layer
112: crack diffusion preventing layer
113: crack inducing layer
114: crack guide layer

Claims (5)

  1. A ceramic body;
    A pair of external electrode terminals provided on both ends of the ceramic body;
    A plurality of internal electrode layers stacked at a predetermined distance in a central portion of the ceramic body, the internal electrode layers having one end connected to one of the external electrode terminals and the other end spaced apart from the external electrode terminal at a predetermined interval (L1); And
    A crack guide layer and a crack guide layer stacked on at least one of an upper end portion and a lower end portion of the ceramic body with a predetermined gap therebetween and formed on at least one side of both ends of the ceramic body,
    Wherein the multilayer ceramic capacitor satisfies the following formula (1).
    [Equation 1]
    Figure pat00012

    (where n3 is the length of the crack guide layer, L2 is a value obtained by subtracting L1 from n3, a1 is a value obtained by subtracting n3 from the length (n1) of the crack diffusion preventing layer, and a2 is a value obtained by subtracting the length (n2) )
  2. The method according to claim 1,
    Wherein the crack guide layer is laminated on the crack guide layer and the crack diffusion barrier layer is laminated on the crack guide layer,
    Multilayer Ceramic Capacitors.
  3. The method according to claim 1,
    Wherein a predetermined interval (L1) between the external electrode terminals spaced apart from the internal electrode layers and the internal electrode layers among the pair of external electrode terminals and a length (n3) of the crack guide layer satisfy the following formula (2) Capacitor.
    &Quot; (2) "
    Figure pat00013

  4. The method according to claim 1,
    Wherein the length (n2) of the crack inducing layer and the length (n1) of the crack diffusion preventing layer satisfy the following formula (3).
    &Quot; (3) "
    Figure pat00014

  5. The method according to claim 1,
    Wherein the length (n3) of the crack guide layer and the length (n2) of the crack inducing layer satisfy the following formula (4).
    &Quot; (4) "
    Figure pat00015
KR1020130042957A 2013-04-18 2013-04-18 Multilayer ceramic capacitor KR101994710B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020130042957A KR101994710B1 (en) 2013-04-18 2013-04-18 Multilayer ceramic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020130042957A KR101994710B1 (en) 2013-04-18 2013-04-18 Multilayer ceramic capacitor

Publications (2)

Publication Number Publication Date
KR20140125151A true KR20140125151A (en) 2014-10-28
KR101994710B1 KR101994710B1 (en) 2019-07-01

Family

ID=51995094

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020130042957A KR101994710B1 (en) 2013-04-18 2013-04-18 Multilayer ceramic capacitor

Country Status (1)

Country Link
KR (1) KR101994710B1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008091521A (en) * 2006-09-29 2008-04-17 Tdk Corp Stacked capacitor and manufacturing method of stacked capacitor
JP4491258B2 (en) * 2004-03-04 2010-06-30 株式会社岡村製作所 Cabinet side plate structure
KR20110122008A (en) 2010-05-03 2011-11-09 삼성전기주식회사 Multilayer ceramic capacitor and printed circuit board comprising the same and fabricating method of the same multilayer ceramic capacitor
JP2013093374A (en) * 2011-10-24 2013-05-16 Murata Mfg Co Ltd Electronic component

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4491258B2 (en) * 2004-03-04 2010-06-30 株式会社岡村製作所 Cabinet side plate structure
JP2008091521A (en) * 2006-09-29 2008-04-17 Tdk Corp Stacked capacitor and manufacturing method of stacked capacitor
KR20110122008A (en) 2010-05-03 2011-11-09 삼성전기주식회사 Multilayer ceramic capacitor and printed circuit board comprising the same and fabricating method of the same multilayer ceramic capacitor
JP2013093374A (en) * 2011-10-24 2013-05-16 Murata Mfg Co Ltd Electronic component

Also Published As

Publication number Publication date
KR101994710B1 (en) 2019-07-01

Similar Documents

Publication Publication Date Title
JP5755685B2 (en) Multilayer chip electronic component, substrate on which multilayer chip electronic component is mounted, and packaging unit
CN101714455B (en) Laminated ceramic electronic component and method for manufacturing the same
JP5375877B2 (en) Multilayer capacitor and multilayer capacitor manufacturing method
JP2005136132A (en) Laminated capacitor
JP5563111B2 (en) Multilayer ceramic capacitor and circuit board mounted with multilayer ceramic capacitor
KR101474065B1 (en) Laminated chip electronic component, board for mounting the same, packing unit thereof
US20130319742A1 (en) Laminated chip electronic component, board for mounting the same, and packing unit thereof
JP5899699B2 (en) Multilayer capacitor
KR101452049B1 (en) Multi-layered ceramic capacitor, mounting structure of circuit having thereon multi-layered ceramic capacitor and packing unit for multi-layered ceramic capacitor
CN102347131B (en) Ceramic electronic component
TWI412047B (en) Ceramic electronic component
JP6275377B2 (en) Multilayer chip electronic component, its mounting substrate and package
KR101539808B1 (en) Multilayer ceramic capacitor
KR101548773B1 (en) Mounting structure of ciruit board having thereon multi-layered ceramic capacitor
WO2006126562A1 (en) Multilayer ceramic electronic component
KR101843182B1 (en) Multilayer ceramic electronic component
JP5699819B2 (en) Ceramic electronic components
US8773839B2 (en) Multilayer ceramic electronic component
KR101933412B1 (en) Multi-layered ceramic capacitor and board for mounting the same
US20140340815A1 (en) Multilayer ceramic capacitor and method of manufacturing the same
KR101141417B1 (en) Multilayer ceramic capacitor and method for manufactuaring the same
JP5536244B2 (en) Multilayer ceramic capacitor, circuit board mounting structure of multilayer ceramic capacitor, and package of multilayer ceramic capacitor
JP5206440B2 (en) Ceramic electronic components
CN102683016A (en) Multilayer ceramic capacitor and method of manufacturing the same
JP5579886B2 (en) Multilayer ceramic capacitor and its mounting board

Legal Events

Date Code Title Description
E701 Decision to grant or registration of patent right
GRNT Written decision to grant