KR20140123318A - Method for separating growth substrate using stress and method for fabricating semiconductor device using the same - Google Patents

Abstract

Disclosed are a method for separating a growth substrate using stress and a method for fabricating a semiconductor device using the same. The method for separating a growth substrate comprise: forming a sacrificial layer on the growth substrate; forming a mask layer on the sacrificial layer, wherein the mask layer includes a masking portion and an opening portion; forming an epitaxial layer covering the masking portion on the sacrificial layer and forming a cavity in the sacrificial layer under the opening portion, wherein the cavity extends at least to a region under the masking portion; and separating the growth substrate from the epitaxial layer by applying stress between the epitaxial layer and the growth substrate. The cavity has a front end portion being in contact with the sacrificial layer and the masking portion, and a breaking plane in the masking portion, which is in contact with the front end, is formed while the growth substrate is separated from the epitaxial layer. Thus, a flaw in and damage to the epitaxial layer can be prevented by reducing the stress applied to the epitaxial and the growth substrate while the growth substrate is separated.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a growth substrate separation method using a stress,

The present invention relates to a growth substrate separation method and a semiconductor device manufacturing method, and more particularly, to a method of separating a growth substrate using stress applied between a growth substrate and an epi layer and a method of manufacturing a semiconductor device.

BACKGROUND ART Light emitting diodes (LEDs) are inorganic semiconductor devices that emit light generated by the recombination of electrons and holes. Recently, they have been used in various fields such as displays, automobile lamps, and general lighting.

The light emitting diode may be classified into a horizontal type light emitting diode and a vertical type light emitting diode according to an electrode formation position.

Although the horizontal flat type light emitting diode is relatively simple in manufacturing method, the light emitting area is reduced because a part of the active layer is removed to form the electrode of the lower semiconductor layer. In addition, current-leaking phenomenon occurs due to the horizontal arrangement of the electrodes, thereby reducing the light emitting efficiency of the light emitting diode. In addition, a sapphire substrate is widely used as a growth substrate for horizontal flat type light emitting diodes. However, the sapphire substrate has low thermal conductivity, so that heat emission of the light emitting diode is difficult. As a result, the junction temperature of the light emitting diode is increased and the internal quantum efficiency of the light emitting diode is lowered.

In order to solve such a problem of the horizontal type light emitting diode, a vertical type light emitting diode has been developed. In the vertical type light emitting diode, since the electrodes are vertically arranged and the growth substrate such as the sapphire substrate is separated, the problem of the horizontal type light emitting diode can be solved. In the vertical type light emitting diode, since the electrodes are arranged vertically, a step of separating the growth substrate during manufacturing is further required. Generally, a laser lift-off (LLO) technique is mainly used for growth substrate separation. Recently, a chemical lift-off (CLO) technique, a stress lift-off ) Technologies are being researched and developed.

However, when the growth substrate is separated using the laser lift-off, a crack may be generated in the semiconductor layer due to a strong energy laser. When a growth substrate of the same kind of material as the semiconductor layer is used (for example, Gallium substrate), it is difficult to apply the laser lift-off method because the energy band gap difference between the growth substrate and the semiconductor layer is small. In the case of chemical lift-off, the process reproducibility of the process of chemical etching between the substrate and the semiconductor layer deteriorates, and the process yield is not constant.

In order to overcome the disadvantages of the above-described laser lift-off and chemical lift-off, a technique for separating a substrate using stress lift off has been variously studied. When stress is used to separate the substrate, stress must be applied between the substrate and the epi layer to separate the epi layer from the growth substrate to a few to several tens of 탆 thick. In the process of applying stress, stress is applied to the epi layer, so that strain and cracks may occur in the epi layer, which degrades the quality of the epi layer. If the quality of the epi layer is lowered, the process yield may be reduced, and the light quantity of the manufactured light emitting diode may be lowered and reliability may be lowered. In addition, since the stress is applied to the growth substrate in the process of applying the stress, the substrate can not be easily reused due to damage or breakage particularly in the case of a brittle substrate. For example, GaN substrates are brittle and easily broken during stress separation. GaN substrates are very expensive, resulting in an increase in the overall process cost.

A problem to be solved by the present invention is to provide a growth substrate separation method that does not cause damage to an epitaxial layer and a growth substrate when a growth substrate is separated using stress.

Another object of the present invention is to provide a method of manufacturing a semiconductor device using a substrate separation method capable of easily separating a growth substrate using stress.

According to an embodiment of the present invention, a growth substrate separation method includes: forming a sacrificial layer on a growth substrate; Forming a mask layer on the sacrificial layer, the mask layer including a masking portion and an opening portion; Forming an epi layer on the sacrificial layer to cover the masking portion and forming a cavity in the sacrificial layer in the region below the opening portion, the cavity extending at least down to the region of the masking portion; Applying stress between the epitaxial layer and the growth substrate to separate the growth substrate from the epitaxial layer; The cavity includes a sacrificial layer and a front end portion in contact with the masking portion, and a breaking surface is formed in the masking portion in contact with the front end portion while the growth substrate is separated from the epilayer.

Accordingly, the stress is concentrated on the masking portion on the tip portion, and the magnitude of the stress applied to the epi layer and the growth substrate during the substrate separation process can be greatly reduced. Therefore, it is possible to prevent the occurrence of defects and damage in the epitaxial layer during the growth substrate separation process, and to prevent the growth substrate from being damaged or broken, thereby improving the process yield and reducing the process cost .

The growth substrate separation method may further include bonding the support substrate on the epi layer before separating the growth substrate.

The thermal expansion coefficient of the support substrate may be different from the thermal expansion coefficient of the epitaxial layer and stress may be applied between the epitaxial layer and the growth substrate during bonding of the support substrate.

Further, during the bonding of the supporting substrate, a stress is applied between the epi layer and the growth substrate, so that a crack is formed in the region above the tip of the masking portion.

Further, the breaking surface may be formed extending from the crack.

By further including bonding the supporting substrate, a crack can be formed in the masking portion during the bonding process, thereby further facilitating the growth substrate separation process.

The support substrate may comprise a metal.

Further, bonding the support substrate onto the epi layer may include Eutectic bonding, and the process bonding may be performed using AuSn.

In some embodiments, the breaking surface may be formed to be inclined from the lower surface of the masking portion toward the center of the masking portion.

The growth substrate separation method may further include electrochemically etching the sacrificial layer to form a microcavity in the sacrificial layer prior to forming the epilayer, .

In addition, before the electrochemical etching, an etch electrode is formed on the sacrificial layer; After the electrochemical etching, removing the etchant and the sacrificial layer under the etch electrode may be further included.

In other embodiments, the width of the masking portion may be equal to or less than the width of the opening portion.

The growth substrate separation method may further include forming a carrier substrate on the lower surface of the growth substrate before separating the growth substrate from the epi layer.

Accordingly, it is possible to prevent the growth substrate from being damaged or broken during the growth substrate separation process.

The carrier substrate may be a glass substrate, a silicon substrate, or a sapphire substrate.

According to another aspect of the present invention, there is provided a growth substrate separation method comprising: forming a sacrificial layer on a growth substrate; Forming a mask layer on the sacrificial layer, the mask layer including a masking portion and an opening portion; Forming an epi layer on the sacrificial layer to cover the masking portion and forming a cavity in the sacrificial layer in the area below the opening portion, the cavity extending at least to a region below the masking portion; And bonding a supporting substrate having a thermal expansion coefficient different from that of the growth substrate on the epilayer, wherein the cavity includes a front end portion in contact with the sacrificial layer and the masking portion, and bonding the supporting substrate on the epi layer A stress is applied between the epitaxial layer and the growth substrate and a braking surface in contact with the front end in the masking portion is formed to separate the support substrate from the epitaxial layer.

The thermal expansion coefficient of the support substrate may be greater than the thermal expansion coefficient of the epi layer.

Also, during bonding of the supporting substrate, the supporting substrate and the epi layer may be bowed.

Further, the support substrate and the epi layer may be bored, so that a crack may be formed at a portion where the masking portion is in contact with the front end portion, and the breaking surface may be formed extending from the crack.

According to another embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a sacrificial layer on a growth substrate; Forming a mask layer on the sacrificial layer, the mask layer including a masking portion and an opening portion; Forming an epi layer on the sacrificial layer to cover the masking portion and forming a cavity in the sacrificial layer in the region below the opening portion, the cavity extending at least down to the region of the masking portion; Applying stress between the epitaxial layer and the growth substrate to separate the growth substrate from the epitaxial layer; Wherein the cavity includes a sacrificial layer and a tip portion in contact with the masking portion, a braking surface in contact with the tip in the masking portion is formed while the growth substrate is separated from the epilayer, A first irregularity is formed on the surface of the layer.

The epi layer may include a first nitride semiconductor layer, an active layer, and a second nitride semiconductor layer.

The method may further include removing the epitaxial layer separated from the growth substrate to a predetermined thickness from the surface of the epitaxial layer to form a second irregularity on the surface of the epitaxial layer, wherein the second irregularity is gentler than the first irregularity It can be inclined.

According to the growth substrate separation method of the present invention, in the substrate separation process, the magnitude of the stress applied to the epi layer and the growth substrate can be greatly reduced. The stress applied to the epitaxial layer and the growth substrate is reduced and it is possible to prevent the occurrence of defects and damage in the epitaxial layer during the growth substrate separation process and to prevent the growth substrate from being damaged or damaged. Therefore, the process yield can be improved and the process cost can be reduced.

According to the semiconductor device manufacturing method using the growth substrate separation method, the crystalline quality of the semiconductor layers of the manufactured semiconductor device can be maintained to be excellent and the increase in defect density can be prevented, thereby improving the process yield. Further, it is possible to prevent the reduction of the efficiency and the reliability of the manufactured semiconductor device.

1 to 5 are sectional views illustrating a method of separating a substrate according to an embodiment of the present invention.
6 to 8 are cross-sectional views illustrating a method of separating a substrate according to another embodiment of the present invention.
9 and 10 are cross-sectional views illustrating a method of separating a substrate according to another embodiment of the present invention.
11 to 15 are sectional views for explaining a method of manufacturing a semiconductor device according to still another embodiment of the present invention.
16A and 16B are a plan view and a cross-sectional view for explaining the removal of the etching electrode in the embodiments of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can sufficiently convey the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, etc. of components may be exaggerated for convenience. It is also to be understood that when an element is referred to as being "above" or "above" another element, But also includes the case where there are other components in between. Like reference numerals designate like elements throughout the specification.

1 to 5 are sectional views illustrating a method of separating a substrate according to an embodiment of the present invention.

Referring to FIG. 1 (a), a sacrificial layer 120 is formed on a growth substrate 110.

The growth substrate 110 is not limited as long as it can grow semiconductor layers. For example, the growth substrate 110 may be a sapphire substrate, a silicon carbide substrate, a silicon substrate, a gallium nitride substrate, an aluminum nitride substrate, or the like. In particular, in this embodiment, the growth substrate 110 may be a gallium nitride substrate.

The sacrificial layer 120 may include a nitride semiconductor such as (Al, Ga, In) N and may be formed using a technique such as MOCVD (Metal Organic Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), or HVPE (Hydride Vapor Phase Epitaxy) May be grown on the growth substrate 110.

Further, the sacrificial layer 120 may be formed of an N-type or P-type nitride semiconductor layer including a high concentration impurity. For example, the sacrificial layer 120 may have a concentration of Si of 3 x 10 ¹⁸ / cm ³ or more, more preferably Si of 3 x 10 ¹⁸ / cm ³ To And may be an N-type GaN layer doped with 3 x 10 ¹⁹ / cm ³ . Accordingly, the microcavity can be formed in the sacrificial layer 120 by using an electro-chemical etching (ECE) process, which will be described later.

Next, referring to FIG. 1B, a mask layer 130 is formed on the sacrificial layer 120.

The mask layer 130 may include a masking portion 131 and an opening portion 133. A portion of the sacrificial layer 120 may be partially exposed by the opening portion 133. [ The masking portion 131 may include, but is not limited to, SiO ₂ , and may include another insulating material.

The mask layer 130 may be formed by depositing a SiO ₂ layer on the sacrificial layer 120 using, for example, E-beam evaporation and techniques and patterning the SiO ₂ layer to form the masking portion 131. [ And an opening portion 133. [0050] Further, by the patterning process, the masking portion 131 may have a trapezoidal cross-section as shown in the figure. However, the present invention is not limited thereto, and the mask layer 130 may be formed by other methods, and the masking portion 131 may have various shapes.

Meanwhile, the mask layer 130 includes the masking portion 131 and the opening portion 133, so that the mask layer 130 can be formed in various patterns. For example, as shown in FIG. 16A, the masking portion 131 and the opening portion 133 may be formed in a stripe shape so that the mask layer 130 may be formed in a stripe pattern. However, the present invention is not limited thereto, and the mask layer 130 may be formed in various patterns such as an island pattern and a mesh pattern.

The widths of the masking portion 131 and the opening portion 133 of the mask layer 130 are determined by the size of the cavity 140 in the subsequent process and the degree of lateral growth of the first nitride semiconductor layer 151 . ≪ / RTI > Particularly, the width of the masking portion 131 may be equal to or less than the width of the opening 133 or may be less than the width of the opening 133, have. For example, the width of the masking portion 131 may be about 4 占 퐉, and the width of the opening 133 may be about 8 占 퐉.

1 (c), sacrificial layer 120 is partially removed using electrochemical etching (ECE).

Hereinafter, the electrochemical etching process will be described in detail.

First, an etch electrode 410 is formed on the sacrificial layer 120. For example, as shown in FIG. 16A, three etching electrodes 410 may be formed on the sacrificial layer 120. Next, the growth substrate 110 on which the sacrifice layer 120 is formed and the cathode electrode (for example, Pt electrode) are immersed in the solution. The solution may be an electrolytic solution, for example, an electrolytic solution containing oxalic acid, HF or NaOH. When a certain voltage is applied to the etching electrode 410 and the cathode electrode, the sacrificial layer 120 is partially removed to form the microcavity 141 as shown in FIG. 1C. The microcavities 141 are formed in a region under the opening portion 133 and a sacrificial layer 120 under the edge region of the masking portion 131. In the electrochemical etching process, the masking portion 131 can serve as an etching mask, As shown in FIG.

In the electrochemical etching process, the size and formation area of the microcavity 141 can be controlled by selectively applying the composition and concentration of the solution, the voltage application time, and the applied voltage. For example, the sacrificial layer 120 may be partially etched by applying a voltage in the range of 10 to 60 V continuously to form the microcavities 141, and an electrochemical etching process for applying a voltage of two stages The microcavities 141 may be formed. For example, a voltage of 9V may be applied for 180 seconds in a one-step electrochemical etching process followed by a voltage of 16.5V for 180 seconds in a two-step electrochemical etching process. Thereby, as shown, a relatively small-sized microcavity is formed first, and a relatively-large-sized microcavity can be formed.

By using the two-step electrochemical etching process, the surface of the sacrificial layer 120 can maintain good crystallinity, and also the relatively large microcavity can be formed inside the sacrificial layer 120, Do.

The manufacturing method of the present embodiment further includes removing the sacrificial layer 120 of the etching electrode 410 and the region 410 'below the etching electrode after removing a part of the sacrificial layer 120 by the electrochemical etching process . 16B shows a cross section of the corresponding A-A 'after removing the sacrificial layer of the etching electrode 410 and the etching-under-electrode region 410' in FIG. 16A. Referring to FIG. 16B, after the electrochemical etching process is completed, the etching electrode 410 and the sacrificial layer 120 in the area 410 'under the etching electrode can be removed. The sacrificial layer 120 in the region 410 'under the etch electrode 410 is removed so that the upper surface of the growth substrate 110 can be exposed to the portion where the sacrificial layer 120 is removed.

In the process of separating the growth substrate 110, a region where the etching electrode 410 is formed may interfere with the separation of the growth substrate 110. Thus, after the electrochemical etching process is completed, the etching electrode 410 and the sacrificial layer 120 in the area below the etching electrode 410 are removed to prevent the etching electrode 410 from separating the growth substrate 110 Can be prevented. Accordingly, the process of separating the growth substrate 110 using the stress can be further facilitated.

Alternatively, the step of removing the etchant electrode 410 and the sacrificial layer 120 in the etch electrode lower region 410 'may be performed after the growth of the epitaxial layer 150 described later. In this case, the epi layer 150 in the region above the etch electrode 410 can be further removed.

Referring to FIGS. 2 and 3, an epi layer is formed on the sacrificial layer 120 to cover the masking portion 131, and a cavity 140 is formed in the sacrificial layer 120.

Referring to FIG. 2, a first nitride semiconductor layer 151 is formed on the sacrificial layer 120 to cover the masking portion 131.

The first nitride semiconductor layer 151 may be grown using techniques such as MOCVD, MBE, or HVPE. The first nitride semiconductor layer 151 may be grown using seeds of the sacrificial layer 120 whose upper surface is exposed by the opening 133. The first nitride semiconductor layer 151 may be grown not only in the vertical direction, . Accordingly, as shown in FIG. 2, the first nitride semiconductor layer 151 may be formed to cover the masking portion 131.

Also, during the growth of the first nitride semiconductor layer 151, the microcavities 141 may be joined together to form the cavity 140. Therefore, the cavity 140 is formed mainly in the region where the microcavity 141 was formed, and may be formed so as to have a region that is larger than the region where the microcavity 141 was formed. The cavity 140 may be formed in the sacrificial layer 120 in the area below the opening part 133 and further the cavity 140 may be extended to at least the area under the masking part 131. [ The cavity 140 is formed to extend to a region below the masking portion 131. The cavity 140 is formed in a shape below the side of the masking part 131 in the area below the masking part 131 so that the height decreases from the center toward the bottom of the masking part 131, thereby forming the tip part 145. The distal end 145 is formed at a portion where the cavity 140, the sacrificial layer 120, and the masking portion 131 are in contact with each other, and thus the cavity 140 may include the tip portion 145. 3, an active layer 153 and a second nitride semiconductor layer 155 are grown on the first nitride semiconductor layer 151 to form an epi-layer 150. Then, as shown in FIG.

The active layer 153 and the second nitride semiconductor layer 155 may be grown using techniques such as MOCVD, MBE, or HVPE, similar to the first nitride semiconductor layer 151.

Each of the semiconductor layers 151, 153, and 155 of the epi layer 150 may include (Al, Ga, In) N. In this embodiment, the first nitride semiconductor layer 151 may be an N-type semiconductor layer, the second nitride semiconductor layer 153 may be a P-type semiconductor layer, or vice versa. The active layer 153 may include a multiple quantum well structure (MQW), and the elements constituting the semiconductor layers and their composition may be adjusted so that the semiconductor layers forming the multiple quantum well structure emit light of a desired peak wavelength have.

The first nitride semiconductor layer 151 may include an un-doped layer and a doped layer. When forming the first nitride semiconductor layer 151, the undoped layer may be grown first, and then the doped layer may be formed so that the first nitride semiconductor layer 151 includes multiple layers. Thus, by initially growing the undoped layer at the initial stage of the formation of the first nitride semiconductor layer 151, the crystal quality of the first nitride semiconductor layer 151 can be improved.

Hereinafter, a description of well-known technical terms relating to the semiconductor layers 151, 153, and 155 including the nitride semiconductor material will be omitted.

Next, referring to FIG. 4, the supporting substrate 171 may be bonded onto the second nitride semiconductor layer 155. Further, a bonding layer 160 for bonding the support substrate 171 and the epi-layer 150 may be further formed.

The supporting substrate 171 may be an insulating substrate, a conductive substrate, or a circuit substrate. For example, the supporting substrate 171 may be a sapphire substrate, a nitride substrate, a glass substrate, a silicon carbide substrate, a silicon substrate, a metal substrate, a ceramic substrate, or a PCB substrate. . ≪ / RTI > The thermal expansion coefficient of the support substrate 171 may be different from the thermal expansion coefficient of the epi-layer 150. When the supporting substrate 171 includes a metal, it may be formed as a multilayer. For example, the support substrate 171 may be a Cu layer bonded to the upper surface and the lower surface of the Mo layer. Thus, by forming the supporting substrate 171 to include two or more kinds of metal layers, the thermal expansion coefficient of the supporting substrate 171 can be adjusted.

Bonding the support substrate 171 onto the epi layer 150 may include eutectic bonding the support substrate 171 and may be eutectic bonded using AuSn, for example. . Accordingly, the bonding layer 160 may include AuSn.

Eutectic bonding using AuSn is performed by heating AuSn to a temperature of about Eutectic temperature (about 280 ° C) (for example, about 350 ° C) and then heating the AuSn to the epi layer 150 May be performed by disposing the support member between the support substrate 171 and cooling the AuSn. At this time, when the thermal expansion coefficient of the support substrate 171 is different from that of the epi layer 150, the volume change rate of the support substrate 171 and the epi layer 150 caused by the temperature change in the bonding process is changed. Accordingly, stress may be applied between the epi layer 150, the sacrificial layer 120, the masking portion 131, and the growth substrate 110, and in particular, between the growth substrate 110 and the epi layer 150, . The stress can be particularly concentrated on the tip end 145 of the cavity 140 and thus a crack C can be generated in the region above the tip end 145 of the masking portion 131. Specifically, there is a sharp change in the cross-sectional shape at the tip portion 145 of the cavity 140, and stress concentration occurs around the tip 145 in the bonding process. The stress acting on the region of the masking portion 131 on the tip end portion 145 sharply increases due to the stress concentration, and thus a crack C may occur.

However, the above description corresponds to an example of the present invention, and the present invention includes all the methods using a bonding method using another material accompanied by a temperature change.

The manufacturing method may further include forming a metal layer (not shown) on the epi layer 150 before forming the supporting substrate 171.

The metal layer (not shown) may include a reflective metal layer and a barrier metal layer, and the barrier metal layer may be formed to cover the reflective metal layer. The metal layer may be formed using a deposition and lift-off technique or the like.

The reflective metal layer may serve to reflect light, and may also serve as an electrode electrically connected to the epi layer 160. Accordingly, the reflective metal layer preferably includes a material capable of forming an ohmic contact with high reflectivity. The reflective metal layer may include, for example, a metal containing at least one of Ni, Pt, Pd, Rh, W, Ti, Al, Ag and Au. In addition, the barrier metal layer prevents interdiffusion of the reflective metal layer and other materials. Thus, it is possible to prevent an increase in contact resistance and a reduction in reflectivity due to damage to the reflective metal layer. The barrier metal layer may include Ni, Cr, Ti, and may be formed of multiple layers.

5, stress is applied between the epitaxial layer 150 and the growth substrate 110 to separate the growth substrate 110 from the epitaxial layer 150. Referring to FIG. At this time, a braking surface B contacting the front end portion 145 may be formed in the masking portion 131. In addition, since the stress can be concentrated on the portion where the crack C is formed, the breaking surface B may be formed extending from the crack C.

The masking portion 131 may be broken along the breaking surface B to be separated into the lower masking portion 131a and the upper masking portion 131b and formed on the lower surface of the sacrificial layer 120 and the lower surface of the epilayer 150, . The breaking surface B may be formed to be inclined in the direction of the center of the masking portion 131 on the lower surface of the masking portion 131, as shown in FIG. The growth substrate 110 can be separated from the epitaxial layer 150 by breaking the masking portion 131 into the lower masking portion 131a and the upper masking portion 131b.

According to the present embodiment, a crack C is generated in the masking portion 131 in the process of bonding the support substrate 171, and the stress C applied from the crack C The masking portion 131 is broken along the breaking surface B so that the growth substrate 110 is separated from the epi-layer 150. In particular, since the stress applied to the crack C and the tip end portion 145 is concentrated, the stress transmitted to the portions other than the masking portion 131, that is, the epi layer 150 and the growth substrate 150 is greatly reduced. Therefore, it is possible to prevent cracks and defects from being generated in the epi-layer 150, thereby preventing the yield from being lowered and preventing the growth substrate 110 from being damaged or cracked. Furthermore, the characteristics of the semiconductor device manufactured using the method of separating a substrate of the present invention can be remarkably improved. For example, when manufacturing a light emitting device, it is possible to prevent the light emitting device from lowering in light quantity and lowering reliability. In addition, since the growth substrate 110 can be separated from the epi layer 150 without damaging or breaking, the growth substrate 110 can be reused, thereby reducing the process cost.

However, the manufacturing method according to the present embodiment includes forming a crack in the masking portion 131 using a bonding process, but the present invention is not limited thereto. That is, it is also included in the present invention that the growth substrate 110 is separated from the epitaxial layer 150 without bonding the support substrate 171 to the epitaxial layer 150. In this case also, stress is concentrated on the tip end portion 145 of the cavity 140 while the stress is applied to separate the growth substrate 110 from the epi layer 150, so that the breaking surface B is formed on the masking portion 131, Can be formed.

6 to 8 are cross-sectional views illustrating a method of separating a substrate according to another embodiment of the present invention.

The present embodiment is substantially similar to the embodiments of FIGS. 1 to 5, but differs in that it further includes forming the carrier substrate 180 on the lower surface of the growth substrate 110 before separating the growth substrate 110 . Hereinafter, the above difference will be mainly described.

6, a sacrificial layer 120, a masking portion 131, an epilayer 150, and a support substrate 171 are formed on a growth substrate 110 in a similar manner to that described with reference to FIGS. .

Referring to FIG. 7, a carrier substrate 180 is formed on the lower surface of the growth substrate 110.

The carrier substrate 180 is not limited as long as it can be attached to the bottom surface of the growth substrate 110, and may be, for example, a silicon substrate, a glass substrate, a sapphire substrate, or the like. In particular, the carrier substrate 180 preferably has a lower brittleness than the growth substrate 110, and is preferably a substrate having a lower elongation than the growth substrate 110.

8, the growth substrate 110 is separated from the epi layer 150, as described with reference to FIG.

According to this embodiment, by forming the carrier substrate 180 having a lower brittleness and / or a lower deposition rate on the lower surface of the growth substrate 110, it is possible to prevent the substrate having a high brittleness such as the GaN substrate from being damaged It is possible to prevent breakage. Therefore, the separated growth substrate 110 can be reused. Particularly, a relatively inexpensive carrier substrate (for example, a glass substrate, a sapphire substrate or the like) is attached to an expensive substrate such as a GaN substrate to prevent damage or breakage of an expensive substrate, thereby further reducing the processing cost.

9 and 10 are cross-sectional views illustrating a method of separating a substrate according to another embodiment of the present invention.

The present embodiment is substantially similar to the embodiment of FIGS. 1 to 5 except that in the process of bonding the support substrate 173 to the epitaxial layer 150, the growth substrate 110 is separated from the epitaxial layer 150 . Hereinafter, the above difference will be mainly described.

9, a sacrificial layer 120, a masking portion 131, an epilayer 150, and a support substrate 171 are formed on a growth substrate 110 in a similar manner to that described with reference to FIGS. . At this time, when the thermal expansion coefficient of the support substrate 171 is larger than the thermal expansion coefficient of the epi-layer 150, bowing occurs as shown in FIG. The stress is concentrated on the tip end portion 145 by the bowsing due to the lowering of the temperature so that a crack C is generated in the masking portion 131 and the stress is further increased as the temperature is lowered to form the braking surface B The masking portion 131 may be broken. Therefore, according to this embodiment, the growth substrate 110 can be separated from the epitaxial layer, as shown in FIG. 10, in the bonding process of the supporting substrate 173, even if no additional stress is applied after the supporting substrate 173 is formed .

According to this embodiment, a separate stress applying process for separating the growth substrate 110 can be omitted. Therefore, the substrate separation process time can be shortened.

11 to 15 are sectional views for explaining a method of manufacturing a semiconductor device according to still another embodiment of the present invention. The semiconductor device manufacturing method according to the present embodiment can use the substrate separating method described in the above embodiments.

Referring to FIG. 11, after the growth substrate 110 is separated from the epitaxial layer 150 using the above-described embodiments, the epitaxial layer 150 and the support substrate 170 are prepared. The epi layer 150 and the supporting substrate 170 shown in Fig. 11 are shown upside down and vice versa, as compared with those shown in the above-described embodiments.

When the growth substrate 110 is separated, first irregularities 210 corresponding to the separated shape are formed on the first nitride semiconductor layer 151. Further, the upper mask layer 131b may remain on the concave portion 210 of the first concave and convexity 210, and a part of the sacrifice layer 120 may remain on the convex portion 210 of the first concave and convex portion 210.

12, residues on the surface of the first nitride semiconductor layer 151 are chemically or physically removed, and the first nitride semiconductor layer 151 is removed to a predetermined thickness from the surface thereof.

The first nitride semiconductor layer 151 may be removed from the surface thereof by a predetermined thickness, for example, about 7 to 9 μm by dry etching or the like, thereby forming the first nitride semiconductor layer 151 may have a second concavo-convex surface 220 formed thereon. The second irregularities 220 may include recesses and protrusions corresponding to the first irregularities 210 and the second irregularities 220 may have a gentle inclination relative to the first irregularities 210.

Since the first nitride semiconductor layer 151 is grown along with the lateral growth from the surface of the sacrifice layer 120, crystallinity may be somewhat lowered around the surface of the first nitride semiconductor layer 151. Also, defects or damage may occur around the surface of the first nitride semiconductor layer 151 in the process of separating the growth substrate 110. Therefore, by removing a predetermined thickness of the surface of the first nitride semiconductor layer 151, the average crystal quality of the entire first nitride semiconductor layer 151 can be improved.

Referring to FIG. 13, the roughness R of the surface of the first nitride semiconductor layer 151 may be increased to form the roughness R. (R) wet etching or the like, and may be, for example, photo-enhanced chemical (PEC) etching, etching using a sulfuric acid phosphoric acid solution, or the like. The size of the roughness R may be variously determined depending on the etching conditions, for example, the average height may be 0.5 탆 or less. By forming the roughness R, the light extraction efficiency of the semiconductor device manufactured by the present manufacturing method can be improved.

14, the epi-layer 150 is patterned to form the element partition region 310. [ The patterning may be performed using dry etching. By forming the element region 310, a part of the bonding layer 160 can be exposed, and the epi layer 150 can be divided into at least one element region 10.

On the other hand, although not shown, a passivation layer (not shown) covering the upper surface and the side surface of the device region 10 can be further formed. The passivation layer can protect the semiconductor device from the outside and also can smooth the inclination of the roughness R on the surface of the first nitride semiconductor layer 151 to improve the light extraction efficiency.

15, an electrode 230 is formed on each device region 10, and a bonding layer 160 and a supporting substrate 170 under the device dividing region 310 are divided. As shown in FIG. 15, A plurality of semiconductor elements 20 are provided.

In the embodiment described with reference to the drawings, a roughness R is also formed on a region where the electrode 230 is formed. However, the roughness R may not be formed in the region where the electrode 230 is formed on the surface of the first nitride semiconductor layer 151. [

Specifically, before the surface roughness of the first nitride semiconductor layer 151 is increased, an electrode formation region where the electrode 230 is to be formed is defined to form an etching mask pattern in the electrode formation region. Etching mask pattern is, for example, may include SiO _2. Then, the surface roughness of the first nitride semiconductor layer 151 is increased by wet etching or the like. At this time, since the region where the etching mask pattern is formed is not etched, the surface roughness may not be increased. Thereafter, the etch mask pattern is removed, the epi-layer 150 is patterned to form the element isolation region 310, and then the electrode 230 is formed on the region where the roughness R is not formed have.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, Variations and changes are possible.

Claims (20)

Forming a sacrificial layer on the growth substrate;
Forming a mask layer on the sacrificial layer, the mask layer including a masking portion and an opening portion;
Forming an epi layer on the sacrificial layer to cover the masking portion and forming a cavity in the sacrificial layer in the region below the opening portion, the cavity extending at least down to the region of the masking portion;
Applying stress between the epitaxial layer and the growth substrate to separate the growth substrate from the epitaxial layer;
Wherein the cavity includes a sacrificial layer and a tip portion in contact with the masking portion,
And a braking surface in contact with the tip end portion in the masking portion is formed while the growth substrate is separated from the epilayer. The method according to claim 1,
Before separating the growth substrate,
And bonding the support substrate on the epi layer. The method of claim 2,
The thermal expansion coefficient of the support substrate is different from the thermal expansion coefficient of the epi layer,
Wherein stress is applied between the epitaxial layer and the growth substrate during bonding of the supporting substrate. The method of claim 3,
Wherein stress is applied between the epitaxial layer and the growth substrate during bonding of the supporting substrate to form a crack in a region on the tip of the masking portion. The method of claim 4,
Wherein the breaking surface extends from the crack. The method of claim 3,
Wherein the support substrate comprises a metal. The method of claim 6,
Bonding the support substrate onto the epi layer may include eutectic bonding,
Wherein the process bonding is performed using AuSn. The method according to claim 1 or 5,
Wherein the braking surface is formed to be inclined from the lower surface of the masking portion toward the center of the masking portion. The method according to claim 1,
Before forming the epi layer,
Further comprising electrochemically etching the sacrificial layer to form a microcavity in the sacrificial layer,
Wherein the cavity is formed by merging or extending the microcavities. The method of claim 9,
Forming an etch electrode on the sacrificial layer prior to the electrochemical etching;
Further comprising removing the sacrificial layer in the area below the etching electrode and the etching electrode after the electrochemical etching. The method according to claim 1,
Wherein a width of the masking portion is equal to or smaller than a width of the opening portion. The method according to claim 1,
Before separating the growth substrate from the epi layer,
And forming a carrier substrate on the lower surface of the growth substrate. The method of claim 12,
Wherein the carrier substrate is a glass substrate, a silicon substrate, or a sapphire substrate. Forming a sacrificial layer on the growth substrate;
Forming a mask layer on the sacrificial layer, the mask layer including a masking portion and an opening portion;
Forming an epi layer on the sacrificial layer to cover the masking portion and forming a cavity in the sacrificial layer in the area below the opening portion, the cavity extending at least to a region below the masking portion;
And bonding a supporting substrate having a thermal expansion coefficient different from that of the growth substrate to the epi layer,
Wherein the cavity includes a sacrificial layer and a tip portion in contact with the masking portion,
During bonding of the support substrate on the epi layer,
A stress is applied between the epi layer and the growth substrate,
And a braking surface in contact with the tip in the masking portion is formed to separate the support substrate from the epi layer. 15. The method of claim 14,
Wherein a thermal expansion coefficient of the support substrate is larger than a thermal expansion coefficient of the epi layer. 16. The method of claim 15,
Wherein the supporting substrate and the epi layer are bowed while bonding the supporting substrate. 18. The method of claim 16,
A crack is formed in a portion where the masking portion is in contact with the tip end portion by bending the support substrate and the epi layer,
Wherein the breaking surface extends from the crack. Forming a sacrificial layer on the growth substrate;
Forming a mask layer on the sacrificial layer, the mask layer including a masking portion and an opening portion;
Forming an epi layer on the sacrificial layer to cover the masking portion and forming a cavity in the sacrificial layer in the region below the opening portion, the cavity extending at least down to the region of the masking portion;
Applying stress between the epitaxial layer and the growth substrate to separate the growth substrate from the epitaxial layer;
Wherein the cavity includes a sacrificial layer and a tip portion in contact with the masking portion,
A breaking surface is formed in the masking portion in contact with the front end portion while the growth substrate is separated from the epi layer,
Wherein a first unevenness is formed on a surface of the epi layer where the growth substrate is separated. 19. The method of claim 18,
Wherein the epitaxial layer includes a first nitride semiconductor layer, an active layer, and a second nitride semiconductor layer. 19. The method of claim 18,
Further comprising removing the epitaxial layer from which the growth substrate has been separated to a predetermined thickness from the surface thereof to form a second irregularity on the surface of the epitaxial layer,
And the second irregularities have a gentler slope than the first irregularities.

Images