KR20140085643A - Data storage device and operating method thereof - Google Patents

Data storage device and operating method thereof Download PDF

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Publication number
KR20140085643A
KR20140085643A KR1020120153521A KR20120153521A KR20140085643A KR 20140085643 A KR20140085643 A KR 20140085643A KR 1020120153521 A KR1020120153521 A KR 1020120153521A KR 20120153521 A KR20120153521 A KR 20120153521A KR 20140085643 A KR20140085643 A KR 20140085643A
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South Korea
Prior art keywords
sector
address
physical address
data
sector addresses
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KR1020120153521A
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Korean (ko)
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엄기표
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에스케이하이닉스 주식회사
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Priority to KR1020120153521A priority Critical patent/KR20140085643A/en
Publication of KR20140085643A publication Critical patent/KR20140085643A/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits

Abstract

The present technology relates to a data storage device, and more specifically, to a data storage device with enhanced operation speed and an operation method thereof. The operation method of the data storage device includes the steps of mapping the sector addresses of a host device to the physical address offsets, and mapping the starting sector address of the consecutive sector addresses to the starting physical address offset when a write operation regarding the consecutive sector addresses is requested from the host device, and sequentially mapping the rest of the sector addresses the rest of the physical address offsets.

Description

≪ Desc / Clms Page number 1 > DATA STORAGE DEVICE AND OPERATING METHOD THEREOF &

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data storage device, and more particularly, to a data storage device having an improved operation speed and a method of operating the same.

Recently, a paradigm for a computer environment has been transformed into ubiquitous computing, which enables a computer system to be used whenever and wherever. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers is rapidly increasing. Such portable electronic devices typically use a data storage device that utilizes a memory device. The data storage device is used as a main storage device or an auxiliary storage device of a portable electronic device.

The data storage device using the memory device is advantageous in that it has excellent stability and durability because it has no mechanical driving part, has very high access speed of information and low power consumption. A data storage device having such advantages includes a USB (Universal Serial Bus) memory device, a memory card having various interfaces, and a solid state drive (SSD).

BACKGROUND ART [0002] As portable electronic devices reproduce large-capacity files such as music, moving pictures, etc., data storage devices are required to have a large storage capacity. A data storage device includes a plurality of memory devices to increase storage capacity. For a data storage device comprising a plurality of memory devices, a large storage capacity as well as a fast operating speed is one of the important characteristics of the data storage device.

The data storage device may include a plurality of memory devices to secure a large storage capacity. The data storage device can use a buffer program method in order to secure a fast operation speed. For example, the data storage device can divide the storage area of a plurality of memory devices into a buffer area (or a log area) and a main area. The data storage device may program the input data into the buffer area and then program the data programmed in the buffer area into the main area at the idle time.

An embodiment of the present invention is to provide a data storage device with improved operation speed and a method of operation thereof.

A method of operating a data storage device including a nonvolatile memory device according to an embodiment of the present invention includes mapping a sector address of a host device to a physical address offset of the nonvolatile memory device, When writing to addresses is requested, the start sector address of the consecutive sector addresses is mapped to the start offset of the physical address, and the remaining sector addresses are sequentially mapped to the remaining offsets of the physical address.

A data storage device according to an embodiment of the present invention includes a nonvolatile memory device; And

Wherein the controller is configured to map the sector addresses of the host device to the offsets of the physical address of the non-volatile memory device, wherein the controller is further configured to map successive sector addresses If the write is requested, mapping the starting sector address of the consecutive sector addresses to the starting offset of the physical address and sequentially mapping the remaining sector addresses to the remaining offsets of the physical address.

According to the embodiment of the present invention, the operation speed of the data storage device can be improved.

1 is a block diagram illustrating an exemplary data processing system including a data storage device in accordance with an embodiment of the present invention.
Figure 2 is a block diagram illustrating an exemplary data storage controller of Figure 1;
3 is a diagram showing a control hierarchical structure of the data processing system of FIG.
4 is a view for explaining an address misalignment phenomenon generated in the data storage device of FIG.
5 is a view for explaining a method of operating a data storage device according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish it, will be described with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. The embodiments are provided so that those skilled in the art can easily carry out the technical idea of the present invention to those skilled in the art.

In the drawings, embodiments of the present invention are not limited to the specific forms shown and are exaggerated for clarity. Although specific terms are used herein, It is to be understood that the same is by way of illustration and example only and is not to be taken by way of limitation of the scope of the appended claims.

The expression " and / or " is used herein to mean including at least one of the elements listed before and after. Also, the expression " coupled / coupled " is used to mean either directly connected to another component or indirectly connected through another component. The singular forms herein include plural forms unless the context clearly dictates otherwise. Also, as used herein, "comprising" or "comprising" means to refer to the presence or addition of one or more other components, steps, operations and elements.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a block diagram illustrating an exemplary data processing system including a data storage device in accordance with an embodiment of the present invention. Referring to FIG. 1, a data processing system 100 includes a host device 110 and a data storage device 120.

Illustratively, host device 110 includes portable electronic devices such as mobile phones, MP3 players, or the like, or electronic devices such as laptop computers, desktop computers, gaming devices, TVs, beam projectors, and the like.

The data storage device 120 is configured to operate in response to a request from the host device 110. [ The data storage device 120 is configured to store data accessed by the host device 110. That is, the data storage device 120 may be used as the main storage device or the auxiliary storage device of the host device 110. [

The data storage device 120 includes a controller 130 and a non-volatile memory device 140. The controller 130 and the data storage medium 140 may be a memory device connected to the host device 110 through various interfaces. Alternatively, the controller 130 and the data storage medium 140 may be configured as a solid state drive (SSD).

The controller 130 is configured to control the non-volatile memory device 140 in response to a request from the host device 110. [ For example, the controller 130 is configured to provide data read from the non-volatile memory device 140 to the host device 110. [ As another example, the controller 130 is configured to store data provided from the host device 110 in the non-volatile memory device 140. For this operation, the controller 130 is configured to control the read, program (or write) and erase operations of the non-volatile memory device 140.

Illustratively, the non-volatile memory device 140 will be configured as a flash memory device. The nonvolatile memory device 140 is divided into a first area 141 and a second area 142. Each of the first region 141 and the second region 142 includes a plurality of memory cells. Each of these memory cells may store 1-bit data or 2-bit or more data per cell. A memory cell capable of storing 1-bit data is called a single level cell (SLC). The single level cell SLC is programmed to have an erase state and a threshold voltage corresponding to one program state. A memory cell capable of storing two or more bits of data is called a multi level cell (MLC). The multi-level cell (MLC) is programmed to have a threshold voltage corresponding to either an erase state and a plurality of program states.

The number of bits that can be stored per cell of the memory cells included in the first area 141 is smaller than the number of bits that can be stored per cell of the memory cells belonging to the second area 142. [ For example, the memory cells included in the first area 141 may store 1-bit data per cell, and the memory cells included in the second area 142 may store 2-bit or more data per cell. As another example, the memory cells included in the first region 141 may store 2-bit data per cell, and the memory cells included in the second region 142 may store 3-bit or more data per cell.

Since the number of bits that can be stored per cell of the memory cells included in the first area 141 and the second area 142 is different from each other, the first area 141 and the second area 142 are formed in different types of memory Device. For example, the first area 141 may be comprised of a single level cell (SLC) memory device. And the second region 142 may comprise a multi-level cell (MLC) memory device. As another example, the first area 141 and the second area 142 may be configured as a hybrid memory device. Here, the hybrid memory device means a memory device in which a memory cell can be selected and used as either a single level cell (SLC) or a multi-level cell (MLC). In this case, the first region 141 may be used in a single level cell (SLC) manner and the second region 142 may be used in a multilevel cell (MLC) manner.

Since the number of bits that can be stored per cell of the memory cells included in the first area 141 and the second area 142 is different from each other, Cells are accessed in different ways. Illustratively, assume that the memory cells included in the first region 141 store 1-bit data per cell and the memory cells belonging to the second region 142 store 2-bit data per cell. In this case, the memory cells included in the first area 141 are programmed in a single level cell (SLC) manner, and the memory cells included in the second area 142 can be programmed in a multi-level cell (MLC) . In addition, the memory cells included in the first area 141 may be read by a single level cell (SLC) method, and the memory cells included in the second area 142 may be read by a multi-level cell (SLC) method.

Since the number of bits that can be stored per cell of the memory cells included in the first area 141 is smaller than the number of bits that can be stored per cell of the memory cells included in the second area 142, The program speed will be faster than the program speed of the memory cells included in the second area 142. [

Using this characteristic, the controller 130 preferentially programs the data provided from the host device 110 in the first area 141. [ This is defined as buffer programming (BP). Optionally, the first area 141 used for buffer programming BP may be referred to as a buffer area or a log area. The controller 130 programs the data temporarily stored in the first area 141 into the second area 142 after transmitting the response to the write request to the host device 110. [ For example, the controller 130 programs the data stored in the first area 141 in the second area 142 during the idle time that the host device 110 does not request. This is defined as main programming (MP). In some cases, the second area 142 used in the main program (MP) may be referred to as a data area.

When host device 110 rotor-provided data is programmed through a buffer programming (BP) operation and a main programming (MP) operation, host device 110 can respond quickly to write or read requests. Accordingly, the operation speed of the data storage device 120 can be accelerated.

According to the buffer programming BP according to the embodiment of the present invention, when successive sector-by-sector data (hereinafter referred to as "sector data") is transmitted from the host device 110, A logical address is mapped (or assigned) to a physical address so that the sector data transferred within a data processing unit (e.g., page) can be processed. When the transferred sector data is stored, attribute information, i.e., metadata, related to the physical address (PA) to which the sector data is originally stored is added. This buffer programming (BP) method will be described in detail below.

Figure 2 is a block diagram illustrating an exemplary data storage controller of Figure 1; 3 is a diagram showing a control hierarchical structure of the data processing system of FIG. In the description of Figures 2 and 3, the non-volatile memory device (140 of Figure 1) is illustrated as being comprised of a flash memory device.

Referring to FIG. 2, the controller 130 includes a micro controller unit (MCU) 131 and an operation memory unit 135. It will be appreciated, however, that the components of controller 130 are not limited to the components mentioned. For example, the controller 130 may further include a host interface, a memory interface, an error correction code unit (ECC unit), and the like. The operational memory device 135 includes at least one of a cache, DRAM, SRAM, ROM, NOR flash memory devices.

The flash memory device 140 performs a read or program operation on a page basis due to its structural features. The flash memory device 140 performs an erase operation on a block-by-block basis due to its structural feature. In addition, the flash memory device 140 is not overwritable. That is, the memory cell of the flash memory device 140 in which data is stored must be erased in order to store new data.

Due to these features of the flash memory device 140, the data storage device (120 in FIG. 1) is disk emulation software to ensure compatibility with the data processing unit with the host device (110 in FIG. 1) Called for additional software. That is, the MCU 131 is configured to drive a Flash Translation Layer (FTL) to process a request from the host device (see 110 in FIG. 1). This flash translation layer (FTL) is loaded into the operation memory device 135 and driven.

The flash translation layer (FTL) is a read-only flash memory device, such as a flash memory device, that is readable and writable by the flash memory device so that the data storage device 120 can be operated in response to a requested access from the file system of the host device 110 , Erase operation, and the like. Accordingly, the file system of the host device 110 can recognize the data storage device 120 including the flash memory device as a general data storage device, for example, a block device.

As shown in FIG. 3, the host device 110 is composed of a software layer including an application (or operating system) 111 and a file system 112. The data storage device 120 is composed of a software layer including a flash conversion layer 135 and a hardware layer including a flash memory device 140.

When data (or a file) is requested to be read or written from the application 111, the file system 112 provides a sector address for accessing the data to the data storage device 120. The sector address is inconsistent with the physical address of the flash memory device 140 because it is the address system managed by the file system 112.

The flash translation layer 135 assigns the sector address provided from the file system 112 to the logical address managed by the flash translation layer 135. [ The flash translation layer (FTL) maps the logical address assigned to the sector address to the physical address of the flash memory device 140. That is, the sector address requested from the host device 110 is converted to the physical address of the flash memory device 140 based on the address mapping table 137 of the flash conversion layer 135.

4 is a view for explaining an address misalignment phenomenon generated in the data storage device of FIG.

The file system (112 in Fig. 3) of the host apparatus 110 uses a sector as a minimum unit for data processing. The flash memory device 140 uses a page as a read or a program processing unit, as described above. Generally, a sector has a size of 512-byte (Byte). And the page may have a size of 512 bytes or more depending on the storage capacity of the flash memory device 140. [ That is, the sizes of sectors and pages are different. Since the unit of processing data of the host device 110 and the flash memory device 140 are different from each other, the sector address and the start address of the page of the flash memory device 140 may be misaligned with each other.

The address misalignment phenomenon will be described in more detail below with reference to FIG. 4, the physical page of the flash memory device 140 has a size of 4 kilobytes (KB), and the logical page of the flash translation layer (FTL) mapped to the physical page is also 4 kilobytes (KB) Size. According to this assumption, up to eight sector addresses can be assigned to a physical address corresponding to one physical page or a logical address corresponding to one logical page.

A case where a write request is generated for the continuous sector data SD5 to SD8 from the file system 112 of the host apparatus 110 will be exemplified. In this case, the file system 112 provides the number of sector addresses 4 including the starting sector address SA5 and the starting sector address SA5 to the data storage 120, i.e., the flash translation layer (FTL) .

The flash translation layer (FTL) maps the logical address assigned to the sector address to the physical address based on the address mapping table. For example, the flash translation layer (FTL) maps the logical address LA0 assigned to the sector address SA5 to the physical address PA33. The flash translation layer (FTL) maps the logical address (LA0) assigned to the sector address (SA6) to the physical address (PA33). The flash translation layer (FTL) maps the logical address (LA0) assigned to the sector address (SA7) to the physical address (PA33). The flash translation layer (FTL) maps the logical address LA1 assigned to the sector address SA8 to the physical address PA34.

According to the mapping result, the sector data is stored in the allocated area of the physical address to which the corresponding sector address is mapped. As described above, a maximum of eight sector addresses can be assigned to a physical address. To simplify the allocation of the sector address, a sector address is assigned so that the offset between the sector address and the physical address is matched, and the sector data can be stored in the allocated area. For example, the sector data SD5 corresponding to the sector address SA5 is stored in the storage area of the offset 5 of the physical address PA33. The sector data SD6 corresponding to the sector address SA6 is stored in the storage area of the offset 6 of the physical address PA33. The sector data SD7 corresponding to the sector address SA7 is stored in the storage area of the offset 7 of the physical address PA33. The sector data SD8 corresponding to the sector address SA8 is stored in the storage area of the offset 0 of the physical address PA34 continuous to the physical address PA33 since there is no matching offset.

Since the sector and page size are different and the sector address is assigned to match the offset of the physical address, a storage area of the physical address to which the sector address is not allocated may be generated. For example, if the sector address is the same as the storage areas corresponding to the offsets (0 to 4) of the physical address PA33 and the storage areas corresponding to the offsets (1-7) of the physical address PA34 An unallocated area may be generated. This occurs because the start address of the physical address, that is, the sector address is not allocated from the start offset (0) of the physical address. That is, this is a phenomenon that occurs because the sector address is not aligned with the start offset of the physical address. This phenomenon is defined as an address sub-alignment phenomenon.

If an address misalignment phenomenon occurs, data can not be stored and wasted areas may be generated. In addition, the operation speed of the flash memory device 140 may be lowered because sector data of a size that can be stored in a storage area of one physical address can be stored and distributed in storage areas of several physical addresses.

5 is a view for explaining a method of operating a data storage device according to an embodiment of the present invention. 5, the physical page of the flash memory device 140 has a size of 4 kilobytes (KB) and the logical page of the flash translation layer (FTL) mapped to the physical page is also 4 kilobytes (KB) Size. According to this assumption, up to eight sector addresses can be assigned to a physical address corresponding to one physical page or a logical address corresponding to one logical page.

A case where a write request is generated for the continuous sector data SD5 to SD8 from the file system 112 of the host apparatus 110 will be exemplified. In this case, the file system 112 provides the number of sector addresses 4 including the starting sector address SA5 and the starting sector address SA5 to the data storage 120, i.e., the flash translation layer (FTL) .

According to the embodiment of the present invention, when writing is requested to the consecutive sector addresses SA5 to SA8, the start sector address SA5 of the consecutive sector addresses SA5 to SA8 is set to the start offset of the physical address And sequentially maps the remaining sector addresses (SA6 to SA8) to the remaining offsets of the physical address. That is, when the continuous sector data (SD5 to SD8) is transmitted, the flash conversion layer (FTL) can store the transmitted sector data (SD5 to SD8) in a page corresponding to one physical address , A sector address or a logical address is mapped to a physical address.

The flash conversion layer FTL is configured to store the sector addresses SD5 to SD8 corresponding to the sector addresses SA5 to SA8 assigned to the different logical addresses LA0 and LA1 in the same physical address PA33 . For example, the flash translation layer (FTL) maps the sector address SA8 assigned to the different logical address LA1 among the transferred sector addresses SA5 to SA8 to the sector address SA8 assigned to the remaining sector addresses SA5 to SA7, To the physical address PA33. In this case, the flash translation layer FTL transfers the address alignment flag AAF to the logical address LA1 to which the sector address SA8 mapped to the same physical address PA34 as the remaining sector addresses SA5 to SA7 is allocated. .

According to the address mapping result, the sector data is stored in the allocated area of the physical address to which the corresponding sector address is mapped. At this time, the sector data (SD) is stored without matching the offset between the sector address and the physical address so that the address misalignment does not occur. For example, the sector data SD5 corresponding to the sector address SA5 is stored in the storage area of the offset 0 of the physical address PA33. The sector data SD6 corresponding to the sector address SA6 is stored in the storage area of the offset 1 of the physical address PA33. The sector data SD7 corresponding to the sector address SA7 is stored in the storage area of the offset 2 of the physical address PA33. The sector data SD8 corresponding to the sector address SA8 is stored in the storage area of the offset 3 of the physical address PA33.

Since the sector data is stored such that the offset between the sector address and the physical address does not match, address information associated with the sector address is additionally stored when the sector data is stored. That is, the metadata associated with the physical address to which the sector data is originally stored is additionally stored. Illustratively, when the sector data SD5 to SD7 are stored, the sector data SD5 to SD7 are offset from the physical address PA33 to be originally stored (see FIG. 4, Offset 5, 6, 7 ) Is added and stored. When the sector data SD8 is stored, information related to the offset of the physical address PA34 (offset 0 in FIG. 4) to which the sector data SD8 is to be originally stored is added and stored. For example, as shown in Fig. 5, the metadata composed of the number of offsets and offsets 5, 3 is added and stored when the sector data SD5 to SD7 are stored. The metadata composed of the number of offsets and offsets (0, 1) is added and stored when the sector data SD8 is stored.

Assume that there is a read request for consecutive sector data (SD5 to SD8) from the file system 112 of the host apparatus 120 after the sector data SD5 to SD8 is stored. In this case, the flash translation layer (FTL) stores the data stored in the storage area corresponding to the start offset (0) of the physical address (PA33) and the last offset (3) Read.

The flash translation layer (FTL) can interpret the offset of the physical address to which the read data should originally be stored based on the metadata consisting of the number of offsets and offsets. For example, the flash translation layer (FTL) may determine three offsets from the start offset (0) of the physical address PA33 (i. E., Based on metadata 5,3 corresponding to the logical address LA0) Data to be read out from the storage area corresponding to the offset (0 to 2) of the physical address PA33 is to be stored in three offsets (i.e., offsets 5 to 7) from the offset 5 of the physical address PA33 . By this interpretation, the flash translation layer (FTL) has data read from the storage area corresponding to three offsets (i.e., the offsets (0-2)) from the start offset (0) of the physical address PA33, Data SD5 to SD7.

The flash translation layer (FTL) can interpret the offset of the physical address from which data read based on the metadata and the address alignment flag (AAF) is originally stored. Illustratively, the flash translation layer (FTL) may refer to metadata corresponding to a previous logical address when the address alignment flag (AAF) parses the metadata corresponding to the logical address set. For example, the flash conversion layer (FTL) may determine whether the physical address (physical address) is the physical address (physical address) based on the meta data 5 and 3 corresponding to the previous logical address LA0 and the metadata 0 and 1 corresponding to the logical address LA1 The data read out from the storage area corresponding to one offset 3 after three offsets (i.e., the offsets 0 to 2) from the start offset 0 of the physical address PA33 is the offset of the physical address PA34 (0). ≪ / RTI > This interpretation may be possible because the successive sector data is stored by a rule that it is stored sequentially in successive logical addresses and physical addresses mapped to it. By this interpretation, the flash translation layer (FTL) is arranged to correspond to one offset (3) after three offsets (i.e., offsets (0-2)) from the start offset (0) It can be seen that the data read out from the storage area is the sector data SD8.

According to an embodiment of the present invention, when writing of consecutive sector addresses is requested from the host device, a start sector address of the consecutive sector addresses is mapped to a start offset of the physical address, Are sequentially mapped to the remaining offsets of the physical address. That is, when successive sector data is transmitted from the host device 110, the sector address and the logical address are mapped to the physical address so that the sector data transmitted in one physical address can be processed. When the transmitted sector data is stored, metadata composed of information related to the sector address corresponding to the sector data is added. Based on the added meta data, it can be determined whether the data stored in the page corresponding to the physical address corresponds to the sector address corresponding to which sector address.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the appended claims and their equivalents. It will be appreciated that the structure of the present invention may be variously modified or changed without departing from the scope or spirit of the present invention.

100: Data processing system
110: Host device
120: Data storage device
130: controller
140: Nonvolatile memory device

Claims (8)

A method of operating a data storage device comprising a non-volatile memory device, the method comprising:
Mapping the sector addresses of the host device to the physical address offsets of the non-volatile memory device,
If the writing of consecutive sector addresses is requested from the host device, mapping the starting sector address of the consecutive sector addresses to the starting offset of the physical address, and adding the remaining sector addresses to the remaining offsets of the physical address sequentially Lt; RTI ID = 0.0 > 1, < / RTI > The method according to claim 1,
And generating metadata comprising address information for the successive sector addresses. 3. The method of claim 2,
Wherein the metadata includes logical address information mapped to the physical address, a starting sector address of the contiguous sector addresses, and information on the number of consecutive sector addresses. 3. The method of claim 2,
And adding the metadata when the sector data corresponding to the consecutive sector addresses is stored. A nonvolatile memory device; And
A controller configured to control the non-volatile memory device,
Wherein the controller is configured to map the sector addresses of the host device to the offsets of the physical address of the non-volatile memory device, wherein when writing to the consecutive sector addresses is requested from the host device, A sector address to a start offset of the physical address, and to sequentially map remaining sector addresses to the remaining offsets of the physical address. 6. The method of claim 5,
Wherein the controller is configured to generate metadata comprising address information for the consecutive sector addresses. The method according to claim 6,
Wherein the metadata comprises logical address information mapped to the physical address, a starting sector address of the contiguous sector addresses, and information on the number of consecutive sector addresses. The method according to claim 6,
Wherein the controller is further configured to store the metadata when the sector data corresponding to the successive sector addresses is stored.
KR1020120153521A 2012-12-26 2012-12-26 Data storage device and operating method thereof KR20140085643A (en)

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