KR20140071779A - Semiconductor memory device and operating method thereof - Google Patents

Semiconductor memory device and operating method thereof Download PDF

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Publication number
KR20140071779A
KR20140071779A KR1020120139756A KR20120139756A KR20140071779A KR 20140071779 A KR20140071779 A KR 20140071779A KR 1020120139756 A KR1020120139756 A KR 1020120139756A KR 20120139756 A KR20120139756 A KR 20120139756A KR 20140071779 A KR20140071779 A KR 20140071779A
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South Korea
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read
voltage
fail
memory cell
readout
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KR1020120139756A
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Korean (ko)
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정승근
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에스케이하이닉스 주식회사
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Publication of KR20140071779A publication Critical patent/KR20140071779A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/26—Floating gate memory which is adapted to be one-time programmable [OTP], e.g. containing multiple OTP blocks permitting limited update ability

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Abstract

The present invention relates to a semiconductor memory device and an operation method thereof. The semiconductor memory device comprises: a main memory cell unit including multiple memory cells; a peripheral circuit which applies a read voltage to the main memory cell unit to read data; an OTP memory cell unit which stores a plurality of different read voltage tables; and a control circuit which selects one read voltage table from among the plurality of different read voltage tables stored in the OTP memory cell unit, based on the attribute parameters of the multiple memory cells, and uses another correction read voltage which is different from the read voltage according to the selected read voltage table to control the peripheral circuit to redo a read operation of the main memory cell unit.

Description

Technical Field [0001] The present invention relates to a semiconductor memory device and an operating method thereof,

The present invention relates to a semiconductor memory device and an operation method thereof, and more particularly, to a semiconductor memory device using an optimized read voltage for each memory chip in a read operation and a method of operating the semiconductor memory device.

In recent years, there is an increasing demand for a nonvolatile memory device that can electrically program and erase data, and does not require a refresh function to rewrite data at regular intervals.

The nonvolatile memory device is an element capable of performing an electrical program / erase operation. As electrons move due to a strong electric field applied to a thin oxide film, the nonvolatile memory device performs program and erase operations by changing a threshold voltage of the cell. At this time, an operation of filling the floating gate with electrons is called a program operation, and an operation of discharging electrons filled in the floating gate is called an erase operation. Also, a data value changed according to a threshold voltage value of memory cells of a programmed nonvolatile memory device is sensed to perform a read operation.

The threshold voltage distribution of the memory cells of the nonvolatile memory device is such that as the data is programmed for a longer period of time, the charges charged in the floating gate escape to lower the threshold voltage. As a result, the programmed data value and the read data value are different from each other during the read operation, so that a read operation error may occur. Also, as the program erase operation is repeatedly performed, the threshold voltage may increase

Also, the memory cells of the nonvolatile memory device have different device characteristics according to the effective field oxide height (EFH) for each memory chip according to factors in the manufacturing process. That is, the threshold voltage distributions of the programmed memory cells may be different from each other depending on the height EFH of the effective field oxide film, and it is difficult to obtain accurate data in the read operation.

In an embodiment of the present invention, a plurality of read voltage tables are stored for each memory chip, one of a plurality of read voltage tables is selected according to characteristic parameters obtained through an analysis operation for each memory chip, And a semiconductor memory device capable of performing a read operation of each memory chip using the semiconductor memory device and an operation method thereof.

A semiconductor memory device according to an embodiment of the present invention includes a main memory cell portion including a plurality of memory cells, a peripheral circuit for reading data by applying a read voltage to the main memory cell portion, And a control unit that selects one of the plurality of read voltage tables stored in the OTP memory cell unit according to the stored OTP memory cell unit and the characteristic parameters of the plurality of memory cells, And a control circuit for controlling the peripheral circuit to redo the read operation of the main memory cell unit using the read voltage.

A semiconductor memory device according to another embodiment of the present invention includes a plurality of multi-chips, each of the plurality of multi-chips including a main memory cell portion including a plurality of memory cells, And an OTP memory cell section in which a plurality of different read voltage tables are stored and a read voltage table of a plurality of read voltage tables stored in the OTP memory cell section in accordance with characteristic parameters of the plurality of memory cells, And a control circuit for controlling the peripheral circuit so as to redo the reading operation of the main memory cell unit by using a correction readout voltage different from the readout voltage according to the selected readout voltage table.

A method of operating a semiconductor memory device according to an embodiment of the present invention includes storing a plurality of read voltage tables including different read voltages according to device characteristics in each memory chip, Selecting one of the plurality of read voltage tables in each of the memory chips according to the analyzed characteristic parameter; and performing a read operation and a re-read operation in accordance with the selected read voltage table .

According to another aspect of the present invention, there is provided a method of operating a semiconductor memory device, comprising: storing a plurality of read voltage tables in an OTP memory cell; analyzing characteristic parameters of the memory chip; Selecting one of the read voltage tables, and performing a read operation using the selected read voltage table.

According to the embodiment of the present invention, after storing a plurality of read voltage tables for each memory chip, one of the plurality of read voltage tables is selected according to the parameters obtained through the analysis operation for each memory chip, So that accurate read data can be obtained by applying an optimized read voltage table to each memory chip. In addition, fast read operation can be performed according to the optimized read voltage table.

1 is a configuration diagram showing a semiconductor memory device according to an embodiment of the present invention.
2 is a threshold voltage distribution diagram for explaining a change in the threshold voltage distribution of a programmed memory cell.
3 is a flowchart illustrating an operation of a semiconductor memory device according to an embodiment of the present invention.
4 is a flowchart illustrating a read operation according to an embodiment of the present invention.
5 is a threshold voltage distribution diagram for explaining a change of a read voltage in a read operation according to an embodiment of the present invention.
6 is a configuration diagram showing a multi-chip semiconductor memory device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. It is provided to let you know.

1 is a block diagram of a semiconductor memory device according to the present invention.

1, the semiconductor memory device includes a main memory cell unit 110, a main main page buffer circuit 120, a voltage supply circuit 130, an X decoder 140, a fail detection circuit 150, a control circuit 160 ), An OTP (one-time programmable) memory cell unit 170, and an OTP page buffer circuit 180.

The main memory cell unit 110 includes a plurality of memory cells capable of storing data.

The main page buffer circuit 120 is responsive to the page buffer control signals PB_signals output from the control circuit 160 during a read operation to set a threshold voltage Vs of the memory cells selected through the bit line BL of the main memory cell unit 110 And stores the sensing result as read data.

In addition, the main page buffer circuit 120 may store new read data when performing a re-read operation after setting the read voltage to the corrected read voltage during the read operation.

The voltage supply circuit 130 generates the read voltage Vread and the pass voltage Vpass in response to the voltage supply circuit control signals VC_signals output from the control circuit 160 during the read operation. The voltage supply circuit 130 may adjust the potential level of the read voltage Vread in response to the voltage supply circuit control signals VC_signals during the read operation.

The X decoder 140 outputs the read voltage Vread to the word lines WL0 to WLn and the select lines SSL and DSL in the main memory cell unit 110 in accordance with the row address RADD input from the control circuit 160. [ , The pass voltage (Vpass), and the operating voltage.

The fail detection circuit 150 performs a fail detection operation on a plurality of read data stored in the main page buffer circuit 120 during a read operation. The fail detection circuit 150 detects and counts whether or not the fail bit of a plurality of read data stored in the main page buffer circuit 120 is a fail bit and counts the number of fail bits that have been counted by the error detection circuit 150 in an error correction circuit And outputs a pass / fail signal PASS / FAIL in comparison with the number of bits. That is, the fail detection circuit 150 outputs the pass signal PASS when the number of counted fail bits is equal to or smaller than the allowable bit number, and outputs the fail signal FAIL when the counted number of fail bits is larger than the allowable bit number Output.

The control circuit 160 outputs page buffer control signals PB_signals for controlling the main page buffer circuit 120 during the read operation and generates voltage supply circuit control signals VC_signals And outputs a row address RADD for controlling the X decoder 140. [

The control circuit 160 newly sets the potential level of the readout voltage Vread output from the voltage supply circuit 130 in accordance with the pass / fail signal output from the fail detection circuit 150 during the read operation to output the corrected readout voltage . The control circuit 160 sets a correction readout voltage according to a selected readout voltage table (read_table) among a plurality of readout voltage tables stored in the OTP memory cell unit 170.

The OTP memory cell unit 170 stores a plurality of readout voltage tables storing the degree of change of the readout voltage, the number of times of change, and the like in the re-read operation. In many readout voltage tables, the degree of voltage change of the readout voltage, etc. are all set differently. The readout voltage table will be described later. The OTP memory cell unit 170 reads a selected read voltage table (read_table) among the plurality of read voltage tables by the control circuit 160 during the booting operation of the semiconductor memory device.

The OTP page buffer circuit 180 reads out a selected one read voltage table (read_table) among a plurality of read voltage tables stored in the OTP memory cell unit 170 during a booting operation of the semiconductor memory device, and outputs the selected read voltage table to the control circuit 160.

2 is a threshold voltage distribution diagram for explaining a change in the threshold voltage distribution of a programmed memory cell.

Referring to FIG. 2, the memory cells of the semiconductor memory device have the same threshold voltage distribution as the initial state after operation. However, as the program operation and the erase operation are repeated and the number of times of the EW cycle increases, the light tail portion of the threshold voltage distribution is liable to be elongated. In addition, as the charges stored in the memory cells escape from the programmed time, the left tail portion of the threshold voltage distribution may be elongated.

Erroneous data values may be read out during a read operation using the initial readout voltage groups R1, R2, and R3 due to the slackening of the light tail and the left tail portion.

When it is determined that the fail bit of the read data is larger than the set bit after performing the read operation using the initial read voltage group R1, R2, R3 during the read operation, a new read voltage (R1-1, R2-1, R3-1) or a new read voltage group (R1-3, R2-3, R3-3) in which the read voltage is gradually decreased can be used to re-execute the read operation have.

3 is a flowchart illustrating an operation of a semiconductor memory device according to an embodiment of the present invention.

The operation of the semiconductor memory device according to the embodiment will be described with reference to FIG.

1) storing a plurality of readout voltage tables in the OTP memory cell unit (S100)

First, a plurality of read voltage tables are stored in the OTP memory cell unit 170 of the semiconductor memory device.

Each of the plurality of read voltage tables is set differently from the set value (? V) that is increased or decreased in the initial read voltage group during the re-read operation.

For example, the set value? V of the first read voltage table is smaller than the set value? V of the second read voltage table. Also, the set value? V of the second read voltage table is smaller than the set value? V of the third read voltage table. A plurality of readout voltage tables of the above-described manner are stored.

A plurality of readout voltage table storage (SlOO) in the OTP memory cell portion is programmed only once in the initial state of the semiconductor memory device. For example, it can be programmed when the product is manufactured.

2) Analysis of the characteristic parameters of the memory chip (S200)

Analyze the characteristic parameters of the memory chip. The characteristic parameter of the memory chip may be an average value of the height EFH of the effective field oxide layer of the plurality of memory cells included in the main memory cell unit 110. [ In addition, the thickness (EOT) of the dielectric film of the memory cell may also be a characteristic parameter. In addition, all factors that can affect the threshold voltage of the memory cell, such as the width and thickness of the memory cell, can be characteristic parameters.

It is preferable that the step of analyzing the characteristic parameter of the memory chip (S200) is carried out prior to shipment of the semiconductor memory device, and the value according to the characteristic parameter is stored in the semiconductor memory device.

3) selecting the read voltage table according to the analyzed parameters (S300)

And selects one of the plurality of read voltage tables according to the analyzed parameters.

For example, when the height of the effective field oxide film is larger than the reference value, the threshold voltage distribution of the memory cell may cause the light tail to increase. Accordingly, a new read voltage table R1-1 (= R1 + ΔV) which increases by the set value ΔV from the initial read voltage group R1, R2, R3 and the previously applied read voltage group among the plurality of read voltage tables, , R2-1 (= R2 + DELTA V) and R3-1 (= R3 + DELTA V)) are selected. At this time, the readout voltage group selected according to how much the height of the effective field oxide layer is larger than the reference value can be further subdivided and selected. (= R1 + DELTA V) and R2 (= R1 + DELTA V) which are increased by a set value (DELTA V) than the initial readout voltage group (R1, R2, R3) when the height of the effective field oxide film is larger than the reference value by The initial read voltage group R1, R2 (= R2 + DELTA V) and R3-1 (= R3 + DELTA V) R2 + 2V), R3-2 (= R3 +? 2V) which is increased by the set value (? 2V) than the read voltage table R1 . That is, it is preferable to select the read voltage table in which the set value increases proportionally as the height of the effective field oxide film increases.

4) Perform a read operation using the selected readout voltage table (S400)

And performs a read operation using the selected readout voltage table. The read operation reads data stored in the main memory cell unit 110 using the initial read voltage group R1, R2, and R3. When it is determined that the fail bit of the read data is larger than the ECC allowable bit number, (For example, R1-1 (= R1 + DELTA V), R2-1 (= R2 + DELTA V), and R3-1 (= R3 + DELTA V)). If it is determined that the fail bit is still larger than the ECC allowable bit number as a result of the re-read operation, a new read voltage group that is increased by ΔV from the previously applied read voltage group is newly set and the re-read operation is repeated. If the fail bit is smaller than the ECC allowable bit number, the re-read operation is stopped and the read operation is terminated.

4 is a flowchart illustrating a read operation according to an embodiment of the present invention.

5 is a threshold voltage distribution diagram for explaining a change of a read voltage in a read operation according to an embodiment of the present invention.

Referring to FIGS. 1, 4, and 5, a read operation of the semiconductor memory device according to the present invention will be described in detail.

In the embodiment of the present invention, the characteristic parameters of the memory chip are selected as the analysis result readout voltage tables R1-1 (= R1 + ΔV), R2-1 (= R2 + ΔV) and R3-1 Let us explain the case as an example.

1) A readout voltage group (S410)

The voltage supply circuit 130 generates the read voltages R1, R2 and R3 corresponding to the A readout voltage group in response to the voltage supply circuit control signals VC_signals output from the control circuit 160. [ X decoder 140 sequentially applies the read voltages R1, R2, R3 to the selected one of the plurality of word lines WL < 0: n > according to the row address RADD, The pass voltage (Vpass) is applied to the line.

The page buffers in the main page buffer circuit 120 are connected to the bit lines BL of the bit lines BL to which the memory cells of the main memory cells are connected each time the read voltages R1, And stores the read data by sensing the potential.

2) Fail bit detection (S420)

The fail bit detection circuit 150 performs a fail bit detection operation of a plurality of read data stored in the page buffers of the main page buffer circuit 120. That is, the fail detection circuit 150 counts the number of fail bits among a plurality of read data stored in each page buffer of the page buffer circuit 120.

3) Error correction is possible (S430)

The fail bit detection circuit 150 compares the number of counted fail bits with the number of allowed bits that can be corrected by an error correction circuit to determine whether or not error correction of the read data is possible. The fail detection circuit 150 outputs the pass signal PASS when the number of counted fail bits is equal to or smaller than the allowable bit number and outputs the fail signal FAIL when the counted number of fail bits is larger than the allowable bit number And performs a pass fail check operation.

4) Read operation as the B read voltage group (S440)

If it is determined in step S430 that the error can not be corrected, the voltage supply circuit 130 reads out B in response to the voltage supply circuit control signals VC_signals output from the control circuit 160 And generates read voltages R1-1, R2-1, and R3-1 corresponding to the voltage group. At this time, the B readout voltage group is higher than the A readout voltage group by the set voltage level (? V). The control circuit 160 sets the B readout voltage group according to a selected one of the plurality of readout voltage tables stored in the OTP memory cell unit 170 during the booting operation of the semiconductor memory device.

The X decoder 140 sequentially outputs the read voltages R1-1, R2-1, and R3-1 to the selected one of the plurality of word lines WL <0: n> according to the row address RADD And a pass voltage Vpass is applied to the unselected word line.

The page buffers in the main page buffer circuit 120 are set to the potentials of the bit lines BL connected to the main memory cell unit 110 every time the read voltages R1-1, R2-1, and R3-1 are sequentially applied And stores the read data.

5) Fail bit detection (S450)

The fail bit detection circuit 150 performs a fail bit detection operation of a plurality of read data stored in the page buffers of the main page buffer circuit 120. That is, the fail detection circuit 150 counts the number of fail bits among a plurality of read data stored in each page buffer of the page buffer circuit 120.

6) Error correction is possible (S460)

The fail bit detection circuit 150 compares the number of counted fail bits with the number of allowable bits that can be corrected by the error correction circuit to determine whether or not error correction of the read data is possible. The fail detection circuit 150 outputs the pass signal PASS when the number of counted fail bits is equal to or smaller than the allowable bit number and outputs the fail signal FAIL when the counted number of fail bits is larger than the allowable bit number And performs a pass fail check operation.

7) Block Fail (S470)

If it is determined in step S460 that the number of fail bits counted is greater than the allowable number of bits, the main memory cell block 110 is processed as a fail block.

That is, if the number of fail bits is larger than the allowable number of bits even if a new read operation using the corrected read voltage is performed for the preset number of times, the main memory cell block 110 is processed as a fail block.

8) Error correction (S480)

If it is determined that the number of fail bits counted in the error correction availability determination steps S430 and S460 is equal to or less than the allowable number of bits, an error correction circuit included in the control circuit 160 is used And corrects the data detected by the fail bit among the data stored in the page buffer circuit 120. [

9) Data output (S490)

And outputs read data corrected by an error correction circuit included in the control circuit 160 to the outside.

In the embodiment of the present invention, the operation of re-reading using the corrected readout voltage group (B readout voltage group) in which the initial readout voltage group (A readout voltage group) is increased by the set value (? V) If the error correction is judged to be impossible after the reading operation using the group (B readout voltage group), a new correction readout voltage group (a group of correction readout voltages higher than the B readout voltage group by a set voltage level (? V) Operation can be performed.

In the embodiment of the present invention, the correction readout voltage is gradually increased. However, the present invention is also applicable to the case where the correction readout voltage gradually falls.

Also, it is preferable that a plurality of read voltage tables are stored differently from the set voltage levels (DELTA V), and the most suitable read voltage table among the plurality of read voltage tables may be selected and used according to the analysis results of the characteristic parameters of the memory chip .

In the present invention, a plurality of read voltage tables are stored for each memory chip in a multi-chip memory device including a plurality of memory chips, and then, in accordance with parameters obtained through an analysis operation for each memory chip, One is selected and the read operation is performed by using the selected readout voltage table, whereby the optimized readout voltage table is applied to each memory chip to obtain accurate readout data. In addition, according to the optimized read voltage table, it is possible to perform a fast read operation by reducing the number of re-read operations in the read operation.

6 is a configuration diagram showing a multi-chip semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 6, a semiconductor memory device 1000 including a multi-chip includes a plurality of multi-chips 1100 to 1300.

Each of the structures of the plurality of multi-chips 1100 to 1300 can be configured similarly to the semiconductor memory device shown in FIG. 1, so that the above description is omitted.

Each of the plurality of multi-chips 1100 to 1300 stores different readout voltage tables in the OTP memory cell portion. In many readout voltage tables, the degree of voltage change of the readout voltage, etc. are all set differently.

The semiconductor memory device 1000 including the plurality of the above-described multiple chips 1100 to 1300 can select different read voltage tables according to the characteristic parameters of the respective multi-chips, The read / write operation is performed in the read operation according to the read operation, and accurate read data can be obtained and output to the host.

110: main memory cell unit 120: main page buffer circuit
130: voltage supply circuit 140: X decoder
150: fail bit detection circuit 160: control circuit
170: OPT memory cell unit 180: OTP page buffer circuit

Claims (31)

A main memory cell portion including a plurality of memory cells;
A peripheral circuit for reading data by applying a read voltage to the main memory cell portion;
An OTP memory cell portion storing a plurality of different readout voltage tables; And
Selecting one read voltage table among a plurality of read voltage tables stored in the OTP memory cell unit according to characteristic parameters of the plurality of memory cells, And a control circuit for controlling the peripheral circuit so as to redo the read operation of the main memory cell unit.
The method according to claim 1,
Wherein the characteristic parameter is an average value of an effective field oxide film height of the plurality of memory cells.
The method according to claim 1,
Wherein the characteristic parameter is an average value of effective oxide film thickness of the plurality of memory cells.
The method according to claim 1,
Wherein the characteristic parameter is an average value of the widths of the plurality of memory cells.
The method according to claim 1,
And a fail bit detection circuit for performing a pass fail check operation of the main memory cell portion according to the data read by the peripheral circuit.
6. The method of claim 5,
Wherein the fail bit detection circuit compares the number of fail bits counted for each page buffer group with the number of allowed bits that can be corrected by an error correction circuit to output a pass / fail signal.
6. The method of claim 5,
Wherein the control circuit controls the peripheral circuit and the fail bit detection circuit to re-execute the read operation using the corrected readout voltage according to the selected readout voltage table when the control circuit determines that the fail- Lt; / RTI &gt;
The method according to claim 1,
Wherein the correction readout voltage is raised or lowered by a set voltage from a readout voltage applied in a previous read operation.
9. The method of claim 8,
Wherein the plurality of read voltage tables have different magnitudes of the set voltages.
The method according to claim 1,
The peripheral circuit includes a voltage supply circuit for generating the readout voltage or the corrected readout voltage in response to voltage supply circuit control signals output from the control circuit;
An X decoder for transferring the read voltage or the corrected read voltage generated in the voltage supply circuit according to a row address to a selected word line of the memory cell block; And
And a page buffer circuit for reading and storing the data of the memory cells included in the plurality of memory cell groups.
The method according to claim 1,
Further comprising an OTP page buffer circuit for reading one of the plurality of read voltage tables stored in the OTP memory cell section and outputting the readout voltage table to the control circuit.
A plurality of multi-chips, each of the plurality of multi-
A main memory cell portion including a plurality of memory cells;
A peripheral circuit for reading data by applying a read voltage to the main memory cell portion;
An OTP memory cell portion storing a plurality of different readout voltage tables; And
Selecting one read voltage table among a plurality of read voltage tables stored in the OTP memory cell unit according to characteristic parameters of the plurality of memory cells, And a control circuit for controlling the peripheral circuit so as to redo the read operation of the main memory cell unit.
13. The method of claim 12,
Wherein the characteristic parameter is an average value of an effective field oxide film height of the plurality of memory cells.
13. The method of claim 12,
Wherein the characteristic parameter is an average value of the widths of the plurality of memory cells.
13. The method of claim 12,
Wherein the characteristic parameter is an average value of effective oxide film thickness of the plurality of memory cells.
Storing in a memory chip a plurality of readout voltage tables containing different readout voltages according to device characteristics;
Analyzing characteristic parameters that can identify the device characteristics of each memory chip;
Selecting one of the plurality of read voltage tables in each memory chip according to the analyzed characteristic parameter; And
And performing a read operation and a read operation in accordance with the selected readout voltage table.
17. The method of claim 16,
Wherein the characteristic parameter is an average value of an effective field oxide film height of the memory cells included in the memory chip.
18. The method of claim 17,
And selects a read voltage table having a larger set voltage value as the average value of the effective field oxide film heights is higher.
19. The method of claim 18,
Wherein the set voltage value is a difference between a previously read out voltage value and a newly set corrected read out voltage value in a read operation.
17. The method of claim 16,
Wherein the characteristic parameter is an average value of the widths of the plurality of memory cells.
17. The method of claim 16,
The step of performing the read and re-read operations
A first reading step of reading data stored in memory cells included in each memory chip using an initial read voltage;
Performing a fail-check operation of a read operation;
Setting a new correction readout voltage for each memory chip according to the readout voltage table corresponding to each memory chip when it is determined as a result of the fail check operation; And
And a second readout step of re-reading data stored in the memory cells in accordance with the new corrected readout voltage.
22. The method of claim 21,
The step of performing the fail-check operation of the read-
Counting a fail bit of data read out in the first readout step; And
And comparing the counted number of fail bits with the allowable number of bits to perform the fail check operation of the read operation for each memory chip.
22. The method of claim 21,
After the second readout step,
And a step of re-executing the fail-check operation of the read operation.
Storing a plurality of readout voltage tables in an OTP memory cell;
Analyzing characteristic parameters of the memory chip;
Selecting one of the plurality of read voltage tables according to the analyzed characteristic parameter; And
And performing a read operation using the selected read voltage table.
25. The method of claim 24,
Wherein the characteristic parameter is an average value of an effective field oxide film height of the memory cells included in the memory chip.
26. The method of claim 25,
And selects a read voltage table having a larger set voltage value as the average value of the effective field oxide film heights is higher.
27. The method of claim 26,
Wherein the set voltage value is a difference between a previously read out voltage value and a newly set corrected read out voltage value in a read operation.
25. The method of claim 24,
Wherein the characteristic parameter is an average value of the widths of the plurality of memory cells.
25. The method of claim 24,
The step of performing the read operation
Reading data stored in memory cells using an initial read voltage group;
Comparing a fail bit and a permissible bit of the data to perform a pass fail check operation of the read operation;
Re-reading data stored in the memory cells by using a correction read voltage different from the initial read voltage group according to the read voltage table when it is determined that the pass fail check operation is failed;
And re-executing the pass fail check operation.
30. The method of claim 29,
And an error correction operation using an ECC circuit is performed when it is determined that the path is a result path of the pass fail check operation, and then the error corrected data is output to the outside.
30. The method of claim 29,
Further comprising the step of processing a memory block for performing a read operation into a block fail if it is determined that the path is a result path of the pass fail check operation even if the step of re-reading the data stored in the memory cells proceeds by a predetermined number of times, Method of operation of the device.
KR1020120139756A 2012-12-04 2012-12-04 Semiconductor memory device and operating method thereof KR20140071779A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
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US9905302B2 (en) 2014-11-20 2018-02-27 Western Digital Technologies, Inc. Read level grouping algorithms for increased flash performance
US10120589B2 (en) 2014-11-07 2018-11-06 Samsung Electronics Co., Ltd. Method of adjusting read voltages applied by a nonvolatile memory device using information stored by a read history table
US10566061B2 (en) 2014-11-20 2020-02-18 Western Digital Technologies, Inc. Calibrating optimal read levels

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10120589B2 (en) 2014-11-07 2018-11-06 Samsung Electronics Co., Ltd. Method of adjusting read voltages applied by a nonvolatile memory device using information stored by a read history table
US9905302B2 (en) 2014-11-20 2018-02-27 Western Digital Technologies, Inc. Read level grouping algorithms for increased flash performance
US10566061B2 (en) 2014-11-20 2020-02-18 Western Digital Technologies, Inc. Calibrating optimal read levels
US11488673B2 (en) 2014-11-20 2022-11-01 Western Digital Technologies, Inc. Calibrating optimal read levels

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