KR20140050151A - Method for modeling delay time and output time of gate - Google Patents

Abstract

The present invention relates to a modeling method which estimates delay time and output time of a gate when a body bias voltage is applied. A method of modeling the delay time or the output time of the gate according to the present invention includes a step of selecting a first gate among a plurality of gates; a step of determining the structure of the selected first gate; a step of generating the delay time ratio or the output time ratio of the selected first gate according to the determination result; and a step of calculating the delay time or the output time of a second gate when the body bias voltage is applied based on the delay time or the output time of the second gate among the generated delay time ratio or the output time ratio and the gates. [Reference numerals] (110) First delay time table; (120) Delay time ratio table; (130) Second delay time table

Description

How to model gate delay and output time {METHOD FOR MODELING DELAY TIME AND OUTPUT TIME OF GATE}

The present invention relates to a semiconductor device, and more particularly, to a method of modeling a gate delay time and an output time.

Process variations occur due to various factors that occur during semiconductor manufacturing. This process variation can lead to performance results that differ from those expected in the design. In order to solve this problem, a semiconductor chip is designed based on a process corner. When the chip is designed by creating a library based on the largest gate delay due to the process variation and the largest leakage current, the performance degradation due to the process variation can be prevented. However, as the size of semiconductor devices decreases due to the development of semiconductor manufacturing technology, process variation increases, and even when a chip is designed using a library based on a process corner, it is difficult to satisfy the expected performance of the chip at design time.

One of the methods for solving the above problems is to apply a body bias voltage to the gate to compensate for abnormal characteristics caused by process variations. However, in order to predict the operating characteristics of the gate to which the body bias voltage is applied, the operating characteristics of all the gates must be simulated according to the assigned body bias value. This process has to be performed for all the gates, resulting in excessive overhead. Therefore, it is difficult to predict the operating characteristics of the gate after the body bias voltage is applied, because it takes a lot of time and cost.

It is an object of the present invention to provide a gate latency modeling method having reduced overhead.

According to an embodiment of the present disclosure, a method of modeling delay times of a plurality of gates may include selecting a first gate of the plurality of gates; Determining a structure of the selected first gate; Generating a delay time ratio of the selected first gate according to the determination result; And calculating a delay time of the second gate when the body bias voltage is applied based on the generated delay time ratio and the delay time of the second gate of the plurality of gates. The second gates have the same number of stacks and the number of stages, the number of stacks is the number of transistors between the power supply voltage and the output terminal of the first and second gates, and the number of stages is the first and second The number of transistors between the input and output terminals of the two gates.

In an embodiment, the delay time is a time point at which the output signal is 1/2 times the power supply voltage from the time point at which the input signal changes.

In an embodiment, the transistors included in each of the first and second gates have different widths.

In an embodiment, the determining of the structure of the selected gate may include determining whether the selected gate has a multi-stage structure; And determining whether the selected gate is a stack structure.

In an embodiment, the generating of the delay time ratio according to the determination result may include generating different delay time ratios according to the determined multi-stage structure and the determined stack structure.

The method may further include calculating a delay time of each of the plurality of gates when the body bias voltage is applied, based on the delay time of each of the plurality of gates and the generated delay time ratio. .

An output time modeling method of a plurality of gates according to an exemplary embodiment of the present disclosure may include selecting a first gate of the plurality of gates; Determining a structure of the selected first gate; Generating an output time ratio according to the determination result; And calculating an output time of the second gate when a body bias voltage is applied based on the generated output time ratio and the output time of the second gate among the plurality of gates. Each of the second gates has the same number of stacks and the number of stages, wherein the number of stacks is the number of transistors between a power supply voltage and an output terminal of the first and second gates, and the number of stages is the first number. And the number of transistors between the input terminal and the output terminal of the second gates.

According to the present invention, the gate delay time can be modeled regardless of the size of the transistor. Thus, a gate delay modeling method with reduced overhead is provided.

1 is a conceptual diagram illustrating a gate delay time modeling method according to an embodiment of the present invention.
2 is a circuit diagram showing an inverter gate.
3 is a graph illustrating a delay time according to an embodiment of the present invention.
4 is a circuit diagram showing a NOR gate.
5 is a circuit diagram illustrating an AND gate.
6A and 6B are graphs for describing an output time according to an embodiment of the present invention.
7 is a flowchart illustrating a gate delay time modeling method according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to explain the present invention in detail so that those skilled in the art can easily carry out the technical idea of the present invention. .

According to the modeling method of the gate delay time of the present invention, the delay time can be predicted regardless of the size of the transistor. Therefore, it is possible to model the delay time of the gate with minimum overhead. For example, it is assumed that the gate delay time modeling method according to the embodiment of the present invention biases the body bias voltage by applying a fixed body bias voltage to the pMOS transistors included in the gate. However, the scope of the present invention is not limited thereto.

1 is a conceptual diagram illustrating an example of a gate delay time modeling 100 according to an exemplary embodiment of the present invention. Referring to FIG. 1, a delay time table 110 (hereinafter, referred to as a “first delay time table”) before applying a body bias voltage, a delay time rate table 120, and a delay time table 130 after applying a body bias voltage are described. (Hereinafter referred to as a "second delay table") includes delay time or delay ratio information of gates classified according to a structure. The structure here refers to the number of stacked transistors and the number of stages included in the gate as a configuration of the gate.

The first delay time table 110 may be a predetermined value or a predetermined value. The delay ratio table 120 includes information for estimating the delay time of the gate after applying the body bias voltage from the first delay time table 110. For example, the ratio of the delay time rate table 120 is a body bias voltage applied to the delay time around the gate ₍₀ d _{.5, nbb)} and body-bias voltage is applied after delay time of the gate ₍₀ d _{.5, bb)} It includes the delay time ratio (η) indicated. The second delay table 130 may be inferred using the first delay table 110 and the delay ratio table 120. Hereinafter, a method of deriving the delay ratio η included in the delay ratio table 120 will be described with reference to FIGS. 2 to 8 and equations.

2 is a circuit diagram illustrating an inverter gate 200. Referring to FIG. 2, the inverter gate 200 includes a pMOS transistor 210, an nMOS transistor 220, and a capacitor 230. The inverter gate 200 inverts and outputs the input signal IN. For example, when the input signal IN is logic high (eg, a voltage of V _DD ), the pMOS transistor 210 will be turned off and the nMOS transistor 220 will be turned on. In this case, since the charges stored in the capacitor 230 are discharged through the nMOS transistor 220, the output signal OUT will be logic low. In contrast, when the input signal IN is logic low (eg, zero voltage), the pMOS transistor 210 will be turned on and the nMOS transistor 220 will be turned off. In this case, since the capacitor 230 is charged by the current I _DD flowing through the pMOS transistor 210, the output signal OUT will be logic high.

Figure 3 is a graph for explaining a delay time (d _{0 .5),} according to an embodiment of the present invention. For example, the graph illustrated in FIG. 2 shows an input signal IN and an output signal OUT of the inverter gate 200. In FIG. 2, the X axis indicates time, and the Y axis indicates voltage.

Referring to FIG. 3, in the first period t1 to t2, the input signal IN is changed to 0 in the power supply voltage V _DD . In this case, the inverter gate 200 will charge the capacitor 230 to the power supply voltage V _DD in response to the input signal IN.

In an ideal case, the time point at which the input signal IN changes and the time point at which the output signal OUT becomes the power supply voltage V _DD should be the same. However, as shown in FIG. 2, the delay of the input / output occurs due to the characteristics of the elements. Conventional delay the input signal (IN) is 1/2 of the power supply voltage (V _DD / 2) the point in time (t ₂₎ from the output signal (OUT) is 1/2 of the power supply voltage (V _DD / 2 ) Up to the point in time (t ₃ ). However, when the delay time (d _{0 .5)} is the input signal is 1/2 times the power source voltage output signals (OUT) from the time (t1) is varied _{(IN) (V DD / 2} ) in accordance with the present invention ( t ₃ ). If by applying a delay time (d _{0 .5)} according to the invention the above-described modeling of the gate delay time, can be independently of modeling a delay of the gate and the size of the transistors (W _p).

Equation 1 shows an amount of charge charged in the capacitor 130. I _D (t) indicates the current flowing through the pMOS transistor 110, C _L indicates the capacitance of the capacitor 130, and V _DD indicates the power supply voltage.

Equation 2 shows the current I _D flowing through the pMOS transistor 110. k is a constant value according to the structure of the pMOS transistor 110. t _in indicates the time at which the input signal IN reaches zero voltage from the power supply voltage V _DD . W _p indicates the width of the pMOS transistor 110. V _SG (t) indicates the voltage difference between the source and the gate of the pMOS transistor 110.

With reference to expressions (1) and (2), the number of cases to obtain the delay time (d _{0 .5)} is a delay time (d _{0 .5)} the input time (t _in) by the length of the delay time (d _{0 .5)} If shorter (in the case 1, d _{0 .5} classified <t _in) and a delay time (d _{0 .5)} the input time (t _in) is longer than (the second case, d _{0 .5>} t _in) Can be. Illustratively, the first case (d _{0 .5} <t _in) is an inverter gate 200, due to the fast response speed of the input signal (IN) is zero voltage V (the power supply voltage output signal (OUT) before the _DD of ) Is reached. On the other hand, the graph shown in Figure 3 is a graph corresponding to the second case _{(d 0 .5> t in)} .

Equation 3 is an equation that shows the delay time (d _{0 .5)} in the first case _{(d 0 .5 <t in)} . Referring to Equation 3, V _t is the threshold voltage of the pMOS transistor, point (210), W _p indicates the width of the pMOS transistor (210) .α ₁ and β ₁ are for the delay time (d _{0 .5)} Pointers to constants except for the variables V _t and W _p . That is, the may be determined by the first case (d _{0 .5} <t _in) from a delay time (d _{0 .5)} is a (W _p), the threshold voltage (V _t) and the width of the pMOS transistor 110.

Equation 4 is a formula showing the delay time (d _{0 .5)} of the second case _{(d 0 .5> t in)} . Referring to Equation 4, α _2, β _2, and γ indicates a constant, except for the variable for the delay time _{(d 0 .5) (V t} , W p). That is, by a delay time (d _{0 .5)} the input time (t _in) is shorter than a delay time (d _{0 .5)} is a threshold voltage (V _t) and the width of the pMOS transistor (110) (W _p) Can be determined.

Referring to Equation 3 and 4, determined by the above-described first and second cases of the delay time (d _{0 .5)} on both the (W _p), the threshold voltage (V _t) and the width of the pMOS transistor 110 do. Through Equations 3 and 4, the delay time ratio η can be expressed as Equation 5. Refers to the ratio of the delay time ratio (η) is a delay time (d _{0 .5, bb)} after the delay time (d _{0 .5, nbb)} and body-bias voltage before being applied to the body bias voltage is applied.

Referring to Equation 5, V _{t and bb} indicate the threshold voltage of the pMOS transistor 110 after the body bias voltage is applied, and V _{t and nbb} indicate the threshold voltage of the pMOS transistor 110 before the body bias voltage is applied. Point to. That is, the delay time ratio (η) can be determined by the V _{t, bb,} V _{t, nbb,} and W _p.

With reference to Equations 1 to 5 described above, the delay ratio table 120 according to the present invention may be generated. Since the delay time according to the present invention is independent of the size of the transistor included in the gate, it is possible to model the gate delay time with a reduced overhead. Hereinafter, the width (p) of the pMOS transistor 110 may be described with reference to Equations 6 to 9. It is explained that the amount of change in the delay time ratio η according to the change in W _p ) is irrelevant.

Equation 6 is an equation showing the amount of change in the delay ratio η with respect to the change in the width W _p of the pMOS transistor 110. Referring to Equation 6, ₀ d _{.5, nbb} points to (referred to as a "first delay" hereinafter.) The delay time before it is applied to the body bias _voltage, d _{0.5, bb} is a bias voltage applied to the body The later delay time (hereinafter referred to as 'second delay time').

Depending on the size of the input time (t _in) can be different from the variation of the delay time for a change in the change of the width of the pMOS transistor _{(110) (W p) (} d 0.5, nbb, d 0 .5, bb). Accordingly, when longer than the input time (t _in) the first delay time (d _{0 .5, nbb)} (first case, see Equation 7), the input time (t _in) the first delay time (d _{0. 5, nbb)} shorter than the second delay time (d _{0 .5, bb)} is longer than (the second case, see equation (8)), and the input time (t _in) is a second delay time (d _{0 .5, bb} ) and the following will be described below by classifying them into a case shorter than the third case (see Equation 9).

Equation 7 is a mathematical expression showing the first case _{(d 0 .5, nbb <t} in). Referring to Equation 7, k ₁ denotes constant values except for the width W _p of the pMOS transistor 110. Since 1 / κ ₁ is much smaller than ₁ , the value of 1 / (κ ₁ W _p ) will be close to zero. That is, the change in the first case (d _{0 .5, nbb} <t _in) from, pMOS transistor 110, the delay time width ratio (η) for a change in the (W _p) of the is small enough to be negligible.

Equation 8 is an equation showing a case where the above-described claim _{2 (t 0 .5, bb <} t in <t 0 .5 nbb). Referring to Equation 8, κ ₂ indicates constant values except for the width W _p of the pMOS transistor 110. Since 1 / κ ₂ is much smaller than 1, the value of 1 / (κ ₂ W _p ) will also be close to zero. That is, in the second case, the change in the delay time ratio η with respect to the change in the width W _p of the pMOS transistor 110 will be small enough to be negligible.

Equation (9) is an equation showing a third case above _{(t in <t 0 .5,} bb). Referring to Equation 9, k ₃ denotes constants other than the width W _p of the pMOS transistor 110. Since 1 / κ ₃ is much smaller than 1, the value of 1 / (κ ₃ W _p ) will approach zero. That is, in the third case, the change in the delay ratio η with respect to the change in the width W _p of the pMOS transistor 110 will be small enough to be negligible.

Referring to Equations 7 to 9, the change amount of the delay time ratio η with respect to the change in the width W _p of the pMOS transistor 110 for all of the first to third cases described above is briefly expressed as in Equation 10. Can be represented.

Referring to Equation 10, k denotes constants other than the width W _p of the pMOS transistor 110. As described above, for all of the first to third cases, 1 / κ is much smaller than 1, so that the change in the delay ratio η to the change in the width W _p of the pMOS transistor 110 is negligible. It will be small enough to be.

In other words, the latency ratio of the present invention described above is independent of the size (eg, width) of the transistors. Therefore, the overhead is reduced when modeling the gate delay time using the above-described delay time ratio, thereby reducing the chip design time and the area of the chip.

4 is a circuit diagram illustrating a NOR gate 300. In exemplary embodiments, the NOR gate 300 has a structure in which a plurality of pMOS transistors 311 and 312 are stacked. Referring to FIG. 3, the NOR gate 300 includes pMOS transistors 311 and 312, nMOS transistors 321 and 322, and a capacitor 330. Unlike the inverter gate 200 of FIG. 1, the NOR gate 300 has a structure in which a plurality of pMOS transistors 311 and 312 are stacked, and therefore, the pMOS transistor 311 may have a pMOS due to a voltage drop V _x . The power supply voltage supplied to the transistor 312 becomes (V _DD -V _x ). Due to this, a number of different delay times (d _{0 .5),} and the delay time ratio (η). Therefore, the delay time ratio may be configured differently according to the number of stacked pMOS transistors. For example, applying the above-described equations, the delay ratio η 'of the NOR gate 200 of FIG. 3 is configured separately from the delay ratio η of the inverter gate 100 of FIG. Can be.

In an exemplary embodiment, the stack refers to the number of transistors connected in series between the gate supply voltage V _DD and the output terminal. In an embodiment of the present invention, a stack refers to the number of pMOS transistors connected in series between a power supply voltage V _DD and an output terminal, but the scope of the present invention is not limited thereto.

5 is a circuit diagram illustrating an AND gate 400. In exemplary embodiments, the AND gate 400 may have a multi-stage structure. Referring to FIG. 4, the AND gate 400 includes a first stage S1 and a second stage S2. By way of example, the number of stages refers to the number of transistors between the input and output terminals of the gate.

The first stage S1 includes pMOS transistors 411 and 412, nMOS transistors 421 and 422, and a capacitor 430. The first stage S1 may charge the capacitor 430 in response to the input signals A and B. FIG. For example, when one of the input signals A and B is logic high, the capacitor 430 is charged to the power supply voltage V _DD . When both input signals A and B are logic low, the charges charged in the capacitor 430 are discharged through the nMOS transistors 421 and 422.

The second stage S2 includes a pMOS transistor 441, an nMOS transistor 451, and a capacitor 460. The second stage S2 has the same configuration as the inverter gate 200 of FIG. 1. In response to the output of the first stage S1, the second stage S2 inverts the output of the first stage S1 and outputs the inverted output.

Equation 11 shows the delay time d _p of the AND gate 400. Referring to Equation 11, d _p indicates the delay time of the AND gate 400, d _p1 indicates the delay time of the first stage S1, and d _p2 indicates the delay time of the second stage S2. . d ¹ _intr indicates the delay time by the parasitic capacitor of the first stage S1, and k ¹ _L C ¹ _L indicates the delay time by the capacitor 430 of the first stage S1. d ² _intr indicates the delay time by the parasitic capacitor of the second stage S2, and k ² _L C ² _L indicates the delay time by the capacitor 460 of the second stage S2.

In the case of an AND gate 400 having a multi-stage structure, delay times d _{p and bb} may vary according to the position of a capacitor in which charge is stored. First, when the charge is stored in the capacitor 430 of the first stage (S1), the delay time (d _{p, bb} ) will be as shown in equation (12).

Referring to Equation 12, the delay time ratio η described with reference to Equations 1 to 10, the capacitance C ¹ _L of the capacitor 430 of the first stage S1, and the input time t _in ) Is a predetermined or measured constant value. Therefore, the delay times d _{p and bb} of the AND gate 400 will be determined by k ² _L.

Next, when the charge is stored in the capacitor 460 of the second stage (S2), the delay time (d _{p , bb} ) will be as shown in equation (13).

Referring to Equation 13, the delay times d _{p and bb} of the AND gate 300 may be determined by d _{p , nbb} and k ² _L. Summarizing with reference to Equation 11, k ² _L can be obtained as shown in Equation 14.

Therefore, with reference to Equations 11 to 14, the delay time d _p of the gates having the multi-stage structure can be configured. That is, the gates having the multi-stage structure may form a delay table different from that of the inverter gate 200 of FIG. 2.

6A and 6B are graphs for describing a ratio of output time according to an embodiment of the present invention. In an exemplary embodiment, the output time t _out according to the present invention is such that the output signal OUT has a second reference voltage (eg, 90% of the power supply voltage) at a first reference voltage (eg, 10% of the power supply voltage). Indicates the time to reach%).

Referring to FIG. 6A, the output signal OUT is input from the time from zero voltage to a predetermined voltage level (for example, x * V _DD ) rather than the time (d _x , hereinafter referred to as 'transition time'). If the time t _in is long, the transition time d _x may be expressed as in Equation 15. On the contrary, when the input time t _in is shorter than the transition time d _{x that} takes for the output signal OUT to reach a certain voltage level (for example, x * V _DD ), the transition time d _x Can be expressed as in Equation 16.

Referring to Equations 15 and 16, first and second transition times d _a and d _b for the transition coefficients a and b may be obtained. Since the output time t _out indicates a difference between the first transition time d _a and the second transition time d _b , the output time t _out is represented by Equation 17 with reference to Equations 15 and 16. This can be cleaned up.

Referring to Equation 17, a and b indicate transition coefficients of the output signal OUT. The transition coefficients a and b are coefficients indicating a ratio with respect to the power supply voltage V _DD . α ₁ , α ₂ , β ₁ , β ₂ , and γ indicate constant values excluding variables for output time t _out . The output time t _out is determined by the threshold voltage V _t , the width W _p and the transition points a and b of the pMOS transistor. The ratio χ of the output time before the body bias voltage is applied and the output time after the body bias voltage is applied may be derived with reference to Equation 17.

Equation 18 is an equation showing the ratio χ of the output time t _{out , nbb} before the body bias voltage is applied and the output time t _{out , bb} after the body bias voltage is applied. Referring to Equation 18, the output time ratio χ is the threshold voltage (V _{t , nbb} ) of the pMOS transistor before the body bias voltage is applied, and the threshold voltages (V _{t , bb)} of the pMOS transistor after the body bias voltage is applied. ), the width W _p of the pMOS transistor, and transition time points a and b. In this case, the threshold voltages V _{t and nbb} of the pMOS transistor before the body bias voltage is applied, the threshold voltages V _{t and bb} of the pMOS transistor after the body bias voltage is applied, and the transition points a and b. May be predetermined or measured values. Thus, the variable associated with the output time ratio χ may be the width W _p of the pMOS transistor.

Equation 19 shows an amount of change in the output time ratio according to the change in the width of the pMOS transistor W _p . With reference to Equation 19, the change amount of the output time ratio χ according to the change in the pMOS transistor width W _p in the first to fifth cases I to V shown in FIG. 6B may be obtained.

First, in the first case (I, t _in <d _{a , nbb} , t _in <d _{a , bb} ), the change amount of the output time ratio according to the change of the pMOS transistor width W _p is expressed by Equation 20. Referring to Equation 20, κ ₄ indicates constant values except W _p . Since 1 / κ ₄ is 0, there is no change in the output time ratio χ according to the change in the pMOS transistor width W _p . That is, in the first case (t, t _in <d _{a, nbb} , t _in <d _{a , bb} ), the output time ratio χ is independent of the width of the pMOS transistor.

Next, in the second case (II, t _in <d _{b , nbb} , d _{a , bb} <t _in <d _{b , bb} ), the change amount of the output time ratio χ according to the change of the pMOS transistor width W _p is shown. Is as shown in Equation 21. Referring to Equation 21, κ ₅ indicates constant values except W _p . Since 1 / κ ₅ is much smaller than 1, the amount of change in the output time ratio χ by the change in the pMOS transistor width W _p is so small that it can be ignored.

Next, in the third case (III, d _{a , nbb} <t _in <d _{b , nbb} , d _{a , bb} <t _in <d _{b , bb} ), the output time ratio according to the change of the pMOS transistor width W _{p is} shown. The change amount of (χ) is shown in Equation 22. Referring to Equation 22, κ ₆ indicates constant values except W _p . Since 1 / κ ₅ is much smaller than 1, the amount of change in the output time ratio χ according to the change in the pMOS transistor width W _p is negligibly small.

Next, in the fourth case (IV, d _{a , nbb} <t _in <d _{b , nbb} , d _{b , bb} <t _in ), the change amount of the output time ratio χ according to the change of the pMOS transistor width W _p is shown. Is as shown in Equation 23. Referring to Equation 23, κ ₇ indicates constant values except W _p . Since 1 / κ ₇ is much smaller than 1, the amount of change in the output time ratio χ caused by the change in the width of the pMOS transistor W _p is negligibly small.

Finally, in the fifth case (V, d _{b , nbb} <t _in , d _{b , bb} <t _in ), the change amount of the output time ratio χ according to the change of the pMOS transistor width W _p is expressed by Equation 24 and same. Referring to Equation 24, κ ₈ indicates constant values except W _p . Since the value of 1 / κ ₈ is 0, there is no change in the output time ratio χ according to the change in the pMOS transistor width W _p . That is, in the fifth case, the output time ratio may be independent of the width of the pMOS transistor.

As described with reference to Equations 20 to 24, in both the first to fifth cases (I to V), the amount of change in the output time ratio χ to the change in the pMOS transistor width W _p is small or very small. Therefore, in both the first to fifth cases (I to V), the output time ratio χ may be independent of the pMOS transistor width W _p .

As described above, when the ratio of the output time of the gate is modeled and combined with the gate output time table, the output time of the gate after applying the body bias can be predicted. In addition, since the ratio of output time of the standard gate is modeled by considering only the structure of the gate (for example, the number of stacks of transistors and the number of stages), unnecessary overhead may be reduced. Since the modeling method of the output time according to the gate structure is similar to the delay modeling method according to the gate structure described above, the description thereof is omitted.

7 is a flowchart illustrating a method of modeling a gate delay time according to an exemplary embodiment of the present invention. For the sake of brevity, the method of modeling the gate delay time is described with reference to FIG. 7, but the gate output time according to the present invention may also be modeled by the method according to the flowchart shown in FIG. 7. By way of example, the gate delay time and output time will be modeled based on the equations described above.

Referring to FIG. 7, in step S110, some of the plurality of gates included in the chip are selected. The selected gate may be a particular one of the gates having the same structure (eg, the same number of stacked transistors and the multi-stage structure).

In step S120, the structure of the selected gate is determined. For example, the number of stacks of selected gates and the number of stages can be determined.

In step S130, the delay time ratio is generated according to the determination result of step S120. For example, the delay time ratio of the gate may be generated according to the classification result of step S120 based on the above-described equation. In exemplary embodiments, the delay time ratio of the generated gate may be stored in an information storage medium (eg, a semiconductor memory, a floppy disk, a compact disk, a hard disk, or the like).

In operation S140, the delay time of the selected gate may be calculated based on the generated delay time ratio. For example, the delay time of the selected gate before applying body bias can be predetermined or measured. Therefore, the delay time of the selected gate after applying the body bias may be calculated based on the delay time of the selected gate and the generated delay time ratio before applying the body bias voltage. For example, in gates having the same structure as the selected gate, the delay time after applying the body bias voltage may be calculated based on the generated delay ratio.

In operation S150, a delay table may be generated based on the calculation result of operation S140. The generated table may be stored in a storage medium (eg, semiconductor memory, floppy disk, compact disk, hard disk, etc.).

According to the gate delay time modeling method of the present invention described above, the delay time of all the gates to which the body bias voltage is applied can be estimated while minimizing unnecessary overhead. The predicted latency information is used to provide stable operating performance, reduced cost, or reduced area in chip or circuit design.

In the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the following claims.

200: inverter gate
300: NOR gate
400: AND gate

Claims (7)

In the delay time modeling method of a plurality of gates,
Selecting a first gate of the plurality of gates;
Determining a structure of the selected first gate;
Generating a delay time ratio of the selected first gate according to the determination result; And
Calculating a delay time of the second gate when a body bias voltage is applied based on the generated delay time ratio and the delay time of the second gate of the plurality of gates,
The first and second gates have the same number of stacks and number of stages,
The number of stacks is the number of transistors between a power supply voltage and an output terminal of the first and second gates,
And the number of stages is a number of transistors between an input terminal and an output terminal of the first and second gates. The method of claim 1,
And the delay time is a time point at which the output signal is 1/2 times the power supply voltage from a time point at which the input signal changes. 3. The method of claim 2,
And transistors included in each of the first and second gates have different widths. The method of claim 1,
Determining the structure of the selected gate,
Determining whether the selected gate is a multi-stage structure; And
And determining whether the selected gate is a stack structure. 5. The method of claim 4,
Generating a delay time ratio according to the determination result,
And generating different delay time ratios according to the determined multi-stage structure and the determined stack structure. The method of claim 1,
Calculating a delay time of each of the plurality of gates when the body bias voltage is applied, based on the delay time of each of the plurality of gates and the generated delay time ratio. Way. In the output time modeling method of a plurality of gates,
Selecting a first gate of the plurality of gates;
Determining a structure of the selected first gate;
Generating an output time ratio according to the determination result; And
Calculating an output time of the second gate when a body bias voltage is applied, based on the generated output time ratio and the output time of the second gate of the plurality of gates,
Each of the first and second gates has the same number of stacks and number of stages as each other,
The number of stacks is the number of transistors between a power supply voltage and an output terminal of the first and second gates,
And the number of stages is the number of transistors between an input terminal and an output terminal of the first and second gates.

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