KR20140030460A - Step shape semiconductor memory device and method for manufacturing of the same - Google Patents

Abstract

The present invention relates to a stepped semiconductor memory device and a method for manufacturing the same. A stepped insulating layer is formed by performing a slimming process on the upper part of the semiconductor substrate. After that, memory cells are formed on the sidewall of the stepped insulating layer by performing a spacer etching process and a material layer (conductive layer, insulating layer) deposition process several times. In the present invention, when the material layer is patterned, a spacer etching process is mainly used and the number of photolithography processes which causes loss at a relatively high cost can be minimized. Because the memory cells have a stepped structure, high integration can easily be realized.

Description

Step shape semiconductor memory device and method for manufacturing of the same

The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly to a stepped phase change memory device and a method for manufacturing the same.

With the rapid development of the information and communication field and the rapid popularization of information media, the demand for next-generation semiconductor memory devices capable of ultra-fast operation and large memory storage capacity is increasing.

Next-generation semiconductor memory devices have been developed to take advantage of volatile memory devices such as DRAM and nonvolatile memory devices such as flash memory, and have excellent data retention and read / write operation characteristics with low power consumption during driving.

As such next-generation semiconductor memory devices, devices such as PCRAM (Phase Change Random Access Memory), RRAM (Resistive Random Access Memory), STT-RAM (Spin Transfer Torque Random Access Memory) or PoRAM (Polymer Random Access Memory) have been actively studied. .

Meanwhile, in manufacturing the semiconductor memory devices as described above, the improvement in the degree of integration of a two-dimensional structure in which memory cells in which an integrated circuit is implemented is planarly disposed on a printed circuit board (PCB) has reached its limit. Therefore, in recent years, various developments have been made to the technology related to a three-dimensional structure in which memory cells are vertically stacked from a substrate.

In general, a semiconductor memory device is manufactured by repeatedly performing a number of unit processes such as an ion implantation process (impurity diffusion process), a deposition process, an etching process, a planarization process, a cleaning process, a drying process, and a packaging process.

In particular, among the etching processes for forming the pattern, the photolithography process is a process involving a mask fabrication, a photoresist coating, an exposure / development process, and the like, including a bit line and a word line of a semiconductor memory device. It is a process that plays a very basic and important role used to make unit patterns.

However, with the higher integration of semiconductor memory devices, the line width of the pattern is smaller than the exposure limit resolution, so that the difficulty of the process is gradually increased, thereby increasing the fail generation rate. In addition, each mask is manufactured separately for each unit pattern constituting the memory cell, thereby increasing manufacturing cost.

Accordingly, various methods for minimizing the photolithography process have been studied in order to increase the yield of semiconductor memory devices and reduce manufacturing costs.

An object of the present invention is to provide a stepped semiconductor memory device and a method of manufacturing the same to minimize the number of photolithography process.

Another object of the present invention is to provide a stepped semiconductor memory device and a method for manufacturing the same, which can increase the yield and minimize the manufacturing cost.

Another object of the present invention is to provide a stepped semiconductor memory device and a method for manufacturing the same, which are advantageous for high integration.

A stepped semiconductor memory device according to a first embodiment of the present invention includes a stepped insulating film formed on a semiconductor substrate through a slimming process; A plurality of memory cells formed on the sidewalls of the stepped insulating layer and having the top surface of the data storage material collinear with other surrounding material films; A stepped word line formed on the stepped insulating layer and formed under the memory cell; And a bit line intersecting the word line on the memory cell.

A stepped semiconductor memory device according to a second embodiment of the present invention includes a stepped insulating film formed on a semiconductor substrate through a slimming process; A plurality of memory cells formed on a side of the stepped insulating layer and having a top surface of the data storage material higher than other material films in the vicinity; A stepped word line formed on the stepped insulating layer and formed under the memory cell; And a bit line intersecting the word line on the memory cell.

In the manufacturing method of the stepped semiconductor memory device according to the first embodiment of the present invention, the step of depositing a first interlayer insulating film on the semiconductor substrate, and repeating the etching process on the first interlayer insulating film to form a step structure Wow; Depositing a conductive film for a word line on the first interlayer insulating film of the staircase structure; Depositing a second interlayer insulating film on the word line conductive film, and etching the second interlayer insulating film to form the second interlayer insulating film on sidewalls of the word line conductive film; Depositing a third interlayer dielectric layer on the semiconductor substrate on which the second interlayer dielectric layer is formed, and etching the third interlayer dielectric layer to form the third interlayer dielectric layer on sidewalls of the second interlayer dielectric layer; After depositing a fourth interlayer dielectric layer on the semiconductor substrate on which the third interlayer dielectric layer is formed, an etching process is performed from the fourth interlayer dielectric layer to the word line conductive layer to separate the word line conductive layers into individual word lines. Separating into; Depositing a fifth interlayer dielectric layer on the semiconductor substrate on which the individual word lines are formed, thereby gap filling the grooves between the individual word lines; Performing an etching process on the semiconductor substrate on which the fifth interlayer insulating film is deposited to expose an upper surface of the third interlayer insulating film, and then removing the exposed third interlayer insulating film; Forming a data storage material in the hole from which the third interlayer insulating film is removed; Forming a bit line on the data storage material.

According to the present invention, a stepped insulating film is formed on a semiconductor substrate through a slimming process, and then a plurality of material film (conductive film, insulating film) deposition processes and a spacer etching process are performed to form a plurality of sidewalls of the stepped insulating film. Form a memory cell.

As described above, in the present invention, when the material film is patterned, the spacer etching process is mainly used, and the yield can be increased and the manufacturing cost can be reduced by minimizing the number of photolithography processes, which are relatively costly compared with other processes for the material pattern. Will be.

In addition, a plurality of memory cells have a step structure, which is more advantageous for high integration.

1 shows a stepped semiconductor memory device according to a first embodiment of the present invention.
2A to 2N illustrate a manufacturing process of a stepped semiconductor memory device according to a first embodiment of the present invention.
3 shows a stepped semiconductor memory device according to a second embodiment of the present invention.
4A to 4N illustrate a manufacturing process of a stepped semiconductor memory device according to a second embodiment of the present invention.

Hereinafter, a stepped semiconductor memory device and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 shows a stepped semiconductor memory device according to a first embodiment of the present invention.

Referring to FIG. 1, a stepped insulating film 102 formed through a slimming process on the semiconductor substrate 100 is illustrated. In addition, a plurality of memory cells 120 are formed at the side of the stepped insulating layer 102. The word line 106a and the bit line 122a are cross-connected to the lower and upper portions of the memory cell 120, respectively.

In the present invention, in forming the memory cell 120, a plurality of material film (conductive film, insulating film) deposition processes and spacer etching processes are performed, and photolithography, which has a relatively high cost loss compared to other processes for material patterns. By minimizing the number of processes, manufacturing costs can be reduced.

Next, a manufacturing process of the memory cell 120 will be described in more detail with reference to the following drawings.

2A through 2N sequentially illustrate a step of manufacturing a stepped semiconductor memory device according to a first embodiment of the present invention. In this case, for convenience of description, only the left "A" region of the semiconductor memory device illustrated in FIG. 1 will be referred to.

Referring to FIG. 2A, a first interlayer insulating film 102 is deposited on the semiconductor substrate 100. Then, a normal slimming process is performed to form the first interlayer insulating film 102 in a stepped structure.

As shown in FIG. 2A, a plurality of sidewalls 104 exist in the first interlayer insulating film 102 of the staircase structure as many times as a slimming process. In the present invention, a plurality of memory cells are formed on the sidewalls 104 through a plurality of material film deposition processes and a spacer etching process.

Referring to FIG. 2B, a word line conductive layer 106 is deposited on the first interlayer insulating layer 102.

In this case, as the conductive film 106 for the word line, for example, a metal, an alloy, a metal oxynitride, or a conductive carbon compound may be used. More specifically, W, Cu, TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, TaAlN, Ti, Mo, Ta, TiSi, TaSi , TiW, TiON, TiAlON, WON, TaON and the like can be used.

Referring to FIG. 2C, a second interlayer insulating layer 108 is deposited on the word line conductive layer 106.

Referring to FIG. 2D, a first spacer etching process is performed on the second interlayer insulating film 108. As a result, the second interlayer insulating film 108 is present only on the sidewalls and a part of the upper portion of the conductive film 106 for the word line. More specifically, the first end to the fourth end (106-1, 106-2, 106-3, 106-4) and the fifth end (106-5) of the conductive film for the word line 106 The second interlayer insulating film 108 is present on the sidewalls and a part of the upper portion.

Referring to FIG. 2E, a third interlayer insulating film 110 is deposited on the resultant. In this case, the third interlayer insulating film 110 may be deposited using a different type of insulating material from the second interlayer insulating film 108.

Referring to FIG. 2F, a second spacer etching process is performed on the third interlayer insulating film 110. As a result, the third interlayer insulating film 110 is present only on the sidewalls of the second interlayer insulating film. More specifically, only the first end to the sixth end 108-1, 108-2, 108-3, 108-4, 108-5, 108-6 of the second interlayer insulating film 108 do.

In this case, the second interlayer dielectric layer 108 should not be removed together during the spacer etching of the third interlayer dielectric layer 110. To this end, as already mentioned, the third interlayer insulating film 110 and the second interlayer insulating film 108 are preferably deposited with different kinds of insulating materials, and the second interlayer insulating film 108 It is preferable to perform a spacer etching process on the third interlayer insulating film 110 using an etchant having an excellent etching selectivity.

Referring to FIG. 2G, a fourth interlayer insulating layer 112 is deposited on the resultant. In this case, the fourth interlayer insulating film 112 may be deposited using the same insulating material or a different insulating material from that of the second interlayer insulating film 108.

Referring to FIG. 2H, a photolithography process is performed to reach from the fourth interlayer insulating film 112 to the conductive film for word lines 106. As a result, grooves 114 having a predetermined interval from the fourth interlayer insulating film 112 to the word line conductive film 106 are formed so that the word line conductive film 106 is formed on each individual word line 106a. Separated by.

Referring to FIG. 2I, a fifth interlayer insulating layer 116 is deposited on the semiconductor substrate 100 on which the individual word lines 106a are formed to form grooves 114 between the individual word lines 106a. Gap fill. In this case, the fifth interlayer insulating layer 116 may be deposited using the same insulating material or different insulating materials from those of the interlayer insulating layers 102, 108, 110, and 112 previously used.

Referring to FIG. 2J, a third spacer etching process is performed on the semiconductor substrate 100 on which the fifth interlayer insulating layer 116 is deposited. As a result, the top surfaces of the second interlayer insulating film 108 and the third interlayer insulating film 110 are exposed. Alternatively, a normal slimming process may be performed in addition to the spacer etching process to expose the top surfaces of the second interlayer insulating film 108 and the third interlayer insulating film 110.

As a result of the spacer etching process, the third interlayer insulating layer 110 is separated at a predetermined interval and is surrounded by other interlayer insulating layers to form a plurality of islands.

Referring to FIG. 2K, a dipout process is performed on the island-type third interlayer insulating film 110. As a result, a hole 118 is formed in the region where the third interlayer insulating film 110 is removed.

Referring to FIG. 2L, the data storage material 120 is deposited on the semiconductor substrate 100 on which the holes 118 are formed. In this case, the data storage material 120 is deposited to a thickness sufficient to completely fill the data storage material 120 in the hole 118. Then, an etch back process is performed on the semiconductor substrate 100 on which the data storage material 120 is formed so that the data storage material 120 remains only inside the hole 118.

In this case, the PCRAM, the RRAM, the STT-RAM, the PoRAM, etc. may be formed according to the type of the data storage material buried in the hole 118.

For example, when forming a PCRAM, a diode and a data storage material are sequentially deposited in the hole 118.

The diode is a switching element for selecting a cell, and may be formed of Si, SiGe, Ge, GaAs, or the like, or may be formed of a PN diode or a Schottky diode.

The data storage material may be formed of a material selected from the group consisting of Te, Se, Ge, mixtures thereof, and alloys thereof. More specifically, the data storage material may be formed of Te, Se, Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O, N, and mixtures or alloys thereof. When the data storage material is embedded, a spacer (not shown) may be further formed on the inner sidewall of the hole 118 to reduce the cross-sectional area.

In addition, a heater (not shown) may be further formed on the diode, and the heater may be formed of an alloy, a metal oxynitride, a conductive carbon compound, or the like, which is a material used to form the word line 106a. More specifically, W, Cu, TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, TaAlN, Ti, Mo, Ta, TiSi, TaSi, TiW , TiON, TiAlON, WON, TaON and the like. Alternatively, the present invention may be formed of a material having mixed ionic electronic conductor (MIEC) and ovix threshold switch (OTS) characteristics.

In addition, an ohmic layer (not shown) may be further formed to reduce contact resistance between the diode, which is the switching element, and the interface of the heater. In this case, the ohmic layer may be formed of silicide, for example.

Referring to FIG. 2M, a bit line conductive layer 122 is deposited on the semiconductor substrate 100 on which the data storage material 120 is formed. In this case, as the bit line conductive film 122, for example, a metal, an alloy, a metal oxynitride, or a conductive carbon compound may be used. More specifically, W, Cu, TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, TaAlN, Ti, Mo, Ta, TiSi, TaSi , TiW, TiON, TiAlON, WON, TaON and the like can be used.

Referring to FIG. 2N, a fourth spacer etching process may be performed on the bit line conductive layer 122. As a result, a bit line conductive layer remains on only the data storage material 120 to form each individual bit line 122a. In addition, the separated bit lines 122a are cross-connected with the lower word lines 106a to selectively drive the cells.

As described above, in the present invention, a stepped insulating film is formed on the semiconductor substrate through a slimming process, and then a plurality of material film (conductive film, insulating film) deposition processes and a spacer etching process are performed. Form a plurality of memory cells in the.

Specifically, in the process of manufacturing the semiconductor memory device illustrated in FIGS. 2A through 2N, that is, in the process of forming the upper bit line from the lower word line, the photolithography process separates the conductive film for the word line into individual word lines. It was applied once in the process (Fig. 2g → 2h).

As described above, the present invention mainly uses a spacer etching process in patterning a material film, while minimizing the number of photolithography processes, which are relatively costly and have high cost, compared to other etching processes for pattern formation. It is possible to increase the cost and reduce the manufacturing cost. In addition, since a plurality of memory cells have a step structure, it is more advantageous for high integration.

3 shows a stepped semiconductor memory device according to a second embodiment of the present invention.

Referring to FIG. 3, a stepped insulating film 202 is formed on the semiconductor substrate 200 through a slimming process. In addition, a plurality of memory cells 220 are formed at the side of the stepped insulating layer 202. The word line 206a and the bit line 222a are cross-connected to the lower and upper portions of the memory cell 220, respectively.

Comparing the memory cell 220 with the memory cell 120 of FIG. 1, the memory cell 120 of FIG. 1 has a data storage material formed only inside the hole 118, whereas the memory cell of FIG. 220 is a form in which the data storage material remains a certain thickness inside and above the hole (“218” in FIG. 4K).

In the present invention, in forming the memory cell 220, a plurality of material film (conductive film, insulating film) deposition processes and spacer etching processes are performed, and photolithography, which has a relatively high cost loss compared to other processes for material patterns. By minimizing the number of processes, manufacturing costs can be reduced.

Next, a manufacturing process of the memory cell 220 will be described in more detail with reference to the following drawings.

4A to 4N sequentially illustrate a manufacturing process of the stepped semiconductor memory device according to the second embodiment of the present invention. In this case, for convenience of description, only the left "B" region of the semiconductor memory device illustrated in FIG. 1 will be referred to. 4A through 4K are the same as the manufacturing process of the semiconductor memory device according to the first embodiment.

Referring to FIG. 4A, a first interlayer insulating film 202 is deposited on the semiconductor substrate 200. Then, a normal slimming process is performed to form the first interlayer insulating film 202 in a staircase structure.

As shown in FIG. 4A, a plurality of sidewalls 204 are present in the first interlayer insulating film 202 of the staircase structure for the number of slimming processes. In the present invention, a plurality of memory cells may be formed on the sidewall 204 through a plurality of material film deposition processes and a spacer etching process.

Referring to FIG. 4B, a word line conductive film 206 is deposited on the first interlayer insulating film 202.

In this case, as the conductive film 206 for the word line, for example, a metal, an alloy, a metal oxynitride, or a conductive carbon compound may be used. More specifically, W, Cu, TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, TaAlN, Ti, Mo, Ta, TiSi, TaSi , TiW, TiON, TiAlON, WON, TaON and the like can be used.

Referring to FIG. 4C, a second interlayer insulating film 208 is deposited on the word line conductive film 206.

Referring to FIG. 4D, a first spacer etching process is performed on the second interlayer insulating film 208. As a result, the second interlayer insulating film 208 is present only on the sidewalls of the word line conductive film 206 and a part of the upper portion. More specifically, the first end to the fourth end (206-1, 206-2, 206-3, 206-4) of the word line conductive film 206 of the sidewall, the fifth end (206-5) The second interlayer insulating layer 208 is present on the sidewalls and a part of the upper portion.

Referring to FIG. 4E, a third interlayer insulating layer 210 is deposited on the resultant. In this case, the third interlayer insulating film 210 may be deposited using a different type of insulating material from the second interlayer insulating film 208.

Referring to FIG. 4F, a second spacer etching process is performed on the third interlayer insulating film 210. As a result, the third interlayer insulating film 210 is present only on sidewalls of the second interlayer insulating film. More specifically, the second interlayer insulating film 208 is present only on the sidewalls of the first to sixth ends 208-1, 208-2, 208-3, 208-4, 208-5, and 208-6. do.

In this case, the second interlayer dielectric layer 208 should not be removed together during the spacer etching of the third interlayer dielectric layer 210. To this end, as already mentioned, the third interlayer insulating film 210 and the second interlayer insulating film 208 are preferably deposited with different kinds of insulating materials, and the second interlayer insulating film 208 It is preferable to perform a spacer etching process on the third interlayer insulating film 210 by using an etchant having an excellent etching selectivity.

Referring to FIG. 4G, a fourth interlayer insulating film 212 is deposited on the resultant. In this case, the fourth interlayer insulating film 212 may be deposited using the same insulating material or a different insulating material from that of the second interlayer insulating film 208.

Referring to FIG. 4H, a photolithography process is performed from the fourth interlayer insulating film 212 to the word line conductive film 206. As a result, grooves 214 having a predetermined interval from the fourth interlayer insulating film 212 to the word line conductive film 206 are formed so that the word line conductive film 206 is formed on each individual word line 206a. Separated by.

Referring to FIG. 4I, a fifth interlayer insulating layer 216 is deposited on the semiconductor substrate 200 on which the individual word lines 206a are formed, and thus grooves 214 are present between the individual word lines 206a. Gap fill In this case, the fifth interlayer insulating film 216 may be deposited using the same insulating material or different insulating materials from those of the interlayer insulating films 202, 208, 210, and 212, which have been previously used.

Referring to FIG. 4J, a third spacer etching process is performed on the semiconductor substrate 200 on which the fifth interlayer insulating layer 216 is deposited. As a result, upper surfaces of the second interlayer insulating film 208 and the third interlayer insulating film 210 are exposed. Alternatively, an upper surface of the second interlayer insulating film 208 and the third interlayer insulating film 210 may be exposed by performing a normal slimming process in addition to the spacer etching process.

As a result of the spacer etching process, the third interlayer dielectric layer 210 is separated at regular intervals and surrounded by other interlayer dielectric layers to form a plurality of islands.

Referring to FIG. 4K, a dipout process is performed on the island-type third interlayer insulating film 210. As a result, a hole 218 is formed in the region where the third interlayer insulating film 210 is removed.

Referring to FIG. 4L, the data storage material 220 is deposited on the semiconductor substrate 200 on which the hole 218 is formed. In this case, the data storage material 220 is deposited to a thickness sufficient to completely fill the data storage material 220 in the hole 218. Then, a photolithography process is performed on the semiconductor substrate 200 on which the data storage material 220 is formed to store data having a predetermined thickness in the direction in which the inside of the hole 218 and the hole 218 are formed side by side. Allow material 220 to remain.

When comparing the shapes of the data storage material 120 and the data storage material 220 according to the second embodiment shown in FIG. 2L, the following differences exist.

In the first embodiment, the data storage material 120 is formed only inside the hole 118, so that the data storage material 120 is horizontal to the surrounding insulating film. In the second embodiment, the data storage material 120 is formed inside the hole 218. The data storage material 220 having a predetermined thickness is formed in the direction in which the holes 218 are formed side by side, and protrude from the surrounding insulating film. This derived area (reference numeral "C") may facilitate electrical connection with the bit line (formed through a subsequent process) as compared with the data storage material 120 of the first embodiment.

In this case, the PCRAM, the RRAM, the STT-RAM, and the PoRAM may be formed according to the type of the data storage material buried in the hole 218.

For example, when forming a PCRAM, a diode and a data storage material are sequentially deposited in the hole 218.

The diode is a switching element for selecting a cell, and may be formed of Si, SiGe, Ge, GaAs, or the like, or may be formed of a PN diode or a Schottky diode.

The data storage material may be formed of a material selected from the group consisting of Te, Se, Ge, mixtures thereof, and alloys thereof. More specifically, the data storage material may be formed of Te, Se, Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O, N, and mixtures or alloys thereof. When the data storage material is embedded, a spacer (not shown) may be further formed on the inner sidewall of the hole 218 to reduce the cross-sectional area.

In addition, a heater (not shown) may be further formed on the diode, and the heater may be formed of an alloy, a metal oxynitride, a conductive carbon compound, or the like, which is a material used to form the word line 206a. More specifically, W, Cu, TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, TaAlN, Ti, Mo, Ta, TiSi, TaSi, TiW , TiON, TiAlON, WON, TaON and the like. Alternatively, the present invention may be formed of a material having mixed ionic electronic conductor (MIEC) and ovix threshold switch (OTS) characteristics.

In addition, an ohmic layer (not shown) may be further formed to reduce contact resistance between the diode, which is the switching element, and the interface of the heater. In this case, the ohmic layer may be formed of silicide, for example.

Referring to FIG. 4M, a bit line conductive layer 222 is deposited on the semiconductor substrate 200 on which the data storage material 220 is formed. In this case, as the bit line conductive film 222, for example, a metal, an alloy, a metal oxynitride, or a conductive carbon compound may be used. More specifically, W, Cu, TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, TaAlN, Ti, Mo, Ta, TiSi, TaSi , TiW, TiON, TiAlON, WON, TaON and the like can be used.

Referring to FIG. 4N, a fourth spacer etching process is performed on the bit line conductive layer 222. As a result, a bit line conductive layer remains on only the data storage material 220 to form each individual bit line 222a. In addition, the discrete bit lines 222a are cross-connected with the lower word lines 206a to selectively drive the cells.

As described above, in the present invention, a stepped insulating film is formed on the semiconductor substrate through a slimming process, and then a plurality of material film (conductive film, insulating film) deposition processes and a spacer etching process are performed. Form a plurality of memory cells in the.

Specifically, in the process of manufacturing the semiconductor memory device illustrated in FIGS. 4A to 4N, that is, in the process of forming the upper bit line from the lower word line, the photolithography process separates the conductive film for the word line into individual word lines. In the process of forming the data storage material 220 inside the hole 218 (FIG. 4G-> 4H) and in the process (4k-4L), it was applied twice.

As described above, the present invention mainly uses a spacer etching process in patterning a material film, while minimizing the number of photolithography processes, which are relatively costly and have high cost, compared to other etching processes for pattern formation. It is possible to increase the cost and reduce the manufacturing cost. In addition, since a plurality of memory cells have a step structure, it is more advantageous for high integration.

While the present invention has been particularly shown and described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It can be understood that Therefore, the embodiments described above are to be understood in all respects as illustrative and not restrictive.

100,200: semiconductor substrate 102,202: first interlayer insulating film
104, 204: side walls 106, 206: conductive film for word lines
106a, 206a: wordline 108,208: second interlayer insulating film
110,210: third interlayer insulating film 112,212: fourth interlayer insulating film
114,214: groove 116,216: fifth interlayer insulating film
118,218: Hall 120,220: data storage material
122, 222: bit line conductive films 122a, 222a: bit line

Claims (18)

A stepped insulating film formed on the semiconductor substrate through a slimming process;
A plurality of memory cells formed on the sidewalls of the stepped insulating layer and having the top surface of the data storage material collinear with other surrounding material films;
A stepped word line formed on the stepped insulating layer and formed under the memory cell; And
And a bit line intersecting the word line on the memory cell. A stepped insulating film formed on the semiconductor substrate through a slimming process;
A plurality of memory cells formed on a side of the stepped insulating layer and having a top surface of the data storage material higher than other material films in the vicinity;
A stepped word line formed on the stepped insulating layer and formed under the memory cell; And
And a bit line intersecting the word line on the memory cell. Depositing a first interlayer dielectric layer on the semiconductor substrate, and repeating an etching process on the first interlayer dielectric layer to form a stepped structure;
Depositing a conductive film for a word line on the first interlayer insulating film of the staircase structure;
Depositing a second interlayer insulating film on the word line conductive film, and etching the second interlayer insulating film to form the second interlayer insulating film on sidewalls of the word line conductive film;
Depositing a third interlayer dielectric layer on the semiconductor substrate on which the second interlayer dielectric layer is formed, and etching the third interlayer dielectric layer to form the third interlayer dielectric layer on sidewalls of the second interlayer dielectric layer;
After depositing a fourth interlayer dielectric layer on the semiconductor substrate on which the third interlayer dielectric layer is formed, an etching process is performed from the fourth interlayer dielectric layer to the word line conductive layer to separate the word line conductive layers into individual word lines. Separating into;
Depositing a fifth interlayer dielectric layer on the semiconductor substrate on which the individual word lines are formed, thereby gap filling the grooves between the individual word lines;
Performing an etching process on the semiconductor substrate on which the fifth interlayer insulating film is deposited to expose an upper surface of the third interlayer insulating film, and then removing the exposed third interlayer insulating film;
Forming a data storage material in the hole from which the third interlayer insulating film is removed;
Forming a bit line on the data storage material. The method of claim 3, wherein the word line conductive film is formed of a metal, an alloy, a metal oxynitride, or a conductive carbon compound. The method of claim 4, wherein the conductive film for the word line is W, Cu, TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, TaAlN, Ti, A method of manufacturing a stepped semiconductor memory device formed of Mo, Ta, TiSi, TaSi, TiW, TiON, TiAlON, WON, TaON, and the like. The stepped semiconductor memory device of claim 3, wherein the data storage material is formed of a material selected from the group consisting of Te, Se, Ge, mixtures thereof, and alloys thereof. Way. The stepped semiconductor memory of claim 6, wherein the data storage material is formed of Te, Se, Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O, N, and mixtures or alloys thereof. Method of manufacturing the device. 4. The method of claim 3, further comprising forming a spacer in the hole from which the third interlayer insulating film is removed to reduce the cross-sectional area when forming the data storage material. 8. The method of claim 7, wherein the switching element for selecting the PCRAM is formed of Si, SiGe, Ge, GaAs, or the like. 10. The method of claim 9, wherein the switching element is a PN diode or a Schottky diode. The method of claim 10, wherein a heater is formed on the switching element by an alloy, a metal oxynitride, a conductive carbon compound, or the like. The method of claim 11, wherein the heater is W, Cu, TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, TaAlN, Ti, Mo, Ta A method of manufacturing a stepped semiconductor memory device, which is formed of TiSi, TaSi, TiW, TiON, TiAlON, WON, TaON and the like. The method of claim 12, wherein the heater is formed of a material having characteristics of Mixed Ionic Electronic Conductor (MIEC) and Ovonix Threshold Switch (OTS). The method of claim 13, further comprising performing a silicide process to reduce the contact resistance between the diode and the interface between the heaters. The method of claim 3, wherein the bit line is formed of a metal, an alloy, a metal oxynitride, or a conductive carbon compound. The method of claim 15, wherein the bit line is W, Cu, TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, TaAlN, Ti, Mo, A method for manufacturing a stepped semiconductor memory device formed of Ta, TiSi, TaSi, TiW, TiON, TiAlON, WON, TaON, and the like. 4. The method of claim 3 wherein the top surface of the data storage material is co-linear with the surrounding material film. 4. The method of claim 3 wherein the top surface of the data storage material is higher than other surrounding material films.

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