KR20130079093A - Semiconductor package having redistribution layer - Google Patents

Abstract

PURPOSE: A semiconductor package capable of having a rewiring layer is provided to form the wirings, which transmit a data signal, in an upper level than the lowest memory chip among the memory chips, thereby simplifying a substrate inner wire. CONSTITUTION: A plurality of first semiconductor chip has the data pads (91) and the power pads (92). An upper wiring layer has a plurality of rewiring pattern (275,276) and a plurality of rewiring pad (291-294). A second semiconductor chip is formed on the most top of the first semiconductor chip. The first conductive connections are formed between the data pads and the second semiconductor chip. The second conductive connections are formed between the second semiconductor chip and the substrate.

Description

Technical Field [0001] The present invention relates to a semiconductor package having a redistribution layer,

The present invention relates to a semiconductor package having a plurality of semiconductor chips.

Various methods for implementing a semiconductor package having high-speed operation characteristics while mounting a plurality of semiconductor chips have been researched.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor package capable of shortening a signal transmission path and reducing the size thereof and mounting a plurality of semiconductor chips thereon.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other matters not mentioned can be clearly understood by those skilled in the art from the following description.

In order to achieve the above object, embodiments of the technical idea of the present invention provide a semiconductor package. The semiconductor package includes a plurality of first semiconductor chips mounted on a substrate and having data pads and power supply pads. An upper wiring layer having a plurality of rewiring patterns and a plurality of rewiring pads is formed on the uppermost first semiconductor chip among the first semiconductor chips. And a second semiconductor chip is mounted on the uppermost first semiconductor chip so as to be close to the data pads. First conductive connections are formed between the data pads and the second semiconductor chip. And second conductive connections are formed between the second semiconductor chip and the substrate. The rewiring patterns are arranged at the same level and are not overlapped with each other. Wherein the data pads of the first semiconductor chips are electrically connected to the substrate via the first conductive connections, the second semiconductor chip, the rewiring patterns, the rewiring pads, and the second conductive connections. do.

At least one of the rewiring pads may be in direct contact with one of the data pads of the uppermost first semiconductor chip.

The second semiconductor chip may be mounted so as to be relatively close to the data pads and relatively far from the power pads.

The first electrical connection path between the first semiconductor chips and the second semiconductor chip may be shorter than the second electrical connection path between the second semiconductor chip and the substrate.

The upper wiring layer may include first rewiring patterns formed between the data pads of the first semiconductor chips and the second semiconductor chip. The upper wiring layer may include second wiring patterns formed between the second semiconductor chip and the substrate. The first rewiring patterns may be shorter than the second rewiring patterns. The data pads of the first semiconductor chips sequentially pass through the first conductive connections, the first rewiring patterns, the second semiconductor chip, the second rewiring patterns, and the second conductive connections And may be connected to the substrate.

The upper wiring layer may include first rewiring pads formed between the data pads of the first semiconductor chips and the second semiconductor chip. The upper wiring layer may include redistribution patterns formed between the second semiconductor chip and the substrate. The upper wiring layer may include second and third rewiring pads formed at both ends of the rewiring patterns. The second semiconductor chip may be close to the first redistribution pads. The second conductive connections may be connected to the third rewiring pads. Wherein the data pads of the first semiconductor chips are electrically connected to the first rewiring pads, the second semiconductor chip, the second rewiring pads, the rewiring patterns, the third rewiring pads, And may be connected to the substrate sequentially through the conductive connections.

And a third conductive connection formed between the rewiring pads. The third conductive connection may traverse the top of at least one of the redistribution patterns. The third conductive connection may be separated from the rewiring patterns. The third conductive connection may include a bonding wire, a beam lead, or a conductive tape.

The upper wiring layer may partly cover the uppermost first semiconductor chip. The upper wiring layer may be absent between the uppermost first semiconductor chip and the second semiconductor chip.

The data pads of the first semiconductor chips may all be electrically connected to the substrate sequentially through the second semiconductor chip, the rewiring pads, the rewiring patterns, and the second conductive connections.

The substrate may include inter-substrate interconnects. Each of the wiring lines inside the substrate may be connected to the power supply pads of the first semiconductor chips or the second semiconductor chip.

And there is no wiring for connecting between the data pads of the first semiconductor chips and the second semiconductor chip in the substrate.

The length ratio of the major axis and the minor axis of the second semiconductor chip may be 1.2 or less.

The power supply pads of the first semiconductor chips can be directly connected to the substrate without passing through the second semiconductor chip.

And a buffer chip connected to the second semiconductor chip.

The buffer chip may be formed on the upper wiring layer.

The upper wiring layer may include first rewiring patterns formed between the data pads of the first semiconductor chips and the second semiconductor chip. The upper wiring layer may include second wiring patterns formed between the second semiconductor chip and the substrate. The upper wiring layer may include third wiring patterns formed between the second semiconductor chip and the buffer chip. The buffer chip may be connected to the second semiconductor chip via the third rewiring patterns.

Some of the first semiconductor chips may be sequentially offset aligned in a first direction to form a first chip stack. Another portion of the first semiconductor chips may be sequentially offset aligned in a second direction different from the first direction on the first chip stack to form a second chip stack. An intermediate wiring layer may be formed between the first chip stack and the second chip stack. The first semiconductor chips included in the first chip stack may be electrically connected to the upper wiring layer via the intermediate wiring layer.

In addition, embodiments of the inventive concept provide another semiconductor package. The semiconductor package includes a plurality of first semiconductor chips mounted on a substrate and having data pads and power supply pads. An upper wiring layer is formed on the uppermost first semiconductor chip among the first semiconductor chips. The upper wiring layer may include first and second rewiring patterns between the plurality of first rewiring pads, the first rewiring pads, and the second rewiring pads, a plurality of third rewiring lines, Pads, the second rewiring patterns between the third rewiring pads and the fourth rewiring pads, the plurality of fifth rewiring pads, the fifth rewiring pads, and the sixth rewiring pads, Third rewiring patterns between the rewiring pads, a plurality of seventh and eighth rewiring pads, and fourth rewiring patterns between the seventh rewiring pads and the eighth rewiring pads do. The first rewiring pads are in contact with the data pads of the uppermost first semiconductor chip. And the second semiconductor chip is mounted on the upper wiring layer. First conductive connections are formed between the first rewiring pads and the data pads. And second conductive connections are formed between the second rewiring pads and the second semiconductor chip. And third conductive connections are formed between the second semiconductor chip and the third rewiring pads. And fourth conductive connections are formed between the fourth rewiring pads and the substrate. And fifth conductive connections are formed between the second semiconductor chip and the fifth rewiring pads. Sixth conductive pads are formed between the sixth rewiring pads and the seventh rewiring pads. Seventh conductive connections are formed between the eighth rewiring pads and the substrate. The sixth conductive connections include a bonding wire, a beam lead, or a conductive tape. At least one of the first rewiring patterns and the second rewiring patterns is disposed between the sixth rewiring pads and the seventh rewiring pads. And the sixth conductive connections deviate from the first wiring patterns and the second wiring patterns.

In addition, embodiments of the inventive concept provide another semiconductor package. The semiconductor package includes a plurality of first semiconductor chips mounted on a substrate and having data pads and power supply pads. An upper wiring layer partially covering the uppermost first semiconductor chip of the first semiconductor chips is formed. The upper wiring layer includes a plurality of first rewiring pads, a plurality of second rewiring pads, and a plurality of rewiring patterns formed between the first rewiring pads and the second rewiring pads . And a second semiconductor chip is formed on the uppermost first semiconductor chip. First conductive contacts are formed between the first semiconductor chips in contact with the data pads. And second conductive connections are formed between the data pads of the second semiconductor chip and the top layer first semiconductor chip. Third conductive connections are formed between the second semiconductor chip and the first rewiring pads. And fourth conductive connections are formed between the second rewiring pads and the substrate. And the upper wiring layer is not provided between the uppermost first semiconductor chip and the second semiconductor chip. Wherein the data pads of the first semiconductor chips are electrically connected to the first conductive connections, the second conductive connections, the second semiconductor chip, the third conductive connections, the first rewiring pads, , The second rewiring pads, and the fourth conductive connections sequentially.

Further, embodiments of the technical idea of the present invention provide another semiconductor package. The semiconductor package includes a first semiconductor chip mounted on a substrate. A first conductive connection connecting the first semiconductor chip and the substrate is formed. A support mounted on the substrate and positioned at the same level as the first semiconductor chip is disposed. A plurality of second semiconductor chips mounted on the support and the first semiconductor chip and having data pads and power supply pads are provided. An adhesion film formed on the bottom surface of the lowermost second semiconductor chip of the second semiconductor chips and attached to the support and the first semiconductor chip is disposed. An upper wiring layer formed on the second uppermost semiconductor chip of the second semiconductor chips and electrically connected to the data pads is provided. A second conductive connection is formed between the data pads and the upper wiring layer. And is mounted on the upper wiring layer and is formed close to the data pads And a third semiconductor chip electrically connected to the upper wiring layer is disposed. And a third conductive connection is formed between the third semiconductor chip and the substrate. The first conductive connection passes through the interior of the adhesive film. The plurality of second semiconductor chips are electrically connected to the substrate sequentially through the data pads, the second conductive connection, the upper wiring layer, the third semiconductor chip, and the third conductive connection.

The length of the electrical connection path between the third semiconductor chip and the data pads is longer than the length of the electrical connection path between the third semiconductor chip and the substrate May be shorter than the electrical connection path.

Wherein the upper wiring layer includes a first rewiring pattern, first and second rewiring pads connected to both ends of the first rewiring pattern, a second rewiring pattern spaced apart from the first rewiring pattern, And a third and fourth rewiring pads connected to both ends of the second rewiring pattern. One end of the second conductive connection may be in contact with the first rewiring pad. And the second rewiring pad may be electrically connected to the third semiconductor chip. One end of the third conductive connection may be in contact with the fourth rewiring pad. And the third rewiring pad may be electrically connected to the third semiconductor chip. And a fourth conductive connection may be formed between the second rewiring pad and the third semiconductor chip. And a fifth conductive connection may be formed between the third rewiring pad and the third semiconductor chip.

The upper wiring layer may include a first rewiring pad, a second rewiring pattern separated from the first rewiring pad, and third and fourth rewiring pads connected to both ends of the second rewiring pattern. have. One end of the second conductive connection may be in contact with the first rewiring pad. The first rewiring pad may be electrically connected to the third semiconductor chip. One end of the third conductive connection may be in contact with the fourth rewiring pad. And the third rewiring pad may be electrically connected to the third semiconductor chip.

The upper wiring layer may include a first rewiring pattern and first and second rewiring pads connected to both ends of the first rewiring pattern. One end of the second conductive connection may be in contact with the first rewiring pad. And the second rewiring pad may be electrically connected to the third semiconductor chip. And one end of the third conductive connection may be in contact with the third semiconductor chip.

The power supply pads of the second semiconductor chips can be directly connected to the substrate without passing through the third semiconductor chip.

Some of the plurality of second semiconductor chips may be sequentially offset aligned in a first direction to form a first chip stack. Another portion of the plurality of second semiconductor chips may be sequentially offset aligned in a second direction different from the first direction on the first chip stack to form a second chip stack. An intermediate wiring layer may be formed on the first chip stack. And the second semiconductor chips included in the first chip stack may be electrically connected to the upper wiring layer via the intermediate wiring layer.

An intermediate adhesive film attached to the bottom surface of the second chip stack and in contact with the intermediate wiring layer may be provided. And a part of the second conductive connection may be connected to the intermediate wiring layer through the intermediate bonding film.

 The first semiconductor chip may include a buffer chip. Each of the second semiconductor chips may include a non-volatile memory chip having a greater width than the first semiconductor chip. The third semiconductor chip may include a logic chip having a narrower width than the second semiconductor chips.

The details of other embodiments are included in the detailed description and drawings.

According to embodiments of the inventive concept, a semiconductor package in which a plurality of memory chips and a logic chip are mounted on a substrate may be provided. A rewiring layer is formed on the uppermost memory chip among the memory chips. The memory chips may be connected to the logic chip via the rewiring layer by conductive connections such as bonding wires. The logic chip may be mounted close to the data pads of the memory chips. The data transfer path between the logic chip and the memory chips can be remarkably shortened as compared with the related art. The substrate does not require wiring for transferring data between the logic chip and the memory chips. The wiring inside the substrate formed in the substrate can be remarkably simplified compared with the conventional one.

In some embodiments, a semiconductor package on which a buffer chip, a support, an adhesive film, a plurality of memory chips, and a logic chip are mounted may be provided on a substrate. A rewiring layer is formed on the uppermost memory chip among the memory chips.

A signal transmission path is shortened, a semiconductor package which is structurally stable, and which is advantageous in light weight shortening while mounting a plurality of semiconductor chips can be realized.

1, 5, 7, 8, 10, 12, 15, 22a, and 23 are layouts for describing a semiconductor package according to example embodiments of the inventive concepts.
2A, 3, 6, 9, 11, 13, 14, 16 to 21, and 24 are cross-sectional views illustrating semiconductor packages according to example embodiments of the inventive concepts.
FIG. 2B is a partial sectional view showing a part of FIG. 2A in detail.
4 is a layout showing wiring in a substrate for explaining a semiconductor package according to embodiments of the present invention.
22B is a cross-sectional view showing a portion of FIG. 22A.
25 to 30 are perspective view and system block diagrams of an electronic device according to embodiments of the inventive concept.

Embodiments of the technical idea of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Also, when a layer is referred to as being "on" another layer or substrate, it may be formed directly on another layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout the specification.

The terms first, second, etc. may be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may be referred to as a first component.

Terms such as top, bottom, top, bottom, or top, bottom, etc. are used to distinguish relative positions in components. For example, in the case of naming the upper part of the drawing as upper part and the lower part as lower part in the drawings for convenience, the upper part may be named lower part and the lower part may be named upper part without departing from the scope of right of the present invention .

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning in the context of the relevant art and are to be construed as ideal or overly formal in meaning unless explicitly defined in the present application Do not.

2A and FIG. 3 are sectional views for explaining a semiconductor package according to embodiments of the technical idea of the present invention, and FIG. 2B is a sectional view for explaining a semiconductor package according to embodiments of the present invention. And Fig. 4 is a layout showing wiring in a substrate to explain a semiconductor package according to embodiments of the present invention.

Referring to FIGS. 1 and 2A, a first chip stack 10 may be mounted on a substrate 3. The first chip stack 10 may include a plurality of memory chips 11, 12, 13 and 14. A rewiring layer 274 may be formed on the uppermost memory chip 14 among the plurality of memory chips 11, 12, 13, A plurality of first rewiring patterns 275, a plurality of second rewiring patterns 276, a plurality of first rewiring pads 291, a plurality of second rewiring patterns 271, Pads 292, a plurality of third rewiring pads 293, a plurality of fourth rewiring pads 294, and a plurality of fifth rewiring pads 297 may be formed. The logic chip 7 may be mounted on the re-wiring layer 274. An encapsulant 59 may be provided on the substrate 3 to cover the first chip stack 10 and the logic chip 7. First to fifth conductive connections 241, 243, 246, 248, 249 may be provided in the encapsulant 59. The plurality of memory chips 11, 12, 13 and 14 and the logic chip 7 may include a plurality of data pads 91 and a plurality of power pads 92.

In another embodiment, the rewiring layer 274 may be referred to as an upper wiring layer.

Each of the first to fifth conductive connections 241, 243, 246, 248 and 249 may include a bonding wire, a beam lead, a conductive tape, a conductive spacer, a penetrating electrode, a solder ball, a solder bump, or a combination thereof. For example, the first to fifth conductive connections 241, 243, 246, 248, and 249 may be bonding wires.

The substrate 3 may include a rigid printed circuit board, a flexible printed circuit board, or a rigid-flexible printed circuit board. The lower surface of the substrate 3 may be covered with a lower solder resist 2 and the upper surface of the substrate 3 may be covered with an upper solder resist 4. [ First electrode fingers 231 and second electrode fingers 233 may be formed on the substrate 3. External terminals 5 penetrating the lower solder resist 2 may be formed under the substrate 3. The first electrode finger 231 may be electrically connected to a selected one of the external terminals 5 through the substrate 3. The external terminals 5 may be a solder ball, a solder bump, a pin grid array, a lead grid array, a conductive tab, Combinations thereof.

Each of the plurality of memory chips 11, 12, 13, and 14 may include a non-volatile memory device such as a NAND flash memory. The plurality of memory chips 11, 12, 13, and 14 may include the data pads 91. The data pads 91 of the plurality of memory chips 11, 12, 13 and 14 may be data input / output pads. The plurality of memory chips 11, 12, 13, and 14 may be stacked in a cascade structure. The plurality of memory chips 11, 12, 13, 14 may be offset by step by step. For example, the plurality of memory chips 11, 12, 13, 14 may be stepwise offset aligned in one direction of the substrate 3. Each of the plurality of memory chips (11, 12, 13, 14) may be wider than the logic chip (7).

The length of each of the first rewiring patterns 275 may be shorter than the length of each of the second rewiring patterns 276. The first rewiring pattern 275 and the second rewiring pattern 276 may be separated from each other. The first and second rewiring pads 291 and 292 that are in contact with both ends of the first rewiring pattern 275 may be formed. The third and fourth rewiring pads 293 and 294 contacting both ends of the second rewiring pattern 276 may be formed. The first rewiring pad 291 may be in contact with or electrically connected to the data pad 91 of the uppermost memory chip 14. Also, the first rewiring pad 291 may be electrically connected to the plurality of memory chips 11, 12, 13 via the second conductive connections 243. The second conductive connections 243 may be in contact with the data pads 91 of the memory chips 11, 12, 13 and the first rewiring pads 291.

In another embodiment, each of the memory chips 11, 12, 13, 14 may comprise a volatile memory device such as a dynamic random access memory (DRAM).

The logic chip 7 may be a controller or a microprocessor including a logic device. The logic chip 7 may be narrower than the plurality of memory chips 11, 12, 13, The logic chip 7 may be mounted on the reordering layer 274. The rewiring layer 274 may cover the top layer memory chip 14. The rewiring layer 274 may be interposed between the logic chip 7 and the uppermost layer memory chip 14. [ A selected one of the data pads 91 of the logic chip 7 may be connected to the second rewiring pad 292 via the fifth conductive connection 249. The other one of the data pads 91 of the logic chip 7 may be connected to the third rewiring pad 293 via the fourth conductive connection 248. The first conductive connection 241 may be formed between the fourth rewiring pad 294 and the first electrode finger 231.

The plurality of memory chips 11, 12, 13 and 14 may be formed of the first rewiring pads 291, the first rewiring patterns 275, the second rewiring pads 292, 5 conductive connections 249, the logic chip 7, the fourth conductive connections 248, the third rewiring pads 293, the second rewiring patterns 276, May be electrically connected to the substrate 3 sequentially through the redistribution pads 294 and the first conductive connections 241. [

The third conductive connections 246 are formed on the second electrode fingers 233, the power supply pads 92 of the memory chips 11, 12, 13 and the fifth rewiring pads 297, As shown in FIG. The fifth rewiring pads 297 may contact or be electrically connected to the power supply pad 92 of the uppermost memory chip 14 among the memory chips 11, 12, 13, The power supply pads 92 of the memory chips 11, 12, 13 and 14 are electrically connected to the second electrode fingers (not shown) via the third conductive connections 246 233, respectively.

Referring to FIG. 2B, the uppermost layer memory chip 14 may include the data pads 91 and the passivation insulating layer 14P. The passivation layer 14P may cover the top layer memory chip 14 and expose the data pads 91. [ The rewiring layer 274 is formed of a first insulating film 274A, the first rewiring pads 291, the first rewiring patterns 275, the second rewiring pads 292, 2 insulating film 274B. The first insulating film 274A may cover the uppermost layer memory chip 14. The first rewiring pads 291, the first rewiring patterns 275, and the second rewiring pads 292 may be formed on the first insulating film 274A. For example, the first rewiring pads 291, the first rewiring patterns 275, and the second rewiring pads 292 may be formed at the same level. The first rewiring pads 291, the first rewiring patterns 275, and the second rewiring pads 292 may not be overlapped with each other. The first rewiring pads 291 may be directly in contact with the data pads 91 of the uppermost memory chip 14 through the first insulating film 274A. The second insulation film 274B covers the first insulation film 274A and the first wiring patterns 275 and covers the first wiring pads 291 and the second wiring pads 292 ) Can be exposed. The second conductive connections 243 may be formed on the first rewiring pads 291. The fifth conductive connections 249 may be formed on the second rewiring pads 292. [

In some embodiments, the first rewiring pads 291, the first rewiring patterns 275, the second rewiring pads 292, the third rewiring pads 293, The second rewiring patterns 276, the fourth rewiring pads 294, and the fifth rewiring pads 297 may be formed at the same level so as not to overlap each other.

In another embodiment, the first insulating film 274A or the second insulating film 274B may be optionally omitted. For example, the first insulating film 274A may be omitted.

In another embodiment, the rewiring layer 274 may be partially formed on the top layer memory chip 14.

Referring to FIG. 3, the substrate 3, the first chip stack 10, the logic chip 7, and the encapsulant 59 may form a card-type package or a mainboard-mounted package . For example, the external terminals (5 in Fig. 2A) may be omitted.

Referring to FIG. 4, the substrate 3 may include intra-substrate interconnects 321, 322, and 323. Some of the in-substrate interconnects 321, 322 and 323 may be those for powering the memory chips 11, 12, 13, 14 and the logic chip 7. For example, some of the intra-substrate interconnects 321, 322, and 323 may be electrically connected to the second electrode fingers 233 and the third conductive interconnects 246. Some of the internal wiring lines 321, 322, and 323 may be ones for inputting / outputting data to / from the logic chip 7 and for transmitting signals to / from external devices. For example, some of the in-substrate interconnects 321, 322, and 323 may be electrically connected to the first electrode fingers 231 and the first conductive connections 241.

1 to 4, the logic chip 7 is located relatively close to the data pads 91 of the memory chips 11, 12, 13, 14 and the memory chips 11, 12, 13, and 14, respectively. The first wiring patterns 275, the first rewiring pads 291, the second rewiring pads 292, the second conductive connections 243, and the fifth conductive pads 292, The memory chip 249 may be interpreted as a first electrical connection path that serves to transfer a data signal between the logic chip 7 and the memory chips 11, 12, 13, The second wiring patterns 276, the third rewiring pads 293, the fourth rewiring pads 294, the fourth conductive connections 248, the first conductive connections 241 and the first electrode fingers 231 may be interpreted as a second electrical connection path for transferring a data signal between the logic chip 7 and the substrate 3. [ The first electrical connection path may be shorter than the second electrical connection path. The fifth rewiring pads 297, the third conductive connections 246 and the second electrode fingers 233 are connected to the memory chips 11, 12, 13, 14 from the substrate 3, And a third electrical connection path that serves to supply power to the first electrical connection path. The substrate wirings 321, 322, and 323 may be connected to the first electrode fingers 231 or the second electrode fingers 233.

As described above, according to the embodiments of the present invention, the substrate 3 is provided with a function of transferring a data signal between the logic chip 7 and the memory chips 11, 12, 13 and 14 No wiring is required. The wirings that can transfer data signals between the logic chip 7 and the memory chips 11, 12, 13 and 14 are all connected to the lowest memory chip 11 among the memory chips 11, 12, 13, (Not shown). The internal wiring lines 321, 322 and 323 formed in the substrate 3 can be remarkably simplified compared with the conventional ones. The power supply capability and signal transmission capability of the board internal wirings 321, 322, and 323 can be remarkably improved as compared with the prior art.

The logic chip 7 may be formed close to the data pads 91 of the memory chips 11, 12, 13, 14. The length of the electrical connection path between the data pads 91 of the memory chips 11, 12, 13, and 14 and the logic chip 7 can be significantly shortened as compared with the related art. The length of the first rewiring pattern 275 may be shorter than the length of the second rewiring pattern 276. The length of the electrical connection path between the data pads 91 of the memory chips 11, 12, 13 and 14 and the logic chip 7 is determined by the electrical length between the logic chip 7 and the substrate 3 It can be shortened shorter than the connection path. The operating speed of the memory chips 11, 12, 13, 14 may be relatively slow compared to the signal transfer speed between the logic chip 7 and the external device. The operating speed of the semiconductor package according to embodiments of the present invention may be determined by the memory chips 11, 12, 13, Shortening the electrical connection path between the logic chip 7 and the memory chips 11, 12, 13, 14 can be very effective in increasing the operating speed of the semiconductor package.

The length of the first rewiring pattern 275 and the second rewiring pattern 276 can be freely adjusted according to the position of the logic chip 7. The positions of the data pads 91 of the logic chip 7 can be efficiently arranged in connection with the first and second rewiring patterns 275 and 276. [ According to the embodiments of the present invention, the degree of freedom of design of the logic chip 7 can be significantly increased compared to the prior art. It may be relatively advantageous to highly integrate the logic chip 7.

FIG. 5 is a layout for explaining a semiconductor package according to embodiments of the present invention, and FIG. 6 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention.

Referring to FIGS. 5 and 6, a first chip stack 10 may be mounted on the substrate 3. The first chip stack 10 may include a plurality of memory chips 11, 12, 13 and 14. A rewiring layer 274 may be formed on the uppermost memory chip 14 among the plurality of memory chips 11, 12, 13, A plurality of second rewiring patterns 276, a plurality of first rewiring pads 291, a plurality of third rewiring pads 293, a plurality of fourth rewiring patterns 293, Pads 294, and a plurality of fifth rewiring pads 297 may be formed. The logic chip 7 may be mounted on the re-wiring layer 274. An encapsulant 59 may be provided on the substrate 3 to cover the first chip stack 10 and the logic chip 7. First to fifth conductive connections 241, 243, 246, 248, 249 may be provided in the encapsulant 59. The plurality of memory chips 11, 12, 13 and 14 and the logic chip 7 may include a plurality of data pads 91 and a plurality of power pads 92.

The first rewiring patterns (275 in FIG. 1) and the second rewiring pads (292 in FIG. 1) may be omitted. The fifth conductive connections 249 may contact the first rewiring pads 291 and the data pads 91 of the logic chip 7. The length of the electrical connection path between the memory chips 11, 12, 13, and 14 and the logic chip 7 can be significantly shortened as compared with the related art.

7 is a layout for explaining a semiconductor package according to embodiments of the technical idea of the present invention.

Referring to FIG. 7, a first chip stack 10 may be mounted on the substrate 3. The first chip stack 10 may include a plurality of memory chips 11, 12, 13 and 14. A rewiring layer 274 may be formed on the uppermost memory chip 14 among the memory chips 11, 12, 13, A plurality of first rewiring patterns 275, a plurality of second rewiring patterns 276, a plurality of first rewiring pads 291, a plurality of second rewiring patterns 271, Pads 292, a plurality of third rewiring pads 293, a plurality of fourth rewiring pads 294, and a plurality of fifth rewiring pads 297 may be formed. The logic chip 7 may be mounted on the re-wiring layer 274. First to fifth conductive connections 241, 243, 246, 248, 249 may be provided on the substrate 3. The plurality of memory chips 11, 12, 13 and 14 and the logic chip 7 may include a plurality of data pads 91 and a plurality of power pads 92.

The first rewiring patterns 275, the second rewiring patterns 276, the first rewiring pads 291, the second rewiring pads 292, The second rewiring pads 293, the fourth rewiring pads 294, and the fifth rewiring pads 297 may be formed to have various positions and lengths. The degree of design freedom of the logic chip 7 can be significantly increased compared to the conventional case. For example, the logic chip 7 may have a length ratio of the long axis to the short axis of 1.2 or less.

FIG. 8 is a layout for explaining a semiconductor package according to embodiments of the present invention, and FIG. 9 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention.

Referring to FIGS. 8 and 9, a first chip stack 10 may be mounted on the substrate 3. The first chip stack 10 may include a plurality of memory chips 11, 12, 13 and 14. A rewiring layer 274 may be formed on the uppermost memory chip 14 among the plurality of memory chips 11, 12, 13, A plurality of first rewiring patterns 275, a plurality of second rewiring patterns 276, a plurality of third rewiring patterns 277, a plurality of first rewiring lines 274, Pads 291, a plurality of second rewiring pads 292, a plurality of third rewiring pads 293, a plurality of fourth rewiring pads 294, a plurality of fifth rewiring pads 292, A plurality of second rewiring pads 297, and a plurality of sixth rewiring pads 298 may be formed. The logic chip 7 and the first buffer chip 261 may be mounted on the reordering layer 274. An encapsulant 59 covering the first chip stack 10, the logic chip 7, and the first buffer chip 261 may be provided on the substrate 3. The first conductive connections 241, the second conductive contacts 243, the third conductive contacts 246, the fourth conductive contacts 248, the fifth conductive contacts 249 , Sixth conductive contacts 244, and seventh conductive contacts 247 may be provided. The memory chips 11, 12, 13 and 14, the first buffer chip 261 and the logic chip 7 include a plurality of data pads 91 and a plurality of power pads 92 .

The first buffer chip 261 may be connected to the logic chip 7 using the seventh conductive connection 247. The third rewiring patterns 277 may be formed between the fifth rewiring pads 297 and the sixth rewiring pads 298. The sixth conductive connections 244 may be formed between the power supply pads 92 and the sixth rewiring pads 298 of the first buffer chip 261. The first buffer chip 261 may include a volatile memory device such as DRAM or SRAM.

FIG. 10 is a layout for explaining a semiconductor package according to embodiments of the present invention, and FIG. 11 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention.

Referring to FIGS. 10 and 11, a first chip stack 10 may be mounted on the substrate 3. The first chip stack 10 may include a plurality of memory chips 11, 12, 13 and 14. A rewiring layer 274 may be formed on the uppermost memory chip 14 among the memory chips 11, 12, 13, A plurality of second rewiring patterns 276, a plurality of third rewiring patterns 277, a plurality of first rewiring pads 291, a plurality of third rewiring patterns 271, Pads 293, a plurality of fourth rewiring pads 294, a plurality of fifth rewiring pads 297, and a plurality of sixth rewiring pads 298 may be formed. The logic chip 7 and the first buffer chip 261 may be mounted on the reordering layer 274. An encapsulant 59 covering the first chip stack 10, the logic chip 7, and the first buffer chip 261 may be provided on the substrate 3. The first conductive connections 241, the second conductive contacts 243, the third conductive contacts 246, the fourth conductive contacts 248, the fifth conductive contacts 249 , Sixth conductive contacts 244, and seventh conductive contacts 247 may be provided. The memory chips 11, 12, 13 and 14, the first buffer chip 261 and the logic chip 7 include a plurality of data pads 91 and a plurality of power pads 92 .

The first rewiring patterns (275 in FIG. 8) and the second rewiring pads (292 in FIG. 8) may be omitted. The fifth conductive connections 249 may contact the first rewiring pads 291 and the data pads 91 of the logic chip 7.

12 is a layout illustrating a semiconductor package according to embodiments of the inventive concept, and FIGS. 13 and 14 are cross-sectional views illustrating a semiconductor package according to embodiments of the inventive concept.

Referring to FIGS. 12 and 13, a first chip stack 10 may be mounted on the substrate 3. The first chip stack 10 may include a plurality of memory chips 11, 12, 13 and 14. A rewiring layer 274 may be formed on the uppermost memory chip 14 among the memory chips 11, 12, 13, A plurality of first rewiring patterns 275, a plurality of second rewiring patterns 276, a plurality of third rewiring patterns 277, a plurality of first rewiring lines 274, Pads 291, a plurality of second rewiring pads 292, a plurality of third rewiring pads 293, a plurality of fourth rewiring pads 294, a plurality of fifth rewiring pads 292, A plurality of second rewiring pads 297, and a plurality of sixth rewiring pads 298 may be formed. The logic chip 7, the first buffer chip 261, and the second buffer chip 262 may be mounted on the reordering layer 274. The second buffer chip 262 may be offset-aligned on the first buffer chip 261. An encapsulating material 59 covering the first chip stack 10, the logic chip 7, the first buffer chip 261 and the second buffer chip 262 is formed on the substrate 3 . The first conductive connections 241, the second conductive contacts 243, the third conductive contacts 246, the fourth conductive contacts 248, the fifth conductive contacts 249 , Sixth conductive contacts 244, and seventh conductive contacts 247 may be provided. The memory chips 11, 12, 13 and 14, the first buffer chip 261, the second buffer chip 262 and the logic chip 7 are connected to a plurality of data pads 91 and a plurality of Power supply pads 92 may be included.

The first buffer chip 261 and the second buffer chip 262 may be connected to the logic chip 7 using the seventh conductive connection 247. The third rewiring patterns 277 may be formed between the fifth rewiring pads 297 and the sixth rewiring pads 298. The sixth conductive connections 244 are formed between the power supply pads 92 and the sixth rewiring pads 298 of the first buffer chip 261 and the second buffer chip 262 . The first buffer chip 261 and the second buffer chip 262 may include a volatile memory device such as DRAM or SRAM.

Referring to FIG. 14, the second buffer chip 262 may be mounted on the first buffer chip 261 using a first adhesive layer 253. The first buffer chip 261 and the second buffer chip 262 may be connected to the logic chip 7 using the seventh conductive connections 247. The seventh conductive connections 247 may pass through the interior of the first adhesive film 253.

The first adhesive film 253 may be referred to as a direct adhesive film (DAF) or a film over wire (FOW). For example, if the seventh conductive connections 247 are a bonding wire, a portion of the bonding wire may partially penetrate or pass through the first adhesive layer 253 . The second buffer chip 262 may be vertically aligned on the first buffer chip 261 when the seventh conductive connections 247 pass through or pass through the first adhesive film 253.

15 is a layout for explaining a semiconductor package according to embodiments of the technical idea of the present invention.

Referring to FIG. 15, a first chip stack 10 may be mounted on a substrate 3. The first chip stack 10 may include a plurality of memory chips 11, 12, 13 and 14. A rewiring layer 274 may be formed on the uppermost memory chip 14 among the memory chips 11, 12, 13, A plurality of first rewiring patterns 275, a plurality of second rewiring patterns 276, a plurality of third rewiring patterns 277, a plurality of fourth rewiring patterns 277, Patterns 313, a plurality of first rewiring pads 291, a plurality of second rewiring pads 292, a plurality of third rewiring pads 293, a plurality of fourth rewiring pads 292, A plurality of fourth rewiring pads 294, a plurality of fifth rewiring pads 297, a plurality of sixth rewiring pads 298, a plurality of seventh rewiring pads 311, 314 may be formed. The logic chip 7, the first buffer chip 261, and the second buffer chip 262 may be mounted on the reordering layer 274. The second buffer chip 262 may be offset-aligned on the first buffer chip 261. An encapsulating material 59 covering the first chip stack 10, the logic chip 7, the first buffer chip 261 and the second buffer chip 262 is formed on the substrate 3 . The first conductive connections 241, the second conductive contacts 243, the third conductive contacts 246, the fourth conductive contacts 248, the fifth conductive contacts 249 , Sixth conductive connections 244, seventh conductive connections 247, and eighth conductive connections 312 may be provided.

The seventh rewiring pads 311 and the eighth rewiring pads 314 may be formed at both ends of the fourth rewiring patterns 313. [ The fourth rewiring patterns 313, the seventh rewiring pads 311 and the eighth rewiring pads 314 are disposed between the first buffer chip 261 and the logic chip 7 . The first buffer chip 261 and the second buffer chip 262 may be connected to the eighth rewiring pads 314 using the seventh conductive connection 247. [ The logic chip 7 may be connected to the seventh rewiring pads 311 using the eighth conductive connections 312.

16 to 21 are cross-sectional views illustrating a semiconductor package according to embodiments of the present invention.

Referring to FIGS. 16 and 17, buffer chips 261 and 262 and a support table 50 can be mounted on the substrate 3. A first chip stack 10 may be mounted on the buffer chips 261 and 262 and the support 50. The first chip stack 10 may include a plurality of memory chips 11, 12, 13 and 14. A rewiring layer 274 may be formed on the uppermost memory chip 14 among the plurality of memory chips 11, 12, 13, The first rewiring pattern 275, the second rewiring pattern 276 and the first to fourth rewiring pads 291, 292, 293 and 294 may be formed in the reordering layer 274 . The logic chip 7 may be mounted on the re-wiring layer 274. An encapsulant 59 may be formed on the substrate 3 to cover the buffer chips 261 and 262, the support 50, the first chip stack 10, and the logic chip 7 . The first conductive contacts 241, the second conductive contacts 243, the fourth conductive contacts 248, the fifth conductive contacts 249, the ninth conductive contacts 241, (242) may be formed. The buffer chips 261 and 262, the memory chips 11, 12, 13 and 14, and the logic chip 7 may include data pads 91. Each of the conductive connections 241, 242, 243, 248, and 249 may include a bonding wire, a beam lead, a conductive tape, a conductive spacer, a penetrating electrode, a solder ball, a solder bump, or a combination thereof.

The substrate 3 may include a rigid printed circuit board, a flexible printed circuit board, or a rigid-flexible printed circuit board. The lower surface of the substrate 3 may be covered with a lower solder resist 2 and the upper surface of the substrate 3 may be covered with an upper solder resist 4. [ A first electrode finger 231 and a third electrode finger 232 may be formed on the substrate 3. External terminals 5 penetrating the lower solder resist 2 may be formed under the substrate 3. The first electrode finger 231 may be electrically connected to a selected one of the external terminals 5 through the substrate 3. The external terminals 5 may be a solder ball, a solder bump, a pin grid array, a lead grid array, a conductive tab, Combinations thereof.

In another embodiment, the substrate 3, the buffer chips 261, 262, the support 50, the first chip stack 10, the logic chip 7, and the encapsulant 59 A card-shaped package can be constructed. The external terminals 5 may be omitted.

Each of the buffer chips 261 and 262 may include a volatile memory device such as DRAM or SRAM. The data pads 91 of the buffer chips 261 and 262 may be data input / output pads. The ninth conductive connections 242 may be formed between the data pads 91 and the third electrode fingers 232 of the buffer chips 261, 262.

The buffer chips 261 and 262 may be electrically connected to the logic chip 7 via the ninth conductive connections 242 and the substrate 3. The buffer chips 261 and 262 may include a first buffer chip 261 and a second buffer chip 262. The second buffer chip 262 may be mounted on the first buffer chip 261 using a first adhesive layer 253. The first adhesive film 253 may be referred to as a direct adhesive film (DAF) or a film over wire (FOW). The ninth conductive connections 242 may pass through the first adhesive layer 253. For example, if the ninth conductive connections 242 are a bonding wire, a portion of the bonding wire may partially penetrate or pass through the first adhesive layer 253 . The second buffer chip 262 may be vertically aligned on the first buffer chip 261 when the ninth conductive connections 242 pass through or pass through the first adhesive film 253. The upper surfaces of the support 50 and the second buffer chip 262 may be at substantially the same horizontal level.

Each of the memory chips 11, 12, 13, and 14 may include a non-volatile memory device such as a NAND flash memory. The data pads 91 of the memory chips 11, 12, 13 and 14 may be data input / output pads. The memory chips 11, 12, 13, 14 may be stacked in a cascade structure. The memory chips 11, 12, 13, 14 may be offset by step by step. Each of the memory chips 11, 12, 13, and 14 may be larger than the second buffer chip 262. The lowest memory chip 11 of the memory chips 11, 12, 13 and 14 may be attached on the support 50 and the second buffer chip 262 using a second adhesive film 254 . One side of the lowest memory chip 11 may be vertically aligned with one side of the support 50. The other side of the lowest memory chip 11 may be aligned on the second buffer chip 262. A third adhesive layer 255 may be formed between the memory chips 11, 12, 13, and 14. The memory chips 11, 12, 13, 14 may be offset aligned step by step in one direction of the substrate 3.

The thickness of the second adhesive film 254 may be thicker than the third adhesive film 255. The ninth conductive connections 242 may pass through the interior of the second adhesive layer 254. For example, if the ninth conductive connections 242 are a bonding wire, a portion of the bonding wire may partially penetrate or pass through the second adhesive layer 254 . The second buffer chip 262 and the supporter 50 are formed in such a manner that the area occupied by the lowest memory chip 11 is smaller than the occupied area of the lowest memory chip 11 when the ninth conductive interconnections 242 penetrate or pass through the second adhesive film 254. [ Lt; / RTI >

The second adhesive film 254 may have the same width as the lowest memory chip 11. The second adhesive film 254 may be attached to the lower surface of the lowest memory chip 11. The second adhesive layer 254 may be in direct contact with the lowest memory chip 11, the second buffer chip 262 and the support 50. The second adhesive layer 254 may be a direct adhesive film (DAF) or a film over wire (FOW). The third adhesive layer 255 may be a material layer of the same kind as the second adhesive layer 254. In some other embodiments, the third adhesive film 255 may be a material film different from the second adhesive film 254.

The first rewiring pattern 275 and the second rewiring pattern 276 may be separated from each other. The first and second rewiring pads 291 and 292 that are in contact with both ends of the first rewiring pattern 275 may be formed. The third and fourth rewiring pads 293 and 294 contacting both ends of the second rewiring pattern 276 may be formed. The first rewiring pad 291 may be in contact with or electrically connected to the data pad 91 of the uppermost memory chip 14. Also, the first rewiring pad 291 may be electrically connected to the plurality of memory chips 11, 12, 13 via the second conductive connections 243. The third conductive connections 243 may be in contact with the data pads 91 of the memory chips 11, 12, 13 and the first rewiring pads 291.

The logic chip 7 may be a controller or a microprocessor. The logic chip 7 may be narrower than the memory chips 11, 12, 13. The logic chip 7 may be mounted on the reordering layer 274. A selected one of the data pads 91 of the logic chip 7 may be connected to the second rewiring pad 292 via the fifth conductive connection 249. The other one of the data pads 91 of the logic chip 7 may be connected to the third rewiring pad 293 via the fourth conductive connection 248. The first conductive connection 241 may be formed between the fourth rewiring pad 294 and the first electrode finger 231.

The memory chips 11, 12 and 13 are electrically connected to the data pads 91, the second conductive connections 243, the first rewiring pads 291, the first rewiring patterns 275, The second rewiring pad 292, the fifth conductive connection 249, the logic chip 7, the fourth conductive connection 248, the third rewiring pad 293, The fourth wiring line 294, and the first conductive connection 241 in this order from the side of the substrate 3, as shown in FIG.

16 and 17, the lengths of the first rewiring pattern 275 and the second rewiring pattern 276 can be freely adjusted according to the position of the logic chip 7, as shown in FIGS. For example, when shortening the signal transmission path between the logic chip 7 and the memory chips 11, 12, and 13, the length of the first rewiring pattern 275 may be shorter than the length of the first rewiring pattern 275, It can be shortened to be shorter than the second rewiring pattern 276. The length of the electrical connection path between the data pads 91 of the memory chips 11, 12, 13 and the logic chip 7 can be significantly shortened compared with the conventional case. The length of the electrical connection path between the data pads 91 and the logic chip 7 of the memory chips 11, 12 and 13 is determined by the electrical connection path between the logic chip 7 and the substrate 3 Can be shortened.

The second buffer chip 262 may be vertically aligned on the first buffer chip 261 using a configuration in which the ninth conductive connections 242 pass through the first adhesive film 253. The second buffer chip 262 and the supporter 50 are connected to each other via the second adhesive film 254 so that the ninth conductive connection 242 passes through the second adhesive film 254, It can be mounted within the occupied area. According to the embodiments of the present invention, a semiconductor package having a configuration advantageous to horizontal width reduction can be provided. It is possible to realize a semiconductor package having a remarkably high operation speed and advantageous in size reduction by mounting a plurality of semiconductor chips.

Referring to FIG. 18, a rewiring layer 274 may be formed on the uppermost memory chip 14 among the memory chips 11, 12, 13, and 14. The first and second rewiring patterns 271 and 276 are formed on both sides of the rewiring layer 274 and the first and second rewiring patterns 291 and 276, 293, and 294 may be formed. The logic chip 7 may be mounted on the re-wiring layer 274. A selected one of the data pads 91 of the logic chip 7 may be connected to the first rewiring pad 291 via a fifth conductive connection 249. The other selected one of the data pads 91 of the logic chip 7 may be connected to the third rewiring pad 293 via a fourth conductive connection 248. The first rewiring pattern (275 in FIG. 16) and the second rewiring pad (292 in FIG. 16) may be omitted.

The logic chip 7 may be mounted close to the data pad 91 of the first rewiring pad 291 and the memory chips 11, 12, 13, The electrical connection path between the logic chip 7 and the memory chips 11, 12, 13, 14 can be remarkably shortened compared to the prior art.

Referring to FIG. 19, the second buffer chip (262 in FIG. 16) may be omitted. The upper surfaces of the support 50 and the first buffer chip 261 may be at substantially the same horizontal level. The lowermost memory chip 11 of the memory chips 11, 12, 13 and 14 may be attached on the support 50 and the first buffer chip 261 using a second adhesive film 254. One side of the lowest memory chip 11 may be aligned on the first buffer chip 261. The ninth conductive connections 242 may pass through the interior of the second adhesive film 254. The first buffer chip 261 and the support 50 may be mounted within the occupied area of the lowest memory chip 11.

Referring to FIG. 20, a chip stack 9 may be mounted on the buffer chips 261 and 262 and the support table 50. The chip stack 9 may include a plurality of memory chips 11, 12, 13, 14, 21, 22, 23, 24. For convenience, the plurality of memory chips 11, 12, 13, 14, 21, 22, 23, 24 are referred to as first to eighth memory chips 11, 12, 13, 14, 21, 22, . The first to fourth memory chips 11, 12, 13 and 14 may constitute a first chip stack 10 and the fifth to eighth memory chips 21, 22, 23, Chip stack 20 can be constructed. A re-wiring layer 274 may be formed on the eighth memory chip 24.

An intermediate rewiring layer 284 may be formed on the fourth memory chip 14. The intermediate rewiring layer 284 includes a fifth rewiring pattern 285 and a ninth rewiring pad 295 and a tenth rewiring pad 296 formed at both ends of the fifth rewiring pattern 285. [ . ≪ / RTI > The first to fourth memory chips 11, 12, 13, and 14 may be stacked in a first cascade structure. The second conductive connections 243 may be in contact with the tenth rewiring pads 296.

The fifth to eighth memory chips 21, 22, 23, 24 may be stacked in a second cascade structure. The fifth to eighth memory chips 21, 22, 23, and 24 may be aligned in different directions from the first to fourth memory chips 11, 12, 13, and 14. The fifth to eighth memory chips 21, 22, 23, and 24 may be sequentially offset aligned in the direction opposite to the first to fourth memory chips 11, 12, 13, and 14. For example, the fifth memory chip 21 may be attached on the intermediate rewiring layer 284 using a fourth adhesive layer 256. The fourth adhesive layer 256 may be substantially the same as the second adhesive layer 254. The second conductive connections 243 may pass through the interior of the fourth adhesive layer 256.

The sixth to eighth memory chips 22, 23 and 24 may be sequentially attached on the fifth memory chip 21 using a fifth adhesive film 257. [ The fifth to seventh memory chips 21, 22, and 23 may be connected to the fourth rewiring pad 294 using tenth conductive connections 245. The data pad 91 of the eighth memory chip 24 may be in contact with or electrically connected to the fourth rewiring pad 294. One end of the tenth conductive connections 245 may be in contact with the ninth rewiring pad 295.

Referring to FIG. 21, a rewiring layer 274 may be formed on the uppermost memory chip 14 among the memory chips 11, 12, 13, and 14. The first rewiring pattern 275 and the first and second rewiring pads 291 and 292 may be formed at both ends of the rewiring layer 274 and the first rewiring pattern 275 . The logic chip 7 may be mounted on the re-wiring layer 274. A selected one of the data pads 91 of the logic chip 7 may be connected to the second rewiring pad 292 via a fifth conductive connection 249. The other selected one of the data pads 91 of the logic chip 7 may be connected to the first electrode finger 231 via the first conductive connection 241. The second rewiring pattern (276 in Fig. 17) and the third and fourth rewiring pads (293, 294 in Fig. 16) may be omitted.

FIG. 22A is a layout for explaining a semiconductor package according to embodiments of the present invention, and FIG. 22B is a sectional view showing a portion of FIG. 22A.

Referring to FIG. 22A, a first chip stack 10 may be mounted on a substrate 3. The first chip stack 10 may include a plurality of memory chips 11, 12, 13 and 14. A rewiring layer 274 may be formed on the uppermost memory chip 14 among the memory chips 11, 12, 13, The plurality of first redistribution patterns 275, the plurality of second redistribution patterns 276, the plurality of first redistribution pads 291, and the plurality of second redistribution lines in the redistribution layer 274. Pads 292, a plurality of third redistribution pads 293, a plurality of fourth redistribution pads 294, a plurality of fifth redistribution pads 297, a plurality of sixth redistribution patterns 376, a plurality of seventh redistribution patterns 377, a plurality of eleventh redistribution pads 393, a plurality of twelfth redistribution pads 394, and a plurality of thirteenth redistribution pads 395 , And a plurality of fourteenth redistribution pads 396 may be formed. The logic chip 7 may be mounted on the re-wiring layer 274. First to fifth conductive connections 241, 243, 246, 248, 249 and eleventh to thirteenth conductive connections 341, 347, 348 may be provided on the substrate 3. The plurality of memory chips 11, 12, 13 and 14 and the logic chip 7 may include a plurality of data pads 91 and a plurality of power pads 92.

The thirteenth conductive connections 348 may be connected between the logic chip 7 and the eleventh rewiring pads 393. The seventh rewiring patterns 377 may be formed between the eleventh rewiring pads 393 and the fourteenth rewiring pads 396. [ The twelfth conductive connections 347 may be connected between the fourteenth rewiring pads 396 and the thirteenth rewiring pads 395. The sixth rewiring patterns 376 may be formed between the thirteenth rewiring pads 395 and the twelfth rewiring pads 394. The eleventh conductive connections 341 may be connected between the twelfth rewiring pads 394 and the fourth electrode finger 331.

The twelfth conductive connections 347 may include a bonding wire, a beam lead, or a conductive tape. For example, the twelfth conductive contacts 347 may be a bonding wire such as a gold wire or an aluminum wire. The second rewiring patterns 276 may be disposed between the 14th rewiring pads 396 and the 13th rewiring pads 395. [ The twelfth conductive connections 347 may traverse the second wiring patterns 276. The twelfth conductive connections 347 may be separated from the second wiring patterns 276.

In another embodiment, a portion of the first rewiring patterns 275 and the second rewiring patterns 276 between the 14th rewiring pads 396 and the 13th rewiring pads 395 At least one can be placed.

Referring to FIG. 22B, the uppermost-level memory chip 14 may include a passivation insulating film 14P. The passivation insulating layer 14P may cover the uppermost layer memory chip 14. The rewiring layer 274 may be formed of the first insulating film 274A, the thirteenth rewiring pads 395, the second rewiring patterns 276, the fourteenth rewiring pads 396, 2 insulating film 274B. The first insulating film 274A may cover the uppermost layer memory chip 14. The thirteenth rewiring pads 395, the second rewiring patterns 276, and the fourteenth rewiring pads 396 may be formed on the first insulating film 274A. For example, the thirteenth rewiring pads 395, the second rewiring patterns 276, and the fourteenth rewiring pads 396 may be formed at the same level. The thirteenth redistribution pads 395, the second redistribution patterns 276, and the fourteenth redistribution pads 396 may be formed so as not to overlap each other.

The second insulating film 274B covers the first insulating film 274A and the second rewiring patterns 276 and covers the thirteenth rewiring pads 395 and the fourteenth rewiring pads 396 ) Can be exposed. The twelfth conductive connections 347 may be formed between the thirteenth rewiring pads 395 and the fourteenth rewiring pads 396. The twelfth conductive connections 347 may be separated from the second wiring patterns 276. The twelfth conductive connections 347 may be in direct contact with the thirteenth rewiring pads 395 and the fourteenth rewiring pads 396.

FIG. 23 is a layout for explaining a semiconductor package according to embodiments of the present invention, and FIG. 24 is a cross-sectional view for explaining a semiconductor package according to embodiments of the present invention.

Referring to FIG. 23 and FIG. 24, a first chip stack 10 may be mounted on the substrate 3. The first chip stack 10 may include a plurality of memory chips 11, 12, 13 and 14. A rewiring layer 274P may be formed on the uppermost memory chip 14 among the plurality of memory chips 11, 12, 13, The reordering layer 274P may partly cover the uppermost layer memory chip 14.

A plurality of second rewiring patterns 276, a plurality of third rewiring pads 293, a plurality of fourth rewiring pads 294, and a plurality of fifth rewiring patterns 274 are formed in the rewiring layer 274P, Line pads 297 may be formed. The logic chip 7 may be mounted on the uppermost memory chip 14. An encapsulant 59 may be provided on the substrate 3 to cover the first chip stack 10 and the logic chip 7. First to fifth conductive connections 241, 243, 246, 248, 249 may be provided in the encapsulant 59. The plurality of memory chips 11, 12, 13 and 14 and the logic chip 7 may include a plurality of data pads 91 and a plurality of power pads 92.

The rewiring layer 274P may be absent between the logic chip 7 and the uppermost layer memory chip 14. [ For example, the reordering layer 274P may be partially formed on the top layer memory chip 14 so as not to overlap with the logic chip 7. The first rewiring pads (291 in FIG. 5) may be omitted. The fifth conductive connections 249 may contact the data pads 91 of the top layer memory chip 14 and the data pads 91 of the logic chip 7. The length of the electrical connection path between the memory chips 11, 12, 13, and 14 and the logic chip 7 can be significantly shortened as compared with the related art.

FIG. 25 is a perspective view of an electronic device according to embodiments of the inventive concept, and FIG. 26 is a system block diagram of the electronic device according to the embodiments of the inventive concept. The electronic device may be a data storage device such as a solid state drive (SSD) 1100.

25 and 26, the solid state drive (SSD) 1100 may include an interface 1113, a controller 1115, a non-volatile memory 1118, and a buffer memory. 1119). The solid state drive 1100 is a device that stores information using a semiconductor device. The solid state drive 1100 is faster than a hard disk drive (HDD) and has advantages such as mechanical delay, failure rate, heat generation, noise reduction, miniaturization, and weight reduction. The solid state drive 1100 may be used in a laptop, a notebook PC, a desktop PC, an MP3 player, or a portable storage device.

The controller 1115 may be formed adjacent to the interface 1113 and electrically connected thereto. The controller 1115 may be a microprocessor including a memory controller and a buffer controller. The non-volatile memory 1118 may be formed adjacent to the controller 1115 and electrically connected thereto. The data storage capacity of the solid state drive 1100 may correspond to the non-volatile memory 1118. The buffer memory 1119 may be formed adjacent to the controller 1115 and electrically connected thereto.

The interface 1113 may be connected to a host 1002 and may transmit and receive electrical signals such as data. For example, the interface 1113 may be a device using standards such as SATA, IDE, SCSI, and / or a combination thereof. The non-volatile memory 1118 may be connected to the interface 1113 via the controller 1115. The non-volatile memory 1118 may store data received via the interface 1113. The data stored in the non-volatile memory 1118 is preserved even if the power supply to the solid state drive 1100 is interrupted.

The buffer memory 1119 may include a volatile memory. The volatile memory may be a dynamic random access memory (DRAM), and / or a static random access memory (SRAM). The buffer memory 1119 exhibits a relatively fast operation speed as compared with the non-volatile memory 1118.

The data processing speed of the interface 1113 may be relatively fast as compared with the operation speed of the nonvolatile memory 1118. Here, the buffer memory 1119 may serve to temporarily store data. The data received via the interface 1113 is temporarily stored in the buffer memory 1119 via the controller 1115 and then transmitted to the non-volatile memory 1118 in accordance with the data writing speed of the non- - volatile memory 1118. < RTI ID = 0.0 > In addition, frequently used data among the data stored in the non-volatile memory 1118 may be pre-read and temporarily stored in the buffer memory 1119. That is, the buffer memory 1119 can increase the effective operation speed of the solid state drive 1100 and reduce the error occurrence rate.

The non-volatile memory 1118, the buffer memory 1119, and the controller 1115 may have a configuration similar to that described with reference to FIGS. 1 to 24. For example, the non-volatile memory 1118, the buffer memory 1119, and the controller 1115 may be mounted in one semiconductor package. In another embodiment, the non-volatile memory 1118 and the controller 1115 may be mounted in a first semiconductor package, and the buffer memory 1119 may be mounted in a second semiconductor package. In another embodiment, the non-volatile memory 1118 is mounted in a first semiconductor package, the buffer memory 1119 is mounted in a second semiconductor package, and the controller 1115 is a third And can be mounted in a semiconductor package. The electrical characteristics of the solid state drive 1100 can be remarkably improved as compared with the conventional art.

27 to 29 are perspective views of electronic devices according to embodiments of the inventive concept, and FIG. 30 is a system block diagram of the electronic devices according to embodiments of the inventive concept.

27 to 29, the semiconductor package described with reference to FIGS. 1 to 24 may include an embedded multi-media chip (eMMC) 1200, a micro SD 1300, a mobile phone 1900, a netbook, a notebook, or a tablet. It can be usefully applied to electronic systems such as a PC. For example, a semiconductor package similar to that described with reference to FIGS. 1 to 24 may be mounted on a main board in the mobile phone 1900. A semiconductor package similar to that described with reference to FIGS. 1 to 24 may be provided as an expansion device such as the micro SD 1300 and may be used in combination with the mobile phone 1900.

Referring to FIG. 30, a semiconductor package similar to that described with reference to FIGS. 1 through 24 may be applied to the electronic system 2100. The electronic system 2100 includes a body 2110, a microprocessor unit 2120, a power unit 2130, a function unit 2140, and a display controller Unit 2150). The body 2110 may be a mother board formed of a printed circuit board (PCB). The microprocessor unit 2120, the power unit 2130, the functional unit 2140 and the display controller unit 2150 may be mounted on the body 2110. A display unit 2160 may be disposed inside the body 2110 or outside the body 2110. For example, the display unit 2160 may be disposed on a surface of the body 2110 to display an image processed by the display controller unit 2150.

The power unit 2130 receives a predetermined voltage from an external battery (not shown) or the like, branches the voltage to a required voltage level, and supplies the voltage to the microprocessor unit 2120, the functional unit 2140, the display controller unit 2150 ) And the like. The microprocessor unit 2120 can receive the voltage from the power unit 2130 and control the functional unit 2140 and the display unit 2160. The functional unit 2140 may perform the functions of various electronic systems 2100. For example, if the electronic system 2100 is a cellular phone, the functional unit 2140 can be connected to the display unit 2160 by dialing or by communicating with an external device 2170 to output video to the display unit 2160, Output, and the like, and can function as a camera image processor when the camera is mounted together.

In an application embodiment, if the electronic system 2100 is connected to a memory card or the like for capacity expansion, the functional unit 2140 may be a memory card controller. The functional unit 2140 can exchange signals with the external device 2170 through a wired or wireless communication unit 2180. When the electronic system 2100 requires a universal serial bus (USB) or the like for function expansion, the functional unit 2140 may serve as an interface controller. The functional unit 2140 may include a mass storage device.

A semiconductor package similar to that described with reference to FIGS. 1 through 24 may be applied to the functional unit 2140 or the microprocessor unit 2120. For example, the functional unit 2140 may be coupled to the substrate 3, the buffer chips 261, 262, the memory chips 11,12, 13,14, the re-routing layer 274, Chip 7 as shown in FIG. The substrate 3 may be electrically connected to the body 2110. The electronic system 2100 is advantageous in that it is thin and lightweight while mounting a plurality of semiconductor chips, and can exhibit high-speed operation characteristics due to shortening of a signal transmission path.

While the embodiments of the present invention have been schematically described with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. I can understand that you can. Therefore, it is to be understood that the embodiments described above are exemplary in all respects and not restrictive.

2, 4: solder resist 3: substrate
5: External terminal 7: Logic chip
9: chip stack 10, 20: first and second chip stacks
11, 12, 13, 14, 21, 22, 23, 24: memory chip
14P: passivation insulation film
50: support 59: encapsulant
91: data pad 92: power pad
231, 232, 233, and 331: electrode fingers
241, 242, 243, 244, 245, 246, 247, 248, 249, 312, 341, 347, 348: conductive connection
253, 254, 255, 256, 257: adhesive film
261, 262: buffer chip
274, 274P, 284: rewiring layer
275, 276, 277, 285, 313, 376, 377: Rewiring pattern
274A: first insulating film 274B: second insulating film
291, 292, 293, 294, 295, 296, 297, 298, 311, 314, 393, 394, 395, 396: redistribution pad
321, 322, 323: substrate wiring
1002: Host 1100: Solid State Disk (SSD)
1113: interface 1115: controller
1118: Non-volatile memory < RTI ID = 0.0 >
1119: Buffer memory
1200: embedded multi-media chip (eMMC)
1300: micro SD 1900: Mobile phone
2100: Electronic system
2110: body 2120: microprocessor unit
2130: Power unit 2140: Function unit
2150: Display controller unit
2160: Display unit
2170: External device 2180: Communication unit

Claims (10)

A plurality of first semiconductor chips mounted on a substrate and having data pads and power supply pads;
An upper wiring layer formed on the uppermost first semiconductor chip of the first semiconductor chips and having a plurality of redistribution patterns and a plurality of redistribution pads;
A second semiconductor chip formed on the uppermost first semiconductor chip and close to the data pads;
First conductive contacts formed between the data pads and the second semiconductor chip; And
And second conductive connections formed between the second semiconductor chip and the substrate,
The redistribution patterns are arranged at the same level and do not overlap each other,
Wherein the data pads of the first semiconductor chips are electrically connected to the substrate via the first conductive connections, the second semiconductor chip, the rewiring patterns, the rewiring pads, and the second conductive connections. ≪ / RTI > The method according to claim 1,
One of the redistribution pads is in direct contact with one of the data pads of the uppermost first semiconductor chip. The method according to claim 1,
And the second semiconductor chip is relatively close to the data pads and relatively far from the power pads. The method according to claim 1,
And a first electrical connection path between the first semiconductor chips and the second semiconductor chip is shorter than a second electrical connection path between the second semiconductor chip and the substrate. 5. The method of claim 4,
The upper wiring layer is
First redistribution patterns formed between the data pads of the first semiconductor chips and the second semiconductor chip; And
Second rewiring patterns formed between the second semiconductor chip and the substrate;
The first redistribution patterns are shorter than the second redistribution patterns,
The data pads of the first semiconductor chips sequentially pass through the first conductive connections, the first redistribution patterns, the second semiconductor chip, the second redistribution patterns, and the second conductive connections. A semiconductor package connected to the substrate. 5. The method of claim 4,
The upper wiring layer is
First redistribution pads formed between the data pads of the first semiconductor chips and the second semiconductor chip;
Redistribution patterns formed between the second semiconductor chip and the substrate; And
Second and third redistribution pads formed at both ends of the redistribution patterns,
The second semiconductor chip is close to the first redistribution pads,
The second conductive connections are connected to the third redistribution pads,
The data pads of the first semiconductor chips may include the first redistribution pads, the second semiconductor chip, the second redistribution pads, the redistribution patterns, the third redistribution pads, and the second redistribution pads. A semiconductor package connected to the substrate via conductive connections in sequence. The method according to claim 1,
Further comprising a third conductive connection formed between the redistribution pad,
The third conductive connection crosses an upper portion of at least one of the redistribution patterns,
The third conductive connection is separated from the redistribution patterns,
And the third conductive connection has a bonding wire, a beam lead, or a conductive tape. The method according to claim 1,
And the upper wiring layer partially covers the uppermost first semiconductor chip, and wherein the upper wiring layer does not have the upper wiring layer between the uppermost first semiconductor chip and the second semiconductor chip. The method according to claim 1,
And the data pads of the first semiconductor chips are all electrically connected to the substrate via the second semiconductor chip, the redistribution pads, the redistribution patterns, and the second conductive connections in sequence. A plurality of first semiconductor chips mounted on a substrate and having data pads and power supply pads;
A first redistribution pattern formed on the uppermost first semiconductor chip of the first semiconductor chips and between a plurality of first and second redistribution pads, the first redistribution pads, and the second redistribution pads A plurality of third and fourth redistribution pads, second redistribution patterns between the third and fourth redistribution pads, a plurality of fifth and sixth redistribution pads, Third redistribution patterns between the fifth and sixth redistribution pads, a plurality of seventh and eighth redistribution pads, and the seventh redistribution pads and the eighth redistribution pad An upper wiring layer having fourth redistribution patterns between pads, wherein the first redistribution pads are in contact with the data pads of the uppermost first semiconductor chip;
A second semiconductor chip on the upper wiring layer;
First conductive connections between the first redistribution pads and the data pads;
Second conductive connections between the second redistribution pads and the second semiconductor chip;
Third conductive connections between the second semiconductor chip and the third redistribution pads;
Fourth conductive connections between the fourth redistribution pads and the substrate;
Fifth conductive connections between the second semiconductor chip and the fifth redistribution pads;
Sixth conductive connections between the sixth redistribution pads and the seventh redistribution pads; And
A seventh conductive connection between the eighth redistribution pads and the substrate,
The sixth conductive connections have a bonding wire, a beam lead, or a conductive tape,
At least one of the first redistribution patterns and the second redistribution patterns is disposed between the sixth redistribution pads and the seventh redistribution pads, wherein the sixth conductive connections are connected to the first redistribution line. The semiconductor package away from the patterns and the second redistribution patterns.

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