KR20130025010A - Manufacturing method for flexible memory device and flexible memory device manufactured by the same - Google Patents

Abstract

PURPOSE: A method for manufacturing a flexible memory device and the flexible memory device manufactured by the same are provided to implement a memory array on a flexible substrate by one switching device and one memory structure. CONSTITUTION: A polycrystalline or signal crystalline silicon switching device with high performance is formed on a flexible substrate. A memory device including the switching device is manufactured. The silicon switching device is transferred after the silicon switching device is manufactured on the silicon substrate. The silicon switching device is crystallized from amorphous silicon to polycrystalline or single crystalline silicon on the flexible substrate.

Description

Flexible memory device manufacturing method and a flexible memory device manufactured thereby TECHNICAL FIELD [Manufacturing method for flexible memory device and flexible memory device manufactured by the same}

The present invention relates to a method for manufacturing a flexible memory device and a flexible memory device manufactured by the present invention, and more particularly, to manufacture a flexible memory device that can manufacture various memory devices in a flexible form by using a high-performance silicon device for switching. A method and a flexible memory device manufactured thereby.

Flexible electronics systems are receiving much attention compared to general bulk silicon technology because of their excellent mobility, uniform contact with curved surfaces, light weight, and user-friendly interface. However, such a flexible electronic device technology is limited to a few devices, and still needs to study a device based on the flexible system. In particular, all-in-one technology that integrates the unique functions of devices into one platform is required, and in order to implement such an all-in-one flexible system, the manufacture of flexible memory used for data processing and storage is the most important. Do.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method and a structure capable of implementing a memory device such as an RRAM PRAM DRAM on a flexible substrate.

According to the present invention, by utilizing a high-performance silicon device for switching, it is possible to manufacture a variety of memory devices of a flexible form. In particular, according to the present invention, a memory array can be implemented on a flexible substrate through one switching element and one memory structure. Furthermore, in the case of RRAM, PRAM, and DRAM, a high performance flexible silicon transistor is an amorphous TiO ₂ (α−). Integrated with TiO ₂ ) dipole resistance memory, GST phase change memory, ZrO ₂ capacitor memory elements, etc., the logic state of the memory can be controlled.

1 is a step-by-step view illustrating a method of manufacturing an 8 x 8 matrix 1T-1R flexible RRAM on a plastic substrate according to an embodiment of the present invention.
FIG. 2A is a schematic diagram illustrating an 8 × 8 matrix 1T-1R flexible RRAM structure on a plastic substrate. FIG.
2B is an enlarged optical image of the 1T-1R array.
2C is a BFTEM image of a flexible device formed on a plastic substrate in accordance with the present invention.
2D shows an enlarged view of a flexible 1T-1R RRAM device according to the present invention.
2E is a photograph showing that the flexible RRAM according to the present invention on a curved surface can provide a uniform contact area.
3A is a schematic structure of an RRAM single cell composed of two electronic elements.
3B is a graph showing the output performance of the NMOSFET.
3C is a graph showing a typical drain current-voltage curve I _D - V _D of a flexible RRAM device according to the present invention.
FIG. 3D is a graph showing the drain current-gate voltage I _D - V _G curve of the 1T-1R flexible RRAM device according to the present invention at a leading voltage of -0.5 V in LRS and HRS.
3E shows the endurance cycling test results at 0.5 v reading voltages obtained by repeated on / off sweeping operations.
As shown in FIG. 3F, the evaluation result of the data storage capability is shown.
4A and 4B show a 1T-1C ZrO2 capacitor DRAM and a 1D-1R GST phase change memory using single crystal silicon transferred from a silicon substrate and a polycrystalline silicon high performance switching element crystallized from a plastic substrate.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the drawings. The following embodiments are provided as examples to ensure that the spirit of the present invention can be fully conveyed to those skilled in the art. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, etc. of the components may be exaggerated for convenience. Like numbers refer to like elements throughout.

The present invention provides a method of manufacturing a flexible memory device, which first transfers a switching device such as a diode or a transistor from a silicon substrate to a flexible substrate, or deposits amorphous silicon on the flexible substrate, and then converts the high performance silicon device to the flexible substrate through laser crystallization. Implement When manufacturing a flexible PRAM, DRAM, and RRAM memory in a matrix form that fully overcomes obstacles caused by interference between adjacent cells and fully function as a memory device, a high performance switch element is still required to drive the memory element. Fully operating memory devices have not been implemented due to the limitations of flexible substrates and device technology. In the present invention, to implement this through the transfer of a high-performance single crystal silicon device to a plastic substrate and crystallization of amorphous silicon.

In an embodiment of the present invention, a silicon device manufacturing process requiring a high temperature process is performed on a bulk SOI sacrificial substrate, and then the switching device is transferred to a flexible plastic substrate. The transfer may first vertically etch the sacrificial substrate surrounding the switching element region, and then perform anisotropic etching again, and then transfer the switching element separated from the lower sacrificial substrate to the flexible substrate through a transfer substrate such as PDMS. Proceeds to step. Thereafter, a component (on-off element) capable of turning the switching element on and off is further formed with respect to the transferred switching element. In an embodiment of the present invention, the memory element may be an RRAM, a DRAM, or a PRAM. In this case, each on-off element may be a resistive memory in the case of RRAM, a capacitor in the case of DRAM, and a phase change memory in the case of PRAM. In addition, when the switching device is a transistor having a source-gate-drain region, the on-off element may be stacked in the drain region, wherein the transistor is manufactured on a sacrificial substrate, and then etched and stripped (membrane) to be. Therefore, the flexible memory device manufactured according to the present invention further includes an on-off element which is manufactured on a sacrificial substrate and then transferred to the flexible substrate, and which turns the switching element on and off after the transfer.

In another embodiment of the present invention, a method of fabricating a flexible memory switching device includes depositing amorphous silicon on a flexible substrate and then crystallizing the amorphous silicon into polycrystalline or single crystal silicon using excimer laser crystallization to implement a high performance silicon device on the flexible substrate. .

Hereinafter, a method of manufacturing a memory device using RRAM will be described. However, the scope of the present invention is not limited by the following examples, and DRAM or PRAM also fall within the scope of the present invention.

One embodiment of the present invention provides a flexible RRAM device for implementing a NOR type array of one transistor and one resistor (1T-1R) structure on a flexible substrate. That is, a high efficiency flexible single crystal silicon transistor is integrated in an amorphous TiO ₂ (α-TiO ₂ ) based dipole resistive memory element, controlling the logic state of the memory. The 1T-1R RRAM unit cells are connected to each other through word, bit, and source lines of an 8 x 8 NOR type array to independently control each unit memory cell. The flexibility of the device according to the invention has been tested through bending tests, demonstrating mechanical stability and reliability in plastic substrates, which will be described in more detail below. Finally, RAM operation of the RRAM device on the flexible substrate has been implemented. From these results, the flexible device according to the present invention showed the possibility of a new high-performance non-volatile memory device.

1 is a step-by-step view illustrating a method of manufacturing an 8 x 8 matrix 1T-1R flexible RRAM on a plastic substrate according to an embodiment of the present invention.

Referring to FIG. 1, first, a patterned and doped silicon nanomembrane on an SOI substrate was transferred from a SOI substrate onto a polyimide substrate (Dupont, Kapton), wherein the spin-cast PI precursor (poly (amic acid), Sigma) Aldrich) was used as the adhesive layer.

After transfer, the active region of the transistor was isolated via photolithography and SF6 plasma matching, and the PI precursor was cured at 250 ° C. for 1 hour in a nitrogen atmosphere (see FIG. 1A). SiO 2 (˜120 nm), the gate insulating layer, was deposited by PECVD at 300 ° C. Source and drain contacts were patterned by lithography and buffered oxide etchant (BOE). Drain and gate electrodes of chromium / gold (10 nm / 200 nm) were deposited by RF sputtering and defined by photolithography and wet etching processes (see FIG. 1B). After forming the switching transistor, the Al lower electrode was deposited in the drain region through the RF sputtering and lift-off process (Fig. 1 (c)). Amorphous TiO 2 (α-TiO 2) thin films were deposited by plasma atomic layer deposition (PEALD, ASM Genitech MP-1000) at a substrate temperature of 100 ° C. The thickness of the thin film was ˜14 nm after 270 cycles. Titanium tetra-iso-propoxide (TI (OCH (CH ₃ ) ₂ ) ₄ ; TTIP) and oxygen plasma were used as Ti precursor and oxygen source (FIG. 1 (d)). After depositing the variable resistance layer α-TiO ₂ layer, an Al upper electrode was deposited in the same manner as the lower electrode (FIG. 1E). Bit lines, source lines and word lines of chromium / gold (10 nm / 200 nm) were successively patterned by RF sputtering and wet etching processes (FIG. 1E). The spincast SU-8 layer was opened in a photo-lithography process to provide an interlayer dielectric layer between metal interlayers.

FIG. 2A is a schematic diagram illustrating an 8 × 8 matrix 1T-1R flexible RRAM structure on a plastic substrate. FIG.

Referring to FIG. 2A, the fabricated n-channel metal-oxide semiconductor field effect transistor (NMOSFET) exhibited a channel length of 10, a contact overlap (Lo) of 20 μm, and a channel width of 200 μm. A doped silicon membrane (100 nm thick) transferred from a silicon-on-insulator (SOI) wafer to a plastic substrate was used as the active layer of the transistor. In addition, for resistance switching, which is an on-off element of the memory device, an α-TiO ₂ layer was provided between the lower and upper electrodes, and the α-TiO ₂ layer was formed in the drain region. The entire memory cell was interconnected via word, bit and source lines in a NOR type array.

2B is an enlarged optical image of the 1T-1R array.

Referring to FIG. 2B, a gate source electrode is connected to a word line WL and a source line SL to control a transistor, and an Al upper electrode is connected to a bit line BL, thereby indicating a logic state of a memory unit cell. To control. The integrated transistor serves to maintain the logic state of the memory cell when another cell is accessed.

2C is a BFTEM image of a flexible device formed on a plastic substrate in accordance with the present invention. Referring to Figure 2c, a metal having a uniform height - is metal (MIM) layer (120 nm Al / 14 nm α -TiO 2/120 nm Al) may know that the formation on a plastic substrate, an insulating layer. Also, the inserted figure shows that the titanium oxide layer is clearly present between the two aluminum electrodes.

2D shows an enlarged view of a flexible 1T-1R RRAM device according to the present invention.

Referring to FIG. 2D, the flexible RRAM according to the present invention shows an NOR type 8 × 8 memory cell matrix, and an active region on a 25 μm thick polyimide film was 1 × 1 cm 2. Metals (Au pads are connected to WL, BL, and SL to allow each 1T-1R memory unit cell to be accessed. The interpolated figure shows an enlarged view of 4 memory unit cells, even in a bent form of the memory according to the present invention. Figure 2e shows the device according to the invention with excellent mechanical flexibility without breaking, referring to Figure 2e, a level of flexibility to wrap a 10 mm diameter quartz rod. The ductility of metal lines and ultra thin inorganic materials (silicon membranes and amorphous titanium oxides) provides an excellent stability of the RRAM device according to the invention on a flexible substrate. It is a picture showing that the flexible RRAM can provide a uniform contact area. Effective institutions.

3A is a schematic structure of an RRAM single cell composed of two electronic elements. The two electronic elements here are NMOSFET and α-TiO ₂ layers based on dipole resistive memory elements. By applying a voltage on the source / drain / gate electrodes, the logic state of the memory device can be controlled. 3B is a graph showing the output performance of the NMOSFET. The effective device mobility of the transistor according to the invention was 340 cm ² / V · s in the linear region, which can be derived through the transfer curve of the interpolated figure of FIG. 3B. For resistance switching of the α-TiO ₂ layer, a current of at least 500 μA is required to apply the necessary voltage for switching between the two electrodes. NMOSFET devices can easily meet these conditions at low drive voltages ((I _D to 500 μA at V _D = 1 V, V _G = 4 V). These results demonstrate the use of ultra-thin single crystal silicon as an active layer. The flexible transistor according to the invention shows that it can be utilized as an effective switching memory device in terms of sufficient current level and on / off ratio.

3C shows a typical drain current-voltage curve I _D - V _D of a flexible RRAM device according to the present invention, wherein 10 V is applied at the gate electrode and the source electrode is grounded for channel opening. The device switches from the high resistance state HRS to the low resistance state LRS state as the drain voltage is swept from 0V to a negative voltage for the SET voltage. LRS is still maintained when it returns to a positive RESET voltage. This indicates that the RRAM memory device according to the present invention exhibits asymmetric dipole resistance switching (BRS) behavior. To more closely analyze the current conduction mechanism, a double log plot of the I _D - V _D curve for the negative voltage region is shown in the interpolation in FIG. 2C. I _D - V _D of HRS The plot ohmic conductivity behavior in the low-voltage region (<0.2 V) slowly to the showed, the square dependence, as indicated in Fig. _{3c (| I D | α |} | V D) (| 2 I D | α | | VD) Changed. After a sudden current increase at a SET voltage of 2.1 V, the memory state changed to LRS. In particular, the slope of the log I- log V plot was slightly less than 2 in the high voltage region of LRS (1.7). This means that current conduction cannot simply be explained by electronic trapping and detrapping phenomena. Thus, this can be explained by the change in trap distribution in the upper interface layer (Al-Ti-O) resulting from the behavior of coral ions by external bias.

FIG. 3D shows the drain current-gate voltage I _D - V _G curve of the 1T-1R flexible RRAM device according to the invention at a leading voltage of -0.5 V in LRS and HRS. Referring to FIG. 3D, the drain current shows a clear distinction depending on the state of the memory, which indicates that the logic state of the unit cell can be easily identified at a fixed reading voltage.

Tests for durability and retention were performed to investigate the reliability of the flexible RRAM according to the present invention.

3E shows the endurance cycling test results at 0.5 v reading voltages obtained by repeated on / off sweeping operations. For 100 cycles, both HRS and LRS retained their resistance without particular change in reading voltage, which represents a reproducible resistance switching characteristic. The retention / maintenance characteristics of the 1T-1R RRM were analyzed at room temperature to evaluate the data storage capacity, as shown in FIG. 3F, wherein the resistance values of the HRS and LRS have a gate open voltage of 10 V and a reading of -0.5 V. It was analyzed every 300 seconds under voltage conditions. Referring to FIG. 3F, excellent retention characteristics were exhibited for 10 ⁴ seconds without electrical degradation in LRS and HRS states.

In another embodiment of the present invention, a 1T-1C ZrO2 capacitor DRAM and a 1D-1R GST phase change memory are illustrated in FIGS. 4A through 4B using single crystal silicon transferred from a silicon substrate and a polycrystalline silicon high performance switching device crystallized from a plastic substrate. Respectively.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (19)

In the method of manufacturing a flexible memory device, the method
Fabricating a high performance polycrystalline or single crystal silicon switching device on a flexible substrate; And
Flexible memory device manufacturing method comprising the step of manufacturing a memory device comprising the switching device. The method of claim 1,
The silicon switching device is manufactured on a silicon substrate and then transferred to a flexible memory device manufacturing method. The method of claim 1,
The silicon switching device is a flexible memory device manufacturing method characterized in that the crystallized from the amorphous silicon to polycrystalline or monocrystalline silicon in the plastic substrate. In the flexible memory device manufactured by claim 2 or 3,
The memory device is a flexible memory device manufacturing method, characterized in that the RRAM, DRAM or PRAM. 5. The method of claim 4,
And the switching element is a transistor having a diode or a source-gate-drain region. The method of claim 5, wherein manufacturing the memory device
After the transfer, laminating an on-off element for turning on and off the memory device on the drain region of the transistor, wherein the on-off element is a resistive memory for RRAM, a capacitor for DRAM, and Flexible memory device manufacturing method characterized in that the case of PRAM phase change memory Isolating a plurality of unit device regions with a silicon membrane layer on the plastic substrate;
Depositing a gate insulating layer on the unit device region;
Forming source and drain contacts on the gate insulating layer;
Stacking a metal on the gate insulating layer to form a source-gate-drain electrode to manufacture a switching transistor;
Stacking a lower electrode on a drain region of the switching transistor;
Stacking a memory layer on the lower electrode;
Stacking an upper electrode on the memory layer;
Connecting upper electrodes of the plurality of unit device regions with bit lines;
Connecting source electrodes of the plurality of unit device regions to source lines; And
And connecting gate electrodes of the plurality of unit device regions with word lines.
Stacking an upper electrode on the memory layer; 8. The method of claim 7,
And transferring the silicon membrane layer from the silicon substrate to the plastic substrate. The method of claim 8,
The silicon membrane layer is a flexible memory device manufacturing method characterized in that the crystallized after being transferred to a plastic substrate. A flexible memory device manufactured by claim 9,
The memory device is a flexible memory device manufacturing method, characterized in that the RRAM, DRAM or PRAM. The method of claim 10,
And insulating layers are stacked between the bit lines, the source lines, and the word lines. 12. The method of claim 11,
The lower and upper electrodes are Al, and the memory layer is a variable resistive layer, wherein the amorphous titanium oxide layer is a flexible memory device manufacturing method. A flexible memory device manufactured by the method according to any one of claims 7 to 12, wherein the flexible memory device is a flexible RRAM. A flexible memory device, wherein the memory device is manufactured on a sacrificial substrate and then transferred to a flexible substrate. The method of claim 14,
And the memory element further comprises an on-off element for turning on and off the switching element after the transfer, wherein the on-off element is formed in the memory element after the transfer. 16. The method of claim 15,
The memory device is a flexible memory device, characterized in that the RRAM. 17. The method of claim 16,
The RRAM is formed on one transistor consisting of a source / gate / drain electrode and the drain electrode, and a flexible memory device, characterized in that consisting of one RRAM element consisting of a lower electrode / variable resistance layer / upper electrode. 18. The method of claim 17,
And the transistor is formed on a silicon membrane layer, and the silicon membrane is manufactured on a silicon substrate and then transferred to a flexible substrate. 19. The method of claim 18,
The lower and upper electrodes are Al, and the variable resistance layer is an amorphous titanium oxide layer.

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