KR20130014194A

KR20130014194A - 3d image lcd and driving method for the same

Info

Publication number: KR20130014194A
Application number: KR1020110076158A
Authority: KR
Inventors: 김민규
Original assignee: 엘지디스플레이 주식회사
Priority date: 2011-07-29
Filing date: 2011-07-29
Publication date: 2013-02-07

Abstract

The present invention discloses a stereoscopic liquid crystal display device. In particular, the present invention relates to a stereoscopic image liquid crystal display device and a driving method thereof in which driving power of a liquid crystal display device for implementing a 3D image using binocular disparity is reduced.
A driving method of a stereoscopic image liquid crystal display device according to an embodiment of the present invention comprises the steps of: receiving an image signal including an image and a right eye image; And generate an interpolation image of the nth frame (n is a natural number) if the image signal is a 2D image, and display the interpolated image on the n + 1 frame. Up to and including the steps.
Accordingly, by driving the liquid crystal display device in a hold type by excluding overlapping images, it is possible to provide a stereoscopic image display device and a driving method thereof in which power consumption of the driving circuit is reduced without degrading image quality.

Description

3D IMAGE LCD AND DRIVING METHOD FOR THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stereoscopic image liquid crystal display device, and more particularly, to a stereoscopic image liquid crystal display device and a driving method thereof in which a driving power of a liquid crystal display device for implementing a 3D image using binocular disparity is reduced.

Liquid crystal display devices (Liquid Crystal Display Device) is replacing the existing display devices due to the characteristics of light and thin. A typical liquid crystal display device displays a desired image on a screen by adjusting the transmission amount of liquid crystal according to image signals applied to a plurality of control switches arranged in a matrix form.

1 is a block diagram schematically illustrating a structure of a conventional liquid crystal display device.

As shown in the drawing, a conventional liquid crystal display device includes an external system 1 that provides various data for displaying an image, and receives and receives data from the external system 1 through an interface 3 from the external system. A timing controller 4, a driver 6 for generating a scan signal and a video signal under the control of the timing controller 4, and a light transmittance of the liquid crystal under the control of the driver 6 to display an image. Consisting of a display panel 8.

In particular, such a liquid crystal display device has a disadvantage in that a motion blur that blurs a screen is likely to occur due to a low response speed of liquid crystals. Estimation Motion Compensation (3) is provided to insert a interpolation image between 60 Hz images to realize a clearer image.

Recently, as interest in 3D stereoscopic images has increased, a technique for implementing a stereoscopic image display apparatus using a liquid crystal display apparatus has been proposed. The stereoscopic image display device implements a virtual 3D image by using a binocular disparity in which a human eye appears about 65 mm apart in a horizontal direction among various factors in which a viewer feels a stereoscopic feeling. The human eye sees different images even when looking at the same object because of binocular disparity, and when these two images are transmitted to the brain through the retina, the brain can fuse them together precisely so that we can feel a three-dimensional feeling. By displaying two images at the same time in the left and right to send separately to create a virtual three-dimensional effect.

As a method of realizing such a stereoscopic image, there are a method of wearing glasses and a glasses-free method of not wearing glasses, and a method of wearing glasses, an anaglyph method of using blue and red sunglasses on each side, Shutter glass with glasses equipped with a film pattern retarder (FPR) that uses polarized glasses with different polarization directions, and a liquid crystal shutter that repeats the time-divided screen periodically and synchronizes the period. , SG).

However, when implementing a stereoscopic image using a liquid crystal display device of 100Hz or more as described above, there is a disadvantage that unnecessary power consumption is increased. 2A and 2B are diagrams for describing an image processing method of a conventional pattern retarder method and a shutter glass type stereoscopic liquid crystal display device. Referring to FIG. 2A, in the case of a pattern retarder method liquid crystal display device, horizontal lines In this 1080 line display panel, images corresponding to the left eye L1 to L1079 and the right eye R1 to R1079 are alternately displayed on one screen. The first image (n, n is a natural number) and the third image ( n + 2) is an original image input from an external system, and the second image n + 1 and the fourth image n + 3 are interpolated images generated by the MEMC (3 in FIG. 1). Therefore, the first image n and the second image n + 1 are the same image, and the two images are combined to drive 120 Hz.

In addition, referring to FIG. 2B, in the case of the shutter glass type liquid crystal display, only one of the images corresponding to the left eye L or the right eye R is displayed on one screen, and each image is alternately displayed on the left eye L. FIG. ) And the right eye (R). Therefore, the first image (n, n is a natural number) and the third image (n + 2) are the original image, and the second image (n + 1) and the fourth image (n + 3) are the MEMC (3 in FIG. 1). The point of the interpolation image generated by) is the same as the pattern retarder method described above, but since only one field of view is displayed on one image, the first image (n) and the second image (n + 1) are added together to 240 Hz. To drive.

Therefore, although the above-described second image n + 1 and the fourth image n + 3 are overlapping images, the timing controller (4 in FIG. 1) and the driver (6 in FIG. 1) may be used to display them. A control signal corresponding to this is generated to control the display panel (8 of FIG. 1), and an image signal must be aligned and converted to be provided. Accordingly, there is a problem that unnecessary power waste occurs.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and the three-dimensional image liquid crystal display device which reduces the power consumption of the driving circuit and simplifies the structure of the driving circuit without deteriorating the image quality in the three-dimensional image display device driving at 100 Hz or more. It relates to a driving method.

In order to achieve the above object, a method of driving a stereoscopic image liquid crystal display device according to an embodiment of the present invention, receiving an image signal including a left eye image and a right eye image from an external system; And generate an interpolation image of the nth frame (n is a natural number) if the image signal is a 2D image, and display the interpolated image on the n + 1 frame. If the image signal is a 3D image, the nth frame is an n + 1 frame period. Up to and including the steps.

Maintaining the n frame until the n + 1 frame period may include dividing one frame of the video signal into two subframes; And displaying the subframe at a unit frequency.

The unit frequency is characterized in that 60Hz.

The two subframes are characterized in that the one frame is divided into a left eye image and a right eye image.

The two subframes are characterized in that the one frame is alternately divided by two horizontal lines.

The two sub-frames are characterized in that the one frame is divided into a screen divided into two forms.

In order to achieve the above object, a stereoscopic image liquid crystal display device according to an embodiment of the present invention, a display panel for displaying an image; A MEMC that receives an image signal including a left eye image and a right eye image corresponding to the image from an external system, and inserts an interpolation image; If the video signal received from the MEMC is a 2D video, the video signal including the interpolated video for the nth (n is a natural number) frame is output. If the video signal is a 3D video, the nth frame excluding the interpolated video is removed. a timing controller for generating a control signal for maintaining up to n + 1 frame periods; And a driver for driving the display panel according to the control of the timing controller.

The timing controller may include: an image processor configured to determine a 2D image or a 3D image of the image signal, and output an image signal including an interpolated image for an nth (n is a natural number) frame if the image signal is a 2D image; And a signal processor configured to generate the control signal to maintain the nth frame until the n + 1th frame period when the image signal is a 3D image.

In order to achieve the above object, a stereoscopic image liquid crystal display device according to an embodiment of the present invention, a display panel for displaying an image; A MEMC that receives an image signal including a left eye image and a right eye image corresponding to the image from an external system, and inserts an interpolation image; If the video signal received from the MEMC is a 2D video, the video signal including the interpolated video for the nth (n is a natural number) frame is output. a timing controller for masking the control signal to maintain up to n + 1 frame periods; And a driver for driving the display panel according to the control of the timing controller.

The control signal is a gate output enable signal.

According to a preferred embodiment of the present invention, the MEMC of the stereoscopic image liquid crystal display device is embedded in a timing controller, and the liquid crystal display device is driven in a hold type by excluding overlapping images, thereby reducing the power of the driving circuit without deterioration of image quality. It is possible to provide a stereoscopic image display device and a driving method thereof having reduced consumption.

In addition, according to another embodiment of the present invention, there is another effect that can provide a three-dimensional display device and a driving method for reducing power consumption through a timing controller having a simpler structure through a masking technique.

1 is a block diagram schematically illustrating a structure of a conventional liquid crystal display device.
2A and 2B are diagrams for describing an image processing method of a conventional pattern retarder method and a shutter glass type stereoscopic liquid crystal display device.
3 is a diagram illustrating a structure of a stereoscopic liquid crystal display according to an exemplary embodiment of the present invention.
4A is a diagram for describing a conventional stereoscopic image processing method, and FIG. 4B is a diagram for explaining a 3D image processing method of a stereoscopic image liquid crystal display according to a first embodiment of the present invention.
5A and 5B illustrate output signal waveforms of a gate and a data driver according to the stereoscopic image display method illustrated in FIGS. 4A and 4B, respectively.
FIG. 6 is a diagram illustrating a structure of a timing controller of a stereoscopic image liquid crystal display according to a first embodiment of the present invention.
7 is a diagram illustrating a stereoscopic image processing method according to a second embodiment of the present invention.
FIG. 8 is a diagram illustrating output signal waveforms of a gate and a data driver according to the stereoscopic image display method of FIG. 7.
9 is a diagram illustrating a stereoscopic image processing method according to a third embodiment of the present invention.
10 is a diagram illustrating a stereoscopic image processing method according to a fourth embodiment of the present invention.
FIG. 11 is a diagram illustrating output signal waveforms of a gate and a data driver according to the stereoscopic image display method of FIG. 10.
12 is a diagram illustrating another example of a timing controller according to an embodiment of the present invention.

Hereinafter, a stereoscopic liquid crystal display and a driving method thereof according to a preferred embodiment of the present invention will be described with reference to the drawings. The following description describes the technical idea of the present invention as an example of a stereoscopic image display device to which a pattern retarder method (FPR) using polarizing glasses having different polarization glasses in different stereoscopic image implementation methods is provided, and the scope does not depart from the scope. It can also be applied to the shutter glass system (SG) within.

3 is a diagram illustrating a structure of a stereoscopic liquid crystal display according to an exemplary embodiment of the present invention.

As shown, the stereoscopic image liquid crystal display device of the present invention comprises a MEMC (20) for receiving an image signal from the external system 10 to generate an interpolated image according to the image type, and generates a control signal corresponding to the image type. Providing a display panel with a timing controller 50 for aligning and converting a video signal received from the MEMC, a gate driver 60 for generating a scan signal under the control of the timing controller 50, and the converted video signal. A data driver 70 and a display panel 80 for implementing an image.

In detail, the external system 10 may include a plurality of video chips, a video controller, a CPU, and the like. The external system 10 may control 2D or 3D image signals 2D_DATA and 3D_DATA and a flat panel display device for an image to be displayed. The data enable signal DE, the clock signal DCLK, the horizontal synchronization signal Hsync, and the vertical synchronization signal Vsync are generated and provided to the MEMC 20.

The MEMC 20 receives any one of the 2D image signal 2D_DATA or the 3D image signal 3D_DATA, generates an interpolated image, inserts the interpolated image, and transmits the interpolated image to the timing controller 50. The external system 10 and the MEMC 20 described above may be implemented as one system 30.

The timing controller 50 processes the video signal according to the format of the received video signal, and controls the gate control signal G_sig and the data control signal S_sig for controlling the gate driver 60 and the data driver 70 to be described later. It generates and provides to each driver (60, 70).

The timing controller 50 receives an image signal including a left eye image and a right eye image corresponding to the image from the MEMC 20. If the image signal is a 2D image, the generated interpolation for the nth (n is a natural number) frame is performed. When the image signal is a 3D image, the image signal is input to the data driver 70. The control signal is generated to maintain the nth frame until the n + 1 frame period except for the interpolation image described above.

The type of the above-described image signal is determined by the flag signal FLAG_SIG, which is identification data provided from the external system 10, and the timing controller 50 determines the driving method and processes the image signal according to the flag signal FLAG_SIG. .

In addition, the timing controller 50 controls the gate output signal GOE, the gate start pulse GSP, and the gate shift clock GSC, which are the control signals of the gate driver 60, in response to the data enable signal DE described above. It generates and transmits to the gate driver 60. In addition, the timing controller 50 corresponds to the above-described data enable signal DE and the like, the source output signal SOE, the source start pulse SSP, the source shift clock SSC, and the control signals of the data driver 20. The polarity control signal POL is generated and transmitted to the data driver 70.

Accordingly, if the 3D image signal 3D_DATA, the timing controller 50 generates and transmits control signals of the gate and data drivers 60 and 70 to drive in a 2 frame hold type without interpolation images. .

Although not shown, the above-described timing controller 50 is connected to a predetermined interface with the external system 10 for high speed and stable data reception, and low voltage differential signal (LVDS) is preferably applied. Do.

The gate driver 60 controls on / off of the switching elements TFT arranged on the display panel 80 in response to the gate control signal G_SIG input from the timing controller 20. The output terminal of the gate driver 60 is connected to a plurality of gate lines (GL1 to GLn (n is a natural number)) formed on the display panel 190. Through this, the gate driving signal is sequentially output for one horizontal line, thereby providing a gate line. The plurality of switching elements TFTs connected to the GL1 to GLn become conductive. Accordingly, when the data driver 70, which will be described later, applies an image signal aligned to each switching element TFT, the image signal is applied to the liquid crystal cell Lc connected to each switching element TFT to implement an image. Done.

The data driver 70 aligns the digital image signal DATA ′ input in response to the data control signal S_SIG input from the timing controller 20, selects reference voltages gamma, and accordingly, analog type. Generates a video signal aDATA. The generated image signals are sequentially latched by one horizontal line, and when all image signals corresponding to one horizontal line are prepared, the generated image signals are transmitted to the display panel 80 through all the data lines DL1 through DLn.

In the display panel 80, a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLn are arranged in a matrix on a transparent substrate, and a plurality of pixels are defined at the intersections thereof. The gate lines GL1 to GLn are connected to the gate driver 60, the data lines DL1 to DLn are connected to the data driver 70, and each pixel is provided with a switching element TFT. Accordingly, the switching element TFT is turned on in response to the signals input to the gate lines GL1 to GLn, and an image signal is applied to the liquid crystal cell Lc through the data lines DL1 to DLn to implement an image. do.

An FPR filter (not shown) having a plurality of retarder patterns is attached to the front surface of the display panel 80. The FPR filter transmits only a specific circularly polarized light from the light emitted from the display panel 80, and has a structure in which the first retarder pattern in one direction and the second retarder pattern in the other direction symmetric thereto are alternately arranged. The first and second retarder patterns are each formed of a birefringent medium to circularly polarize the light passing through the + λ / 4 and −λ / 4 phase delays. That is, the optical axes of the first retarder pattern and the second retarder pattern are orthogonal to each other. Accordingly, the first retarder pattern is disposed to face the line on which the left eye image is displayed on the display panel 80 to provide light of the left eye image. Convert to left circular polarization. Similarly, the second literer pattern is disposed on the display panel 80 so as to face the line on which the right eye image is displayed to convert light of the right eye image into right circularly polarized light.

According to this structure, an observer wearing a polarizing filter having only a left circularly polarized light passing through the left eye and a polarizing filter having only a right circularly polarized light passing through the right eye sees only the image to the left eye and the right eye. When the image displayed on 80 is a 3D image, that is, an image divided into a left eye and a right eye, it is sensed in three dimensions.

According to the above structure, the driving method is determined by the timing controller 50 in the stereoscopic image liquid crystal display according to the exemplary embodiment of the present invention, and when the image to be displayed is 2D, the image of 120 Hz with improved motion blur Implement In addition, in the case of a 3D image, by generating a signal for half of 120Hz and driving in accordance with the two-frame holding method, driving of the drivers 60 and 70 is stopped for half the unit frequency, thereby reducing power consumption. You can do it. Hereinafter, an image processing method of a stereoscopic liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings. In the following description, for convenience of description, reference numerals of the stereoscopic liquid crystal display shown in FIG. 3 will be referred together.

4A is a diagram for describing a conventional stereoscopic image processing method, and FIG. 4B is a diagram for explaining a 3D image processing method of a stereoscopic image liquid crystal display according to a first embodiment of the present invention.

As illustrated, in the conventional stereoscopic image processing method, in the case of a display panel having a horizontal line of 1080 ^th LINE, the image signal input from the external system includes one image corresponding to the left eye L1 to L1079 and the right eye R1 to R1079. This is the form displayed alternately on the screen. Accordingly, the stereoscopic image is realized by combining the image separated into the left eye image 540 lines and the right eye image 540 lines.

Conventionally, the first image (n, n is a natural number) and the third image (n + 2) are original images input from an external system, and the second image (n + 1) and the fourth image (n + 3) are MEMCs. It is an interpolation image generated by (20 of FIG. 1). Accordingly, the first image n and the second image n + 1 are the same image, and both images are driven at 120 Hz.

In contrast, in the 3D image processing method of the stereoscopic image liquid crystal display according to the present invention, when the timing controller 20 is a 2D image according to the flag signal FLAG_SIG, the 3D image processing method is an interpolation image of the first image n. A second image n + 1 and a fourth image n + 3 which is an interpolation image of the third image n + 2 are generated, inserted between the images, and transmitted to the data driver 70. Accordingly, the first image n and the second image n + 1 form one image, which is recognized by the viewer as one image is driven at a frequency of 60 Hz.

Here, each of the first image n to the fourth image n + 4 may include at least one frame or subframe.

In addition, in the case of the 3D image, only the first image n and the third image n + 2 are transmitted to the data driver 20 without generating an interpolation image, and the gate driver and the data driver maintain two frames. Drive the way. Accordingly, the first image n and the third image n + 2 each form one image, which is recognized by an observer as one image is driven at 60 Hz.

Therefore, in the case of driving the 3D image of the present invention, the gate and data drivers are driven at half the power consumption compared to the conventional art. Hereinafter, the difference in power consumption of the present invention will be described with reference to the signal waveform output from each driver.

5A and 5B illustrate output signal waveforms of a gate and a data driver according to the stereoscopic image display method illustrated in FIGS. 4A and 4B, respectively.

As shown, in the conventional 3D image processing method, the gate driver 60 receives a gate shift clock (GSC), a gate output enable (GOE), and a gate start pulse from the timing controller 20. A control signal such as Gate Start Pulse (GSP) is input and driven, and a plurality of gate lines GL1 to GLn are applied by sequentially applying a driving signal of the thin film transistor TFT to the plurality of gate lines GL1 to GLn. Drive by 1 horizontal line sequentially.

In this case, the gate shift clock GSC applied to the gate driver 60 is a signal specifying a turn-on time of the thin film transistor T, and the gate output enable signal GOE is a gate driver. The signal for controlling the output of the 310 is a signal indicating that the gate start pulse GSP is the start line of the screen, that is, the first horizontal line 1 ^ST LINE in the application of one vertical signal.

In addition, the data driver 70 may include a source sampling clock (SSC), a source output enable (SOE), a source start pulse (SSP), and a polarity reverse signal (POL). And a control signal such as a) and an image signal DATA, and drive one horizontal line of image data in synchronization with the driving signal of the thin film transistor TFT applied to the gate lines GL to GLn. ~ DLn).

In this case, the source sampling clock signal SSC is a sampling clock for latching the image signal DATA based on the rising edge or the falling edge, and the source output enable signal SOE is a latched image signal DATA in the data line The control signal is output to DL1 to DLn, and the source start pulse SSP is a signal indicating the first pixel which is the start point of data in the application of one horizontal signal, and the polarity control signal POL is inversion driving. This is a signal that controls the inversion of the polarity of the liquid crystal.

Accordingly, in the conventional 3D image processing shown in FIG. 5A, first, as the display period of the first image, the gate driver 60 starts the first horizontal line 1 ^ST LINE in response to the start of the gate start pulse SSP. ), The high signal (high) is sequentially applied from the 1080 horizontal line (1080 ^TH LINE), and correspondingly, the data driver 70 transmits the first cardinal image {L1 (n)} of the left eye and the first cardinal number of the right eye. The last cardinal image {l079 (n)} of the left eye and the last cardinal image {R1079 (n)} of the right eye are transmitted to the display panel 80 in the order of the image {R1 (n)}.

Next, when a high signal is sequentially applied to the 1080 horizontal line 1080 ^TH LINE, the same driving as the above-described first image is repeated as a display section of the second image, and the first image and the second image are repeated. It will drive 120Hz total to the image.

In contrast, in the 3D image processing according to the embodiment of the present invention illustrated in FIG. 5B, as the display section of the first image is first displayed, the gate driver 60 performs a first operation according to the start of the gate start pulse SSP. The high signal (high) is sequentially applied from the horizontal line (1 ^ST LINE) to the 1080 horizontal line (1080 ^TH LINE), and correspondingly, the data driver 70 receives the first radix image {L1 (n)} of the left eye. , The last radix image {l079 (n)} of the left eye and the last radix image {R1079 (n)} of the right eye are transmitted to the display panel 80 in the order of the first radix image {R1 (n)} of the right eye. It is the same as before.

However, when the high signal is sequentially applied to the 1080 horizontal line (1080 ^TH LINE), the timing controller (eg, the source output enable signal SOE and the gate enable signal GOE) is displayed in the display section of the second image. All the signals output from 20 are shifted to the low level, so that the output signal of the gate driver 60 is maintained at the low level, so that the output of the data driver 70 is not generated. do.

Accordingly, the image signal applied to the liquid crystal cell Lc of the display panel 80 maintains the previous frame, thereby implementing the same second image as the first image. Therefore, in the stereoscopic image display apparatus of the present invention, the gate and the data driver are driven at half the power consumption compared with the prior art {(S2) = (S1) / 2}. Here, the first image and the second image are actually the same image, and the viewer recognizes the same as the 60 Hz driving up to the third image, which is the next image.

FIG. 6 is a diagram illustrating a structure of a timing controller of a stereoscopic image liquid crystal display according to a first embodiment of the present invention.

As shown, the timing controller 50 of the stereoscopic image liquid crystal display device of the present invention determines the shape of the image received from the MEMC, and corresponding to the image processor 51 for performing 2D or 3D image processing, and the image, And a signal processor 54 for generating control signals of the gate and the data driver according to the determination of the processor 51.

The image processor 51 receives the flag signal FLAG_S from an external system, determines whether the transmitted video is a 2D video signal 2D_DATA or a 3D video signal 3D_DATA, and the determined video signal is a 2D video signal. In the case of (2D_DATA), the original video signal into which the interpolation video is inserted is aligned and converted into a form that can be used by the data driver 70 and inputted to the data driver 70.

In addition, when the determined video signal is the 3D video signal 3D_DATA, the signal processor 54 is informed that it is a 2 frame hold driving, and the original video signal excluding the interpolated video is aligned and converted to provide a data driver ( 70).

In addition, the signal processor 54 includes a gate signal generator 56 and a data signal generator 57.

The gate signal generator 56 generates a signal such as a gate shift clock GSC, a gate output enable signal GOE, and a gate start pulse GSP for controlling the operation timing of the gate driver and inputs the same to the gate driver. do.

The data signal generator 57 may include a source sampling clock SSC, a source output enable SOE, a source start pulse SSP, and a polarity inversion signal POL for controlling a data signal according to an operation timing and a polarity of the data driver. Create and enter into the data driver.

In particular, the signal processor 54 controls the gate and the data driver to drive in a 2 frame hold type without interpolation if the 3D image signal 3D_DATA corresponds to the image discrimination result of the image processor 51. It is responsible for generating signals.

According to the above structure, the timing controller of the stereoscopic image liquid crystal display device of the present invention controls the display panel to implement a 3D image by improving the power consumption according to the type of the image. Hereinafter, an image processing method of a stereoscopic liquid crystal display device according to another embodiment of the present invention will be described with reference to the drawings.

7 is a diagram illustrating a stereoscopic image processing method according to a second embodiment of the present invention.

As shown, according to the second embodiment of the present invention, the right eye image R, except for the left eye image L, is extracted from the first image n, and only the horizontal line corresponding to the right eye image r is extracted. It is characterized by generating two images (n + 1).

Accordingly, the first image is first displayed in the first frame up to the 1079 horizontal line (1079 ^th LINE) in the order of the first horizontal line (1 ^st LINE), the third horizontal line (3 ^rd LINE), the second frame In the second image, up to the 1080 horizontal line (1080 ^th LINE) is displayed in the order of the second horizontal line (2 ^nd LINE), the fourth horizontal line (4 ^th LINE). At this time, the first image of the first frame is driven to maintain two frames until the third image starts. In addition, the second image is driven to maintain two frames until the fourth image starts.

Accordingly, the first image n and the second image n + 1 form one image, respectively, as if each image is driven at 120 Hz.

FIG. 8 is a diagram illustrating output signal waveforms of a gate and a data driver according to the stereoscopic image display method of FIG. 7.

As shown, first, as the display section of the first image, in response to the start of the gate start pulse SSP, the gate driver 60 may include a first horizontal line (1 ^st LINE) and a third horizontal line (3 ^rd LINE). The high signal (high) is applied to the 1079th horizontal line (1079 ^th LINE) in the order of. The data driver 70 corresponds to the first cardinal image {L1 (n)} of the left eye, and the second cardinal image of the left eye. The last radix-th image {L1079 (n)} of the left eye is transmitted to the display panel 80 in the order of {L3 (n)}. That is, it drives in an interlace form in units of one horizontal line.

Then, in the next frame, the gate driver 60 has a second horizontal line (2 ^nd LINE), a fourth horizontal line, the 1080 horizontal lines in the order of (4 ^th LINE) (1080 ^th LINE) high signal (high) to In response, the data driver 70 transmits the last cardinal image of the left eye in the order of the first cardinal image {R1 (n + 1)} of the right eye and the second cardinal image {R3 (n + 1)} of the right eye. {Rl080 (n + 1)} is transmitted to the display panel 80.

Accordingly, each frame can reduce half the power consumption in the same section compared to the prior art {(S1) = (S3) + (S4)}.

9 is a diagram illustrating a stereoscopic image processing method according to a third embodiment of the present invention.

As shown, according to the third embodiment of the present invention, the left eye image L and the right eye image R are extracted one by one in a horizontal line unit from the first image n, and the second image n + 1 is extracted. It characterized in that to generate.

In this way, first the first image has a first horizontal line (1 ^st LINE), the second horizontal line (2 ^nd LINE) the 1077 horizontal lines (1077 ^th LINE) shown in the first frame, and to the second frame in the order of in is displayed to a second image, the third horizontal line (lINE 3 ^rd), a fourth horizontal line (4 ^th lINE) the 1078 horizontal lines (lINE 1078 ^th) in this order. At this time, the first image of the first frame is driven to maintain two frames until the third image starts, as in the above-described second embodiment. In addition, the second image is driven to maintain two frames until the fourth image starts. That is, it is driven in an interlace form in units of two horizontal lines.

10 is a diagram illustrating a stereoscopic image processing method according to a fourth embodiment of the present invention.

As shown, according to the fourth embodiment of the present invention, the first image n includes the first horizontal line 1 ^st LINE to the 540th horizontal line 540 ^th LINE, and the second image n +1), up to and including the 540 horizontal lines (540 ^th lINE) from the 1080 horizontal lines (lINE 1080 ^th) to be characterized in that it displays each frame in alternation.

In this way, first the first image has a first horizontal line (1 ^st LINE) from 540 horizontal lines displayed on the first frame to the (540 ^th LINE), and the second frame as the second image, the 541 horizontal lines (541 ^rd LINE) to the 1080th horizontal line (1080 ^th LINE) is displayed sequentially. In this case, the first frame of the first frame is driven to maintain two frames until the third image is started, as in the above-described second and third embodiments. That is, it is driven in the form of an interlace in half screen units. This means that the first image n and the second image n + 1 form one image, and each image is driven at 120 Hz.

FIG. 11 is a diagram illustrating output signal waveforms of a gate and a data driver according to the stereoscopic image display method of FIG. 10.

Accordingly, each frame can reduce half the power consumption in the same section compared to the prior art {(S1) = (S5) / 2}.

12 is a diagram illustrating another example of a timing controller according to an embodiment of the present invention.

As shown, the timing controller of the present invention includes a data processing module 130 for processing data received from an external system, a signal processing module 150 for generating control signals of a gate and a data driver, and a data processing module ( And a data masking module 160 for masking data according to the type of the image signal received from the 130.

The data processing module 130 sorts and converts the data into a form inputtable to the data driver regardless of the type of the video signal.

The signal processing module 150 includes signals such as a gate shift clock GSC, a gate output enable signal GOE, and a gate start pulse GSP for controlling the operation timing of the gate driver, an operation timing of the data driver, It generates a source sampling clock (SSC), a source output enable (SOE), a source start pulse (SSP), and a polarity inversion signal (POL) to control data signals according to polarity, and inputs them to each driver.

The data masking module 160 receives the flag signal FLAG_S and inputs the data signal to the data driver as it is received from the data processing module 130 when the input image signal is the 2D image signal 2D_DATA. 3D_DATA), a part of control signal is masked to implement 2 frame holding drive.

For example, when the gate output enable signal GOE is masked at a high level, the gate output signal is always maintained at a low level, so that even when an image signal is input from the data driver, the switching element of the display panel Since it is not conducting, the image of the previous frame can be maintained as it is, and by maintaining it until the next frame, two frame maintenance driving can be implemented.

Accordingly, power consumption may be reduced when a stereoscopic image is implemented by using a timing controller having a simpler structure.

Many details are set forth in detail, but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

10: external system 20: MEMC
50: timing controller 60: gate driver
70: data driver 80: display panel
TFT: Switching element Lc: Liquid crystal cell
GL1 to GLn: Gate Line DL1 to DLn: Data Line

Claims

Receiving an image signal including a left eye image and a right eye image from an external system; And
If the video signal is a 2D image, an interpolation image of the nth (n is a natural number) frame is generated and displayed in the n + 1 frame. If the video signal is a 3D image, the nth frame is maintained until the n + 1 frame period. Steps to
Method of driving a three-dimensional image liquid crystal display comprising a.

The method of claim 1,
Maintaining the n frame until the n + 1 frame period,
Dividing one frame of the video signal into two subframes; And
Displaying the subframe in unit frequency
Method of driving a three-dimensional image liquid crystal display device comprising a.

The method of claim 2,
And the unit frequency is 120 Hz.

The method of claim 2,
The two subframes,
And the one frame is divided into a left eye image and a right eye image.

The method of claim 2,
The two subframes,
And one frame is alternately divided by two horizontal lines.

The method of claim 2,
The two subframes,
And the one frame is divided into a bisected form of a screen.

A display panel for displaying an image;
A MEMC that receives an image signal including a left eye image and a right eye image corresponding to the image from an external system, and inserts an interpolation image;
If the video signal received from the MEMC is a 2D video, the video signal including the interpolated video for the nth (n is a natural number) frame is output. a timing controller for generating a control signal for maintaining up to n + 1 frame periods; And
A driver to drive the display panel according to the control of the timing controller
Stereoscopic liquid crystal display device comprising a.

The method of claim 7, wherein
The timing controller,
An image processor for determining a 2D image or a 3D image of the image signal, and outputting an image signal including an interpolated image for an nth frame (n is a natural number) if the image signal is a 2D image;
A signal processor configured to generate the control signal to maintain an nth frame until an n + 1th frame period when the image signal is a 3D image;
Stereoscopic liquid crystal display device comprising a.

A display panel for displaying an image;
A MEMC that receives an image signal including a left eye image and a right eye image corresponding to the image from an external system, and inserts an interpolation image;
If the video signal received from the MEMC is a 2D video, the video signal including the interpolated video for the nth (n is a natural number) frame is output. If the video signal is a 3D video, the nth frame excluding the interpolated video is removed. a timing controller for masking the control signal to maintain up to n + 1 frame periods; And
A driver to drive the display panel according to the control of the timing controller
Stereoscopic liquid crystal display device comprising a.

The method of claim 9,
And the control signal is a gate output enable signal.