KR20130007295A - Hard disk drive, method of operating thereof, and data processing system having the same - Google Patents

Hard disk drive, method of operating thereof, and data processing system having the same Download PDF

Info

Publication number
KR20130007295A
KR20130007295A KR1020110065089A KR20110065089A KR20130007295A KR 20130007295 A KR20130007295 A KR 20130007295A KR 1020110065089 A KR1020110065089 A KR 1020110065089A KR 20110065089 A KR20110065089 A KR 20110065089A KR 20130007295 A KR20130007295 A KR 20130007295A
Authority
KR
South Korea
Prior art keywords
voltage
code
cpu
driving
hard disk
Prior art date
Application number
KR1020110065089A
Other languages
Korean (ko)
Inventor
오경환
하지원
이상호
Original Assignee
시게이트 테크놀로지 인터내셔날
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 시게이트 테크놀로지 인터내셔날 filed Critical 시게이트 테크놀로지 인터내셔날
Priority to KR1020110065089A priority Critical patent/KR20130007295A/en
Publication of KR20130007295A publication Critical patent/KR20130007295A/en

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B19/00—Driving, starting, stopping record carriers not specifically of filamentary or web form, or of supports therefor; Control thereof; Control of operating function ; Driving both disc and head
    • G11B19/20—Driving; Starting; Stopping; Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B2220/00—Record carriers by type
    • G11B2220/20—Disc-shaped record carriers
    • G11B2220/25—Disc-shaped record carriers characterised in that the disc is based on a specific recording technology
    • G11B2220/2508—Magnetic discs
    • G11B2220/2516—Hard disks

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Digital Magnetic Recording (AREA)

Abstract

The hard disk drive is disclosed. The hard disk drive may include a voltage generator for generating a driving voltage according to a voltage code, an analog to digital converter (ADC) for converting the driving voltage into a digital code, and comparing the digital code with a reference code, based on a comparison result. And a CPU for changing the voltage code to correct the driving voltage.

Description

HARD DISK DRIVE, METHOD OF OPERATING THEREOF, AND DATA PROCESSING SYSTEM HAVING THE SAME}

Embodiments of the present disclosure relate to a hard disk drive. In particular, a hard disk drive capable of calibrating a driving voltage for driving each of the components included in the hard disk drive, a method of operating the same, And a data processing system including the same.

A hard disk drive (HDD) is a recording device used for storing information. Typically, information is written to concentric tracks implemented on either side of the magnetic disk. Each driving voltage is required to drive each of the plurality of components included in the HDD.

The voltage generator supplies a respective driving voltage required for each of the plurality of components by using a voltage supplied from an external source. However, due to the voltage offset of the voltage generator, a voltage difference occurs between the driving voltage, which is the output voltage of the voltage generator, and each of the voltages required to drive each of the plurality of components.

The technical problem to be achieved by the present invention is to monitor the driving voltage, which is the output voltage of the voltage generator, a hard disk drive capable of reducing the voltage offset by calibrating the driving voltage according to the monitoring result, an operating method thereof, and It is to provide a data processing system including the same.

According to an embodiment of the present invention, a hard disk drive may include a voltage generator for generating a driving voltage according to a voltage code, an analog to digital converter (ADC) for converting the driving voltage into a digital code, and comparing the digital code with a reference code. And changing the voltage code to adjust the driving voltage according to a comparison result.

The driving voltage may be a voltage for driving one of a read / write channel circuit, a preamplifier, or the CPU.

The voltage generator and the ADC may be implemented on the same chip. The ADC may receive the driving voltage from a voltage supply line implemented outside of the chip.

The voltage supply line may include a dummy resistor. In addition, according to an embodiment, the CPU and the ADC may be implemented on the same chip.

The CPU may change the voltage code when the voltage offset of the voltage generator exceeds one half of the voltage variable unit of the voltage generator. The voltage generator may include a register for storing the voltage code.

In an operating method of a hard disk drive according to an embodiment of the present invention, a voltage generator generates a driving voltage according to a voltage code, an ADC converts the driving voltage into a digital code, and a CPU generates the digital code and a reference code. And comparing and changing the voltage code to adjust the driving voltage according to the comparison result.

Changing the voltage code may change the voltage code stored in a register implemented in the voltage generator.

The method of operating the hard disk drive may further include generating a changed driving voltage according to the changed voltage code of the voltage generator.

A data processing system according to an embodiment of the present invention includes a hard disk drive and a host for controlling the operation of the hard disk drive.

The driving voltage may be a voltage for driving one of a read / write channel circuit, a preamplifier, or the CPU.

The voltage generator and the ADC may be implemented on the same chip. According to an embodiment, the CPU and the ADC may be implemented on the same chip.

The data processing system may be implemented by a computer or a network attached storage (NAS).

Hard disk drive according to an embodiment of the present invention has the effect of improving the accuracy of the driving voltage by reducing the voltage error, that is, the voltage offset (voltage offset) in hardware.

In addition, the hard disk drive according to the embodiment of the present invention has an effect of increasing the voltage margin in which the driving voltage is variable by improving the accuracy of the driving voltage.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to more fully understand the drawings recited in the detailed description of the present invention, a detailed description of each drawing is provided.
1 is a schematic block diagram of a hard disk drive according to an embodiment of the present invention.
FIG. 2 illustrates the voltage generator, analog to digtal converter (ADC), and central processing unit (CPU) shown in FIG. 1 together.
3 illustrates a result of measuring a driving voltage output from the voltage generator illustrated in FIG. 1.
4 shows the result of measuring the voltage offset of the voltage generator shown in FIG.
FIG. 5 illustrates a result of measuring a voltage offset after correcting a driving voltage of the voltage generator shown in FIG. 1.
6 is a flowchart illustrating a method of operating a hard disk drive according to an embodiment of the present invention.
FIG. 7 is a schematic block diagram of a data processing system including the hard disk drive shown in FIG. 1.

Specific structural to functional descriptions of the embodiments according to the inventive concept disclosed herein are merely illustrated for the purpose of describing the embodiments according to the inventive concept. It may be embodied in various forms and should not be construed as limited to the embodiments set forth herein or in the application.

Embodiments in accordance with the concepts of the present invention can make various changes and have various forms, so that specific embodiments are illustrated in the drawings and described in detail in this specification or application. It is to be understood, however, that it is not intended to limit the embodiments according to the concepts of the present invention to the particular forms of disclosure, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Terms such as first and / or second may be used to describe various components, but the components should not be limited by the terms. The terms are intended to distinguish one element from another, for example, without departing from the scope of the invention in accordance with the concepts of the present invention, the first element may be termed the second element, The second component may also be referred to as a first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, the terms "comprises ", or" having ", or the like, specify that there is a stated feature, number, step, operation, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and are not construed in ideal or excessively formal meanings unless expressly defined herein. Do not.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings.

1 is a schematic block diagram of a hard disk drive according to an embodiment of the present invention.

Referring to FIG. 1, a hard disk drive (HDD) 100 may include a plurality of hard disks 10, a plurality of heads 12, a head assembly 14, which are a plurality of magnetic recording media. ), Preamplifier (16), circuit block (18), driver block (or servo control block; 30), spindle motor (38), voice coil motor (40) And an analog to digital converter (ADC) 42.

Each of the plurality of hard disks 10 can store data and is rotated by the spindle motor 38. Each of the plurality of heads 12 is positioned above the corresponding hard disk among the plurality of hard disks 10 to perform a read operation or a write operation, and the voice coil motor 40 A plurality of support arms extending from the head assembly 14 coupled to the plurality of hard disks 10.

When reading data stored in the plurality of hard disks 10, the preamplifier 16 amplifies the read signal output from any one of the plurality of heads 12, and reads the amplified read signal. Output to a write channel circuit (read / write channel circuit) 20.

When writing data to the plurality of hard disks 10, the preamplifier 16 outputs a write signal output from the read / write channel circuit 20, for example, a write current of any one of the plurality of heads 12. To the head. Therefore, the head may write the write signal to any one of the plurality of hard disks 10.

The read / write channel circuit 20 converts the read signal amplified by the preamplifier 16 into read data RDATA, and converts the read data RDATA into a hard disk controller (HDC) 22. Output In addition, the read / write channel circuit 20 converts the write data WDATA output from the hard disk controller 22 into a write signal, and outputs the write signal to the preamplifier 16.

When writing data to the hard disk, the hard disk controller 22 outputs write data output from the host to the read / write channel circuit 20 under the control of the CPU 24. Thus, the write data output from the host can be written to any one of the plurality of hard disks 10 through the read / write channel circuit 20, the preamplifier 16, and the corresponding head. have.

When reading data from the hard disk, the hard disk controller 22 receives the read data RDATA decoded by the read / write channel circuit 20 under the control of the CPU 24 and interfaces the received read data. It can be transmitted to the host through.

The CPU 24 reads a control code or a boot code stored in a read only memory (ROM) 26 and stores it in a random access memory (RAM) 28, and stores the control code or a stored code in the RAM 28. Based on the boot code, the overall operation of the hard disk drive 100 or the hard disk controller 22 may be controlled. Therefore, the CPU 24 may control the read operation or the write operation of the hard disk drive 100.

The CPU 24 receives a read command or a write command output from the host through each interface connected to a bus, and controls track seek or track following according to the received command. It is possible to control the operation of the servo controller capable of controlling the spindle motor driver 32 and the VCM driver 34.

The spindle motor driver 32 controls the operation of the spindle motor 38 that controls the rotation of the plurality of hard disks 10 in response to a control signal output from the hard disk controller 22.

The VCM driver 34 generates a driving current for driving the voice coil motor 40 in response to a control signal for position control of each of the plurality of heads 12 output from the hard disk controller 22. Output to the voice coil of the voice coil motor 40.

Accordingly, the voice coil motor 40 may include a hard disk in which data to be read out of the plurality of heads 12 from among the plurality of hard disks 10 is recorded according to the direction and level of the driving current output from the VCM driver 34. Move up a track embodied on the disc. The head moved by the voice coil motor 40 transfers the control signal output from the read / write channel circuit 20 or the position information recorded on the hard disk to the preamplifier 16 under the control of the hard disk controller 22. Output

When the head moves to the target track of the hard disk to be read, the disk formatter (not shown) of the hard disk controller 22 outputs a servo gate signal to the read / write channel circuit 20.

The read / write channel circuit 20 reads a servo pattern recorded on each of the plurality of hard disks 10 in response to the servo gate signal.

The voltage generator 36 receives an external input voltage, such as 12V or 5V, to generate a driving voltage VDD for driving the read / write channel circuit 20. The voltage generator 36 may further include a register 37 for storing the voltage code. The voltage generator 36 generates a driving voltage VDD according to the voltage code. That is, the voltage code includes voltage level information necessary for driving the read / write channel circuit 20.

The voltage generator 36 may generate the driving voltage by a switching method or a linear method.

According to an embodiment, the voltage generator 36 may generate a driving voltage for driving the preamplifier 16 or the CPU 24.

The ADC 42 converts the output voltage of the voltage generator 36, that is, the driving voltage VDD supplied to the read / write channel circuit 20 into a digital code.

In FIG. 1, an example in which the ADC 42 is implemented outside of the voltage generator 36 is illustrated, but according to the embodiment, the ADC 42 and the voltage generator 36 may be implemented in the same chip. In this case, the ADC 42 may receive the voltage from a voltage supply line implemented outside of the chip. The voltage supply line may include a dummy resistor. Whether the dummy resistor is utilized may be determined in software or hardware. When a problem occurs in current distribution in the hard disk drive 100 or when a problem occurs due to sink current, the problem may be solved by utilizing the dummy resistor. The resistance value of the dummy resistor may be 0 ohm.

Also, according to another embodiment, the ADC 42 and the CPU 24 may be implemented on the same chip.

The CPU 24 may receive the digital code output from the ADC 42, compare the digital code with the reference code, and change the voltage code to adjust the driving voltage VDD according to the comparison result. That is, the CPU 24 may adjust the driving voltage by setting the voltage code stored in the register 37 included in the voltage generator 36 to a new value or a change. The reference code may be stored in hardware or software in the CPU 24, and may be any one of a plurality of reference codes.

The buffer memory 29 may temporarily store data exchanged between the hard disk drive 100 and the host. According to an embodiment, the buffer memory 29 may be implemented outside the circuit block 18.

According to an embodiment, the circuit block 18 including the read / write channel circuit 20, the hard disk controller 22, the CPU 24, the ROM 26, and the RAM 28 may be one chip, for example. It may be implemented as a system on chip (SoC).

In addition, the driver block 30 including the spindle motor driver 32, the VCM driver 34, and the voltage generator 36 may be implemented as one chip, for example, an SoC.

FIG. 2 illustrates the voltage generator, ADC, and CPU shown in FIG. 1 together.

As described above, the ADC 42 may be implemented between the voltage generator 36 and the CPU 24, may be implemented together on a chip in which the voltage generator 36 is implemented, and the CPU 24 is also implemented. Can be implemented together on a chip.

1 and 2, the voltage generator 36 generates the driving voltage VDD according to the voltage code CCODE stored in the register 37. As a specific example, the voltage generator 36 may output the driving voltage VDD in a variable unit of 25 mV within a voltage range of 0.8V to 1.475V. That is, the voltage generator 36 may output a driving voltage having any one of 29 level values from 0.8V to 1.475V.

The ADC 42 converts the driving voltage VDD into a digital code DCODE and outputs the digital code DCODE. The CPU 24 changes the voltage code CCODE to compare the digital code DCODE with the reference code and correct the driving voltage according to the comparison result. The new voltage code CCODE is stored in the register 37, and the voltage generator 36 generates a driving voltage VDD corresponding to the new voltage code CCODE.

3 illustrates a result of measuring a driving voltage output from the voltage generator illustrated in FIG. 1. 3 is a value obtained by converting the driving voltage VDD into a digital code DCODE, that is, an output value of the ADC 42. 3 is a voltage value corresponding to the digital code DCODE.

Referring to FIG. 3, an error exists between the output voltage of the voltage generator 36, that is, the driving voltage VDD and the voltage corresponding to the target voltage VT of the voltage generator 36, that is, the voltage code CCODE. . As shown in FIG. 3, the voltage generator 36 outputs a driving voltage VDD that is 23 mV on average higher than the target voltage VT. In this case, the difference between the driving voltage VDD and the target voltage VT is referred to as a voltage offset.

4 shows the result of measuring the voltage offset of the voltage generator shown in FIG. 4 is the target voltage VT of the voltage generator 36, and the vertical axis is the voltage offset of the voltage generator 36.

Referring to FIG. 4, if the voltage offset is higher than 1/2 of the variable unit (eg, 23 mV) of the voltage generator 36, for example, 12.5 mV, the target voltage VT of the voltage generator 36 may be changed. The voltage offset can be reduced. Therefore, the value of the voltage offset can be reduced to 12.5mV or less.

Table 1 shows the result of measuring the voltage offset before and after correcting the driving voltage of the voltage generator 36 shown in FIG.

VT DCODE [dec] VDD D1 VDD ' D2 0.800 208 0.817 0.017 0.792 -0.008 0.825 214 0.847 0.022 1.817 -0.008 0.850 221 0.873 0.023 0.847 -0.003 0.875 228 0.899 0.024 0.873 -0.002 0.900 234 0.925 0.024 0.899 -0.001 0.925 241 0.950 0.025 0.925 0.000 0.950 247 0.976 0.026 0.950 0.000 0.975 254 1.001 0.026 0.976 0.001 1,000 261 1.026 0.026 1.001 0.001 1.025 267 1.054 0.029 1.026 0.001 1.050 274 1.080 0.030 1.054 0.004 1.075 281 1.104 0.029 1.080 0.005 1.100 287 1.129 0.029 1.104 0.004 1.125 294 1.152 0.027 1.129 0.004 1.150 300 1.178 0.028 1.152 0.002 1.175 306 1.203 0.028 1.178 0.003 1.200 313 1.227 0.027 1.203 0.003 1.225 320 1.251 0.026 1.227 0.002 1.250 326 1.274 0.024 1.251 0.001 1.275 333 1.297 0.022 1.274 -0.001 1.300 339 1.318 0.018 1.297 -0.003 1.325 346 1.341 0.016 1.318 -0.007 1.350 353 1.365 0.015 1.341 -0.009 1.375 359 1.390 0.015 1.365 -0.010 1.400 366 1.416 0.016 1.390 -0.010 1.425 372 1.439 0.014 1.416 -0.009 1.450 379 1.461 0.011 1.439 -0.011 1.475 385 1.483 0.008 1.461 -0.014

Referring to Table 1, when the target voltage VT of the voltage generator 36 is 0.800V, the voltage generator 36 outputs a driving voltage VDD of 0.817V.

The ADC 42 converts the driving voltage VDD into a digital code DCODE and outputs the digital code DCODE. At this time, the digital code DCODE has a value of 208 [dec]. The CPU 24 may change the voltage code CCODE to compare the digital code DCODE with the reference code and to correct the driving voltage VDD according to the comparison result.

The reference code is a value corresponding to the target voltage VT, and may be a value converted to the same dimension as the digital code CODE for comparison with the digital code DCODE. The reference code may be stored in a table in a nonvolatile memory device such as a read only memory (ROM) 26.

As a result, the CPU 24 compares the value of the target voltage VT with the value of the driving voltage VDD, so that the difference between the value of the target voltage VT and the value of the driving voltage VDD, that is, the voltage offset D1. ) Is calculated. At this time, the voltage offset D1 has a value of 0.017.

The CPU 24 may then compare the voltage offset D1 with the voltage variable unit of the voltage generator 36. When the magnitude of the voltage offset D1 is larger than ½ of the voltage variable unit, the CPU 24 may modify the voltage code CCODE according to the value of the voltage offset D1. When the magnitude of the value of the voltage offset D1 is less than or equal to ½ of the voltage variable unit, the CPU 24 may not change the voltage code CCODE.

Since the value of the voltage offset D1 is larger than 12.5 mV corresponding to ½ of the voltage variable unit, the CPU 24 changes the voltage code CCODE such that the target voltage VT is 0.775 V, and the voltage generator ( 36 may output a driving voltage VDD ′ corresponding to 0.792V according to the changed voltage code CCODE.

As a result, by changing the target voltage VT, it is possible to reduce the voltage difference between the output voltage of the voltage generator 36 and the voltage required to drive the read / write channel circuit 20. The voltage offset D2 after the correction is -0.008, which has a reduced value compared to the voltage offset D1 before the correction.

According to an embodiment, the CPU 24 may convert the digital code DCODE into a voltage value and then compare the converted voltage value with the target voltage VT. That is, the CPU 24 may compare the target voltage VT and the driving voltage VDD and change the voltage code CCODE according to the comparison result. At this time, the CPU 24 converts the digital code (DCODE) to the voltage value using a linear function, or uses the table containing data on the voltage value corresponding to the digital code (DCODE). ) Can be converted into the voltage value.

When the target voltage VT of the voltage generator 36 is 0.825V, the voltage generator 36 outputs a driving voltage VDD corresponding to 0.847V. The ADC 42 converts the driving voltage VDD into a digital code DCODE and outputs it. At this time, the digital code DCODE has a value of 214 [dec]. The CPU 24 may change the voltage code CCODE to compare the digital code DCODE with the reference code and to adjust the driving voltage VDD according to the comparison result.

The CPU 24 calculates the voltage offset D1 by comparing the value of the target voltage VT with the value of the driving voltage VDD. At this time, the voltage offset D1 has a value of 0.022. The CPU 24 may then compare the voltage offset unit D1 with the voltage variable unit of the voltage generator 36.

Since the value of the voltage offset D1 is larger than 12.5 mV, the CPU 24 changes the voltage code CCODE such that the target voltage VT is 0.800 V, and the voltage generator 36 changes the changed voltage code CCODE. Accordingly, the driving voltage VDD ′ corresponding to 0.817V may be output. At this time, the voltage offset D2 after correction is −0.008, which is a value lower than the voltage offset D1 before correction.

When the value of the target voltage VT is 0.850V to 1.475V, the driving voltage VDD may be corrected in the same manner as described above, and the description thereof is omitted.

In addition, the hard disk drive 100 according to an embodiment of the present invention may correct the driving voltage of the entire section based on the voltage offset measured only for the specific driving voltage of the voltage generator 36.

FIG. 5 illustrates a result of measuring a voltage offset after correcting a driving voltage of the voltage generator shown in FIG. 1.

1 and 5, the voltage offset in all sections has a value of 12.5 mV or less. That is, the driving voltage VDD output from the voltage generator 36 may be corrected such that the voltage offset has a value of ½ or less of a variable unit of the voltage generator 36.

6 is a flowchart illustrating a method of operating a hard disk drive according to an embodiment of the present invention.

1 and 6, the voltage generator 36 generates the driving voltage VDD according to the voltage code CCODE (S10). For example, when the magnitude of the voltage required to drive the read / write channel circuit 20, that is, the target voltage of the voltage generator 36 is 1.2V, the voltage generator 36 is driven according to the voltage code CCODE. VDD). In this case, the driving voltage VDD may be different from the target voltage due to the voltage offset of the voltage generator 36.

The ADC 42 converts the driving voltage VDD into a digital code DCODE (S30). This conversion is for measuring the magnitude of the driving voltage VDD.

The CPU 24 compares the digital code DCODE with the reference code, and changes the voltage code CCODE to adjust the driving voltage VDD according to the comparison result (S50). That is, the CPU 24 may change or set the voltage code CCODE stored in the register 37 included in the voltage generator 36.

As shown in Table 1, the voltage generator 36 generates the changed driving voltage VDD 'according to the changed voltage code CCODE (S70). As the voltage code CCODE is changed, the target voltage VT of the voltage generator 36 is also changed to 1.175V. At this time, the voltage generator 36 outputs a driving voltage VDD 'corresponding to 1.203V. Therefore, the difference with the voltage required to drive the read / write channel circuit 20 can be reduced.

As a result, the CPU 24 may change the driving voltage VDD by changing the voltage code CCODE stored in the register 37 included in the voltage generator 36.

In addition, the CPU 24 may store the correction result of the driving voltage VDD in a memory (not shown). The memory may be a nonvolatile memory. Therefore, the CPU 24 may control the operation of the voltage generator 36 to correct the driving voltage VDD without performing a measurement process using the correction result stored in the memory.

FIG. 7 is a schematic block diagram of a data processing system including the hard disk drive shown in FIG. 1.

The data processing system 200 includes a hard disk drive 100 and a hard disk drive 100 and a host 210 for giving or receiving data. The data processing system 200 may be implemented as a computer or a network attached storage (NAS).

1 and 7, the hard disk drive 100 includes a plurality of hard disks 10, a plurality of heads 12, a head assembly 14, a preamplifier 16, which are a plurality of magnetic recording media. , Circuit block 18, driver block 30, spindle motor 38, voice coil motor 40, and ADC 42. Descriptions overlapping with the hard disk drive 100 shown in FIG. 1 will be omitted.

The host 210 includes a host CPU 211, a memory 213, and an interface 214. The host CPU 24 controls the operation of the host 210, and in the write operation, the data output from the memory 213 is implemented in the circuit block 18 of the hard disk drive 100 through the interface 214. Transmit to host interface 49. The interface 214 and the host interface 49 may be implemented as SATA interfaces. Accordingly, the interface 214 and the host interface 49 may transmit or receive data using the SATA protocol.

In the read operation, the interface 214 may store data transmitted from the host interface 49 implemented in the circuit block 18 of the hard disk drive 100 in the memory 213 under the control of the host CPU 211. . The host CPU 211 may process data stored in the memory 213, for example, display it using a display device, or output the data using a printer connected to a peripheral device, for example, a USB port.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

10: multiple disks 12: multiple heads
14 head assembly 16 preamplifier
18: circuit block 20: lead / write channel circuit
22: hard disk controller 24: CPU
26: ROM 28: RAM
29: buffer memory 30: driver block
32: spindle motor drive unit 34: VCM drive unit
36: voltage generator 37: resistor
38: spindle motor 40: voice coil motor
42: ADC 49: host interface
100: hard disk drive 200: data processing system
210: host 211: host CPU
213: memory 214: interface

Claims (10)

A voltage generator for generating a driving voltage in accordance with the voltage code;
An analog to digital converter (ADC) for converting the driving voltage into a digital code; And
And a CPU for comparing the digital code with a reference code and changing the voltage code to correct the driving voltage according to the comparison result. The method of claim 1,
And the drive voltage is a voltage for driving one of the read / write channel circuit, the preamplifier, or the CPU. The method of claim 1,
The voltage generator and the ADC are implemented on the same chip. The method of claim 3,
And the ADC receives the driving voltage from a voltage supply line implemented outside of the chip. The method of claim 1,
The CPU and the ADC are implemented on the same chip. The method of claim 1,
And the CPU changes the voltage code when the voltage offset of the voltage generator exceeds one half of the voltage variable unit of the voltage generator. The method of claim 1,
And the voltage generator includes a register for storing the voltage code. The voltage generator generating a driving voltage according to the voltage code;
Converting the driving voltage into a digital code by an ADC; And
A CPU comparing the digital code with a reference code, and changing the voltage code to correct the driving voltage according to the comparison result. The method of claim 8, wherein changing the voltage code comprises:
And operating the voltage code stored in a register implemented in the voltage generator. The method of claim 8, wherein the operating method of the hard disk drive comprises:
And generating a changed driving voltage according to the changed voltage code by the voltage generator.
KR1020110065089A 2011-06-30 2011-06-30 Hard disk drive, method of operating thereof, and data processing system having the same KR20130007295A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020110065089A KR20130007295A (en) 2011-06-30 2011-06-30 Hard disk drive, method of operating thereof, and data processing system having the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020110065089A KR20130007295A (en) 2011-06-30 2011-06-30 Hard disk drive, method of operating thereof, and data processing system having the same

Publications (1)

Publication Number Publication Date
KR20130007295A true KR20130007295A (en) 2013-01-18

Family

ID=47837891

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020110065089A KR20130007295A (en) 2011-06-30 2011-06-30 Hard disk drive, method of operating thereof, and data processing system having the same

Country Status (1)

Country Link
KR (1) KR20130007295A (en)

Similar Documents

Publication Publication Date Title
US8730602B2 (en) Method and apparatus for detecting touch-down and contact between a head and a storage medium using a sensor, and a disk drive and storage medium using the method
US7224135B1 (en) Imposed current motor drive
US7633696B2 (en) Fly height calibration for read/write heads
US7706096B2 (en) Disk drive device manufacturing method thereof, and method for specifying data track pitch for the disk drive device
US20080186617A1 (en) Disk drive device and method for error recovery procedure therefor
US8941937B1 (en) Addressing insufficient bit error rates amongst segments
US20180174615A1 (en) Storage device and a method for defect scanning of the same
KR102295395B1 (en) Semiconductor integrated circuit and operating method for the same
US10657987B1 (en) Laser boost and duration optimization
US20120154947A1 (en) Method of controlling defects and apparatuses using the same
US7933086B2 (en) Power supply voltage supply circuit and disk apparatus
JP2015022778A (en) Magnetic disk device and writing method for magnetic disk
KR20130007295A (en) Hard disk drive, method of operating thereof, and data processing system having the same
KR100855981B1 (en) Write factor setting method and disk drive separately setting write factor for each of the plurality of heads
JP2011076707A (en) Method of setting zone layout of recording medium, data recording apparatus, disk drive, and recording medium
KR20110048726A (en) Method for managing defect and apparatuses using same
US20110188147A1 (en) Method adjusting gain of variable gain amplifier and apparatus using same
JP2010153005A (en) Power source voltage regulator circuit and information storage device
US11249450B1 (en) Calibration of multi-stage servo system
JPH05335953A (en) A/d converter
US11862202B2 (en) Data storage device with smart ISOFET threshold voltage automatic tuning
US20100226032A1 (en) Control device, magnetic disk device, and iw sensitivity calculating method
US10686427B1 (en) Reconfigurable analog filter with offset compensation
US20170221512A1 (en) Hard disk drive, manufacturing method of the same, and servo data writing method
US11769525B1 (en) Seek-induced vibration compensation

Legal Events

Date Code Title Description
N231 Notification of change of applicant
WITN Withdrawal due to no request for examination