KR20120069457A - Substrate for organic electro luminescent device and method of fabricating the same - Google Patents

Abstract

PURPOSE: A substrate for an organic electroluminescent device and a manufacturing method thereof are provided to improve the capacitance of a storage capacitor per unit area by making a plurality of storage capacitors overlap each other. CONSTITUTION: A source electrode(133) and a drain electrode(136) are formed on an interlayer dielectric layer. A third storage electrode(134) corresponds to the first storage electrode. A first protection layer(138) is formed on the source electrode, the drain electrode, and the third storage electrode. A first electrode(147) in contact with the drain electrode is formed on a first protection layer. A bank(155) with a first height and a spacer(160) are formed in a boundary of each pixel area on the first electrode.

Description

Substrate for organic electroluminescent device and method of fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate for an organic light emitting device, and more particularly, to an array substrate for an organic light emitting device and a method of manufacturing the same, including a thin film transistor including polysilicon as a semiconductor layer and simplifying a manufacturing process and improving off current characteristics. .

In recent years, as the society enters the information age, the display field that processes and displays a large amount of information has been rapidly developed, and recently, a flat panel display device having excellent performance of thinning, light weight, and low power consumption has recently been developed. It is proposed.

Among them, organic light emitting diodes have high brightness and low operating voltage characteristics, and because they emit light by themselves, they have a high contrast ratio, enable ultra-thin displays, and have a response time of several microseconds ( ㎲) It is stable for moving picture.

In addition, the organic light emitting diode is not limited in viewing angle and stable at low temperatures, and is driven at a low voltage of DC 5 to 15V, thus facilitating the fabrication and design of a driving circuit, and the deposition and encapsulation equipment. It can be said that the manufacturing process is very simple.

Due to these advantages, organic light emitting diodes are attracting the most attention as next generation flat panel display devices.

In such an organic light emitting device, an array substrate including a thin film transistor is essentially provided to turn off / on each pixel area.

In this case, in the case of an array substrate for an organic light emitting device, a thin film transistor including polysilicon having excellent mobility characteristics as a semiconductor layer is provided for device stability.

In order to manufacture an array substrate for an organic light emitting device having a thin film transistor using a conventional polysilicon as a semiconductor layer, a mask process is generally performed ten times.

That is, in the conventional array substrate for an organic light emitting device having a thin film transistor having polysilicon as a semiconductor layer, the semiconductor layer formation / first storage electrode formation / gate electrode formation / semiconductor of polysilicon until the organic light emitting layer is formed A total of 10 mask processes are carried out: forming an interlayer insulating film having a layer contact hole, forming a source and drain electrode, forming a first protective layer of an inorganic film, forming a second protective layer of an organic film, forming an anode electrode, forming a bank, and forming a spacer. It is true.

A mask process means a photolithography process, and after forming a material layer for patterning on a substrate, forming a photoresist layer having photosensitive characteristics thereon, and using an exposure mask having a light transmitting region and a blocking region. A series of complex unit processes, such as exposure, development of the exposed photoresist layer, etching of the material layer using the developed photoresist pattern, stripping of the photoresist pattern, and the like.

In order to process a single mask process, a unit process equipment for each unit process and a material for each unit process are required, and further, each process process time through each unit process equipment is required.

Therefore, each manufacturer of the organic light emitting device is trying to reduce the mask process in order to reduce the manufacturing cost and productivity of the array substrate.

On the other hand, in the conventional organic light emitting device substrate, the use of polysilicon semiconductor layers is excellent in mobility characteristics, but the leakage current at the boundary between the active layer made of pure polysilicon and the doped portion of impurities is increased. There is a problem that current characteristics are deteriorated.

The present invention has been made to solve the above-described problem, the present invention has a thin film transistor with a polysilicon semiconductor layer, while reducing the number of mask processes, furthermore, an organic electroluminescence that can improve the off current characteristics It is an object of the present invention to provide an array substrate for a device and a method of manufacturing the same.

In order to achieve the above object, in the method of manufacturing a substrate for an organic light emitting diode according to an embodiment of the present invention, a display area and a non-display area are defined outside thereof, and the gate area and the data wire cross each other in the display area. A semiconductor layer of polysilicon is formed in the device region on the substrate in which a pixel region is defined, and a device region in which a thin film transistor is formed in the pixel region and a storage region in which a storage capacitor is formed is formed. Forming a semiconductor pattern; Forming a gate insulating film over the semiconductor layer and the semiconductor pattern; A gate electrode having a multi-layer structure formed on the gate insulating layer, the lower layer having a first width corresponding to a central portion of the semiconductor layer and an upper layer having a second width smaller than the first width, and forming a gate electrode; Forming a storage electrode; Impurity doping is performed to form an ohmic contact layer doped with a first dose of impurities corresponding to a portion of the semiconductor layer exposed to the outside of the lower layer of the gate electrode, and the gate electrode exposed to the outside of the upper layer of the gate electrode. The portion corresponding to the lower layer of the to form an LDD layer doped with a second dose of impurities smaller than the first dose, the semiconductor pattern is doped with a second dose of impurities to improve the conductivity of the semiconductor pattern Forming a second storage electrode; Forming an interlayer insulating layer exposing the ohmic contact layer over the gate electrode and the first storage electrode; Forming source and drain electrodes on the interlayer insulating layer, the source and drain electrodes being in contact with the ohmic contact layer and spaced apart from each other, and simultaneously forming a third storage electrode corresponding to the first storage electrode; Forming a first passivation layer exposing the drain electrode over the source and drain electrodes and a third storage electrode; Forming a first electrode in contact with the drain electrode over the protective layer; Forming a bank having a first height at a boundary at each pixel region over the first electrode, and simultaneously forming a spacer having a second height higher than the first height at a boundary of each pixel region; .

In this case, before forming the first passivation layer, forming a second passivation layer exposing the drain electrode over the data line and the source and drain electrodes.

The method may further include forming a bank having a first height at a boundary at each pixel area over the first electrode, and simultaneously forming a spacer having a second height higher than the first height at a boundary of each pixel area. Forming a layer of an organic material by coating a photosensitive organic insulating material on the first electrode; Performing diffraction exposure or halftone exposure on the organic material layer using an exposure mask having a transmission region, a blocking region, and a semi-transmissive region; The bank having the first height is formed at the boundary of each pixel region by developing the diffractive exposure or the halftone exposed organic material layer, and at the same time the selectively having the second height at the boundary of each pixel region. Forming a spacer.

The method may further include forming a bank having a first height at a boundary at each pixel area over the first electrode, and simultaneously forming a spacer having a second height higher than the first height at a boundary of each pixel area. The method may include forming a first organic material layer by applying a photosensitive first organic insulating material on the first electrode; Patterning the first organic material layer to form the bank having the first height at a boundary of each pixel region; Applying a second organic insulating material over the bank to form a second organic material layer; Patterning the second organic material layer to form the spacers having the second height selectively on the banks positioned at the boundaries of each pixel region.

Forming a semiconductor layer of polysilicon in the device region, and forming a semiconductor pattern of polysilicon in the storage region, forming an amorphous silicon layer on the substrate; Crystallizing the amorphous silicon layer with a polysilicon layer; Patterning the polysilicon layer.

In addition, a gate electrode having a multilayer structure including a lower layer having a first width corresponding to a center portion of the semiconductor layer and an upper layer having a second width smaller than the first width is formed on the gate insulating layer, and corresponds to the semiconductor pattern. The first storage electrode may be formed by forming a transparent conductive material layer and a metal material layer on the gate insulating layer; Forming a first photoresist pattern having a first thickness corresponding to the storage area on the metal material layer, and forming a second photoresist pattern having a second thickness thicker than the first thickness in the device area; The first storage sequentially stacked in the storage area by sequentially removing the metal material layer and the transparent conductive material layer exposed to the outside of the first and second photoresist patterns by using an etching solution having an etching ratio. Forming a gate electrode and a dummy metal pattern, and forming the gate electrode formed of a transparent conductive material sequentially stacked on the device region, the lower layer having the first width, and the upper layer having a second width and a metal material. Making a step; Exposing the metal dummy pattern by ashing to remove the first photoresist pattern of the first thickness; Removing the metal dummy pattern to expose the first storage electrode; Removing the second photoresist pattern.

The source electrode and the third storage electrode may be connected to each other.

The first protective layer may be formed of an organic insulating material so as to have a flat surface corresponding to the display area.

The forming of the gate electrode may include forming a gate wiring extending in one direction on each of the pixel regions over the gate insulating layer and forming a gate pad electrode at one end of the gate wiring, wherein the source and drain electrodes are formed. The forming step may include forming a data line electrode defining the pixel region and the data pad electrode at one end of the data line crossing the gate line over the interlayer insulating layer, and simultaneously forming a power line in parallel with the data line. Steps.

The forming of the interlayer insulating film may include forming an active contact hole exposing the ohmic contact layer and a gate pad contact hole exposing the gate pad electrode, and forming the first electrode. Forming an auxiliary gate pad electrode on the interlayer insulating layer to contact the gate pad electrode through the gate pad contact hole, and forming an auxiliary data pad electrode covering the data pad electrode.

The forming of the gate electrode may include forming a gate wiring extending in one direction on each of the pixel regions over the gate insulating layer and forming a gate pad electrode at one end of the gate wiring, wherein the source and drain electrodes are formed. The forming step may include forming a data line electrode defining the pixel region and the data pad electrode at one end of the data line crossing the gate line over the interlayer insulating layer, and simultaneously forming a power line in parallel with the data line. The forming of the second passivation layer may include forming a gate pad contact hole exposing the gate pad electrode and a data pad contact hole exposing the data pad electrode.

The forming of the first electrode may include forming an auxiliary gate pad electrode contacting the gate pad electrode through the gate pad contact hole on the second passivation layer, and forming an auxiliary gate pad electrode through the data pad contact hole. Forming an auxiliary data pad electrode in contact.

The method may further include forming a buffer layer on the entire surface of the substrate before forming the semiconductor layer of the polysilicon and the semiconductor pattern on the substrate.

The forming of the first electrode may include forming a lower metal layer by depositing a metal material having excellent reflection efficiency on the first protective layer, and forming an upper conductive layer by depositing a transparent conductive material on the lower metal layer. And forming the first electrode having a double layer structure by successively patterning the upper conductive layer and the lower metal layer, or by forming and patterning a transparent conductive material layer over the first protective layer. Forming the first electrode having a layer structure.

In the substrate for an organic light emitting device according to an exemplary embodiment of the present invention, a display area and a non-display area are defined outside the display area, and a pixel area is defined in the display area by crossing a gate line and a data line, and within the pixel area. A second region in which the device region in which the thin film transistor is formed and the storage region in which the storage capacitor is formed are formed in the device region on the substrate, and doped with a first dose of impurities in both the first region and the first region in the center; A semiconductor layer of polysilicon composed of a third region doped with a second dose of impurities greater than the first dose, and a first storage electrode of impurity polysilicon formed in the storage region, outside the region and the second region; ; A gate insulating film formed over the semiconductor layer and the first storage electrode; A plurality of second storage electrodes formed on the gate insulating layer corresponding to the first storage electrode, a lower layer formed corresponding to the first and second regions of the semiconductor layer of the polysilicon, and an upper layer formed corresponding to the second region; A gate electrode having a layer structure; An interlayer dielectric layer covering the second storage electrode and the gate electrode and exposing the third region of the semiconductor layer, respectively; A source and drain electrode formed on the interlayer insulating layer and in contact with the third region of the semiconductor layer and spaced apart from each other, and a third storage electrode formed to correspond to the second storage electrode; A first passivation layer covering the source and drain electrodes and the third storage electrode and exposing the drain electrode and formed in the display area; A first electrode in contact with the drain electrode over the first passivation layer and formed in each pixel area; A bank overlapping an edge of the first electrode and having a first height and formed at a boundary of each pixel region, and a spacer selectively formed on the bank.

In addition, a second passivation layer formed of an inorganic insulating material in the display area and the non-display area under the first passivation layer and exposing the drain electrode may be provided.

In addition, the second storage electrode and the lower layer of the gate electrode is made of a transparent conductive material, has a thickness of 100 ~ 500Å, the upper layer of the gate electrode is characterized in that made of one or two or more metal materials.

In addition, the first storage electrode, the gate insulating layer, and the second storage electrode constitute a first storage capacitor, and the second storage electrode, the interlayer insulating layer, and the third storage electrode constitute a second storage capacitor. The capacitors are characterized by their parallel structure.

A gate wiring formed at a boundary of each pixel region in the same layer on which the gate electrode is formed; A data line formed on the same layer where the source and drain electrodes are formed to cross the gate line at a boundary of each pixel region; And a power supply wiring formed to be spaced apart from the data wiring.

In addition, a buffer layer may be formed on an entire surface of the substrate under the semiconductor layer and the first storage electrode.

As described above, the substrate for an organic light emitting device having a thin film transistor having a semiconductor layer of polysilicon according to each embodiment of the present invention is characterized in that the mask process is performed a total of nine to seven times before forming the organic light emitting layer By doing so, there is an effect of shortening the mask process once to three times as compared with the related art and further reducing the manufacturing cost.

In addition, in each embodiment of the present invention, a substrate for an organic light emitting diode has a low-dose impurity-doped LDD layer between an active layer of pure polysilicon and a region doped with a high dose amount to generate a leakage current. By suppressing this, there is an effect of improving the off current characteristic.

In addition, the array substrate for an organic light emitting device according to the embodiment of the present invention has an effect of improving the capacity of the storage capacitor per unit area by having a configuration in which a plurality of storage capacitors overlap and are connected in parallel.

1A to 1N are cross-sectional views illustrating manufacturing steps of one pixel region of an array substrate for an organic light emitting diode having a thin film transistor having a semiconductor layer of polysilicon according to a first embodiment of the present invention.
2A through 2B are cross-sectional views illustrating manufacturing steps of one pixel region of an array substrate for an organic light emitting diode having a thin film transistor having a semiconductor layer of polysilicon according to a second embodiment of the present invention.
3 is a cross-sectional view of one pixel area of a substrate for an organic light emitting device having a thin film transistor having a semiconductor layer of polysilicon according to a third embodiment of the present invention.

Hereinafter, a substrate for an organic light emitting diode using polysilicon according to an embodiment of the present invention and a method of manufacturing the same will be described with reference to the accompanying drawings.

1A to 1N are cross-sectional views illustrating manufacturing steps of one pixel area of an array substrate for an organic light emitting diode device having a thin film transistor having a semiconductor layer of polysilicon according to a first embodiment of the present invention.

For convenience of description, the region in which the thin film transistor is formed in each pixel region is defined as an element region DA and the region in which the storage capacitor is formed as a storage region StgA, and a portion where the gate pad electrode is formed is referred to as a gate pad portion. A portion where the data pad electrode (GPA) is formed is defined as a data pad portion DPA.

The thin film transistor Tr formed in the device area DA becomes a driving thin film transistor connected to the organic light emitting diode, and the switching thin film transistor connected to the gate and data lines has the same structure as that of the driving thin film transistor. Did not do it. In the description, the switching and driving thin film transistors are referred to as thin film transistors.

First, as shown in FIG. 1A, a buffer layer 111 is formed by depositing silicon nitride (SiNx) or silicon oxide (SiO ₂ ), which is an inorganic insulating material, on the substrate 110. When the amorphous silicon layer (not shown) is recrystallized from the polysilicon layer 180, the buffer layer 111 may be formed of alkali ions present in the substrate 110 due to heat generated by laser irradiation or heat treatment. For example, potassium ions (K +), sodium ions (Na +), and the like may be generated to prevent degradation of the film characteristics of the semiconductor layer made of polysilicon by such alkali ions. In this case, the buffer layer 111 may be omitted depending on the material of the substrate 110.

Thereafter, amorphous silicon is deposited on the buffer layer 111 to form an amorphous silicon layer (not shown) on the entire surface.

Next, the pure amorphous silicon layer (not shown) is crystallized to form the pure polysilicon layer 180 by performing a crystallization process to improve mobility characteristics of the pure amorphous silicon layer (not shown). In this case, it is preferable that the crystallization process is a crystallization process using solid phase crystallization (SPC) or a laser.

The solid phase crystallization (SPC) process, for example, thermal crystallization (Thermal Crystallization) through heat treatment in an atmosphere of 600 ℃ to 800 ℃ or alternating magnetic field crystallization (Alternating Magnetic in a temperature atmosphere of 600 ℃ to 700 ℃ using an alternating magnetic field crystallization device It is preferable that the field crystallization process, and the crystallization using the laser is preferably an Excimer Laser Annealing (ELA) method or a sequential lateral solidification (SLS) crystallization using an excimer laser.

Next, as illustrated in FIG. 1B, a mask process including applying the polysilicon layer (180 of FIG. 1A) to photoresist, exposing using an exposure mask, developing exposed photoresist, etching, and stripping is performed. By proceeding and patterning, a polysilicon semiconductor layer 113 is formed in the device region DA, and a polysilicon semiconductor pattern 114 is formed in the storage region StgA. In this case, the semiconductor pattern 114 may form a first storage electrode (115 in FIG. 1N) after the dopant is later doped to improve conductivity.

Next, as illustrated in FIG. 1C, an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ) is deposited on the entire surface of the semiconductor pattern 114 and the polysilicon semiconductor layer to form a gate insulating film 116. ).

Thereafter, a transparent conductive material layer having a thickness of about 100 GPa to 500 GPa is deposited by depositing a transparent conductive material, for example, indium tin oxide (ITO) or indium zinc oxide (IZO), on the entire surface of the gate insulating layer 116 ( 182, and subsequently to the transparent conductive material layer 182, a low resistance metal material such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo), mol One or more materials of titanium (MoTi) are deposited to form a gate metal layer 184 having a single layer or a multilayer structure. In the drawing, the gate metal layer 184 having a single layer structure is formed.

Next, as shown in FIG. 1D, a photoresist layer (not shown) is formed by applying photoresist onto the gate metal layer 184, a light transmitting region and a blocking region over the photoresist layer (not shown), and An exposure mask (not shown) having a transflective area capable of adjusting the amount of light transmitted is positioned, and exposure is performed through the exposure mask (not shown).

In this case, the light passing through the transflective region is, for example, in the case of an exposure mask (not shown) in which the transflective region is configured in a slit form to diffract the light exposed by the slit, or to provide a multilayer coating film. In this case, the amount of light is controlled by the multilayer coating film.

Accordingly, light reaches the entire surface of the photoresist layer (not shown) corresponding to the transflective area on the exposure mask (not shown), but is smaller than the intensity or amount of light passing through the transmission area.

When the photoresist layer (not shown) exposed through the exposure mask is developed, the first photoresist pattern 191a having a first thickness is formed in a portion corresponding to the transmission region of the exposure mask (not shown). The second photoresist pattern 191b having a second thickness thinner than the first thickness is formed in a portion corresponding to the transflective area of the exposure mask (not shown), and the blocking of the exposure mask (not shown). All portions corresponding to the regions are removed to expose the gate metal layer 184 of FIG. 1C.

Accordingly, the second photoresist pattern 191b having a second thickness is formed in the storage area StgA corresponding to the reflective transmission area of the exposure mask (not shown), and the transmission area of the exposure mask (not shown). The first photoresist pattern 191a having a first thickness is formed to correspond to a central portion of the semiconductor layer 113 of polysilicon in the device region DA corresponding to.

Next, the gate metal layer 184 of FIG. 1D and the transparent conductive material layer 182 of FIG. 1D and the lower portion exposed to the outside of the first and second photoresist patterns 191a and 191b are sequentially etched and removed. In the device area DA, a lower layer 120a made of a transparent conductive material and a low resistance metal material are sequentially stacked on the gate insulating layer 116 to correspond to a central portion of the semiconductor layer 113 of the polysilicon. A gate electrode 120 having a multilayer structure having an upper layer 120b is formed, and at the same time, in the storage area StgA, a second storage electrode 118 made of a transparent conductive material and a dummy metal pattern 119 are sequentially formed. do.

Although not shown in the drawing, a gate wiring (not shown) having a multi-layer structure is formed on the gate insulating layer 116 and extends in one direction on the boundary of each pixel region P. Referring to FIG. In this case, the gate line (not shown) is formed to be connected to the gate electrode 120 of the switching thin film transistor (not shown).

In the gate pad part GPA, a gate pad electrode 121 is formed on the gate insulating layer 116 to be connected to one end of the gate line 120. In this case, the gate pad electrode 121 also has the same multilayer structure as the gate electrode 120.

Meanwhile, the etching of the gate metal layer 184 of FIG. 1C and the transparent conductive material layer 182 of FIG. 1C exposed to the outside of the first and second photoresist patterns 191a and 191b may be performed by wet etching using an etchant. desirable. In this case, the etching ratio of the gate metal layer 184 of FIG. 1C is greater than that of the transparent conductive material layer 182 of FIG. 1C, thereby finally using the gate metal layer 184 of FIG. 1C and the transparent conductive material layer. When the etching of the gate metal layer (184 of FIG. 1C) is completed, overetching is performed on the gate metal layer (184 of FIG. 1C), so that the gate wiring (not shown) having the multilayer structure, the gate electrode 120, and the gate pad electrode ( 121 is characterized in that each upper layer (not shown, 120b, 121b) is formed having a width smaller than the width of the lower layer (not shown, 120b, 121b).

The reason why the gate metal layer 184 (FIG. 1C) is overetched so that both ends of the lower layer 120a are exposed to the outside of the upper layer 120b in the gate electrode 120 may be due to impurities that are subsequently processed. This is to form a region having a different dose in the doped semiconductor layer 113 at the time of doping.

Next, as shown in FIG. 1E, ashing is performed to remove the second photoresist pattern (191b of FIG. 1D) having the second thickness, thereby removing the metal dummy pattern () in the storage area StgA. 119).

In this case, the thickness of the first photoresist pattern 191a having the first thickness also decreases due to ashing, but still remains on the gate electrode 120 and the gate wiring (not shown). .

Next, as shown in FIG. 1F, the second photoresist pattern (191b of FIG. 1D) is removed, thereby removing the newly exposed metal dummy pattern (119 of FIG. 1E), thereby being transparent in the storage area StgA. The second storage electrode 118 made of a conductive material is exposed.

Next, as shown in FIG. 1G, a strip is removed to remove the first photoresist pattern 191a of FIG. 1F, thereby forming a multi-layered gate electrode 120, a gate wiring (not shown), and a gate. The pad electrode 121 is exposed.

Subsequently, in the state where the gate electrode 120, the gate wiring (not shown), and the gate pad electrode 121 of the multilayer structure are formed, the gate electrode 120 more precisely, the upper layer of the gate electrode is used as a doping blocking mask. Doping of any one of a type impurity such as boron (B), indium (In), gallium (Ga) or an n type impurity such as phosphorus (P), arsenic (As) or antimony (Sb) .

In the figure, the p-type impurity is shown as an example.

On the other hand, the doping of such impurities in the storage region (StgA) is doped with impurities having a first dose to the semiconductor pattern of the polysilicon (114 in Fig. 1h) to improve the conductivity characteristics to serve as an electrode By doing so, the first storage electrode 115 is formed.

Although the second storage electrode 118 made of a transparent conductive material is formed in the storage area StgA, the second storage electrode 118 made of the transparent conductive material has a thickness of about 100 kPa to 500 kPa, and thus doping impurities. Since the impurity ions can penetrate the second storage electrode 118 to reach the inside of the polysilicon semiconductor pattern 114 of FIG.

In the device area DA, dopants may be doped only with respect to the semiconductor layer 113 of polysilicon in a portion exposed to the outside of the upper layer 120b of the gate electrode 120 when the dopant is doped. . In this case, the portion overlapping the lower layer 120a of the gate electrode 120 by the lower layer 120a of the gate electrode 120 is the same in which impurities are doped in the semiconductor pattern (114 in FIG. 1H) of the polysilicon. In other words, the LDD region 113c is formed by doping the impurities having the level, that is, the first dose.

In addition, since the lower layer 120a of the gate electrode 120 is not formed in the portion of the semiconductor layer 113 of the polysilicon located outside the LDD region 113c, there is no doping obstacle, so An impurity having a large second dose is doped to form the ohmic contact layer 113b. The central part of the semiconductor layer 113 of the polysilicon semiconductor layer 113 is doped with impurities by the upper layer 120b of the gate electrode 120, thereby achieving a pure polysilicon state.

Therefore, when the doping of the impurities is completed, the semiconductor layer 113 of the polysilicon formed in the device region DA may have an active layer 113a made of pure polysilicon and doped with a first dose of impurities on both sides thereof. The LDD layer 113c and the ohmic contact layer 113b doped with an impurity of a second dose larger than the first dose is formed outside the LDD layer 113c and the respective LDD layers 113c.

In the polysilicon semiconductor layer 113 having such a configuration, the ohmic contact layer 113b doped with the second dose of impurities has the highest conductivity because of low internal resistance, and then the LDD layer 113c The active layer 113a has the smallest conductivity.

Meanwhile, the first storage electrode 115, the gate insulating layer 116, and the second storage electrode 118 having improved conductivity by doping impurities in the storage region StgA form a first storage capacitor StgC1.

Next, as shown in FIG. 1H, silicon oxide (SiO ₂ ), which is an inorganic insulating material, is formed on the entire surface of the gate electrode 120, the gate wiring (not shown), the gate pad electrode 121, and the second storage electrode 118. Or an interlayer insulating film 123 is formed by depositing silicon nitride (SiNx).

Subsequently, a mask process is performed on the interlayer insulating layer 123 and patterned together with the gate insulating layer 116 to expose the ohmic contact layer 113b of the semiconductor layer 113, respectively. To form.

Next, as illustrated in FIG. 1I, a metal material, for example, aluminum (Al), aluminum alloy (AlNd), copper (Cu), or copper, may be formed on the entire surface of the interlayer insulating layer 123 on which the semiconductor layer contact hole 125 is formed. A second metal layer (not shown) is formed by depositing any one or two or more of an alloy, molybdenum (Mo), and molybdenum (MoTi).

Subsequently, the second metal layer (not shown) is patterned by performing a mask process so as to intersect the gate line (not shown) at the boundary of the pixel region P to define the pixel area P (not shown). At the same time, power wirings (not shown) are formed parallel to the data lines (not shown). In this case, a data pad electrode 127 connected to one end of the data line (not shown) is formed in the data pad part DPA.

At the same time, source and drain electrodes 133 and 136 are formed in the device area DA to contact the ohmic contact layer 113b and to be spaced apart from each other through the semiconductor layer contact hole 125. In this case, the source electrode 133 is formed to extend to the storage region StgA to form the third storage electrode 134.

In this configuration, the second storage electrode 118, the interlayer insulating layer 123, and the third storage electrode 134 form a second storage capacitor StgC2 in the storage region StgA.

In this case, the first and second storage capacitors StgC1 and StgC2 form a structure in which the first and second storage capacitors StgC1 and StgC2 are connected in parallel to each other through the second storage electrode 118, thereby increasing the total storage capacitor capacity.

Next, as shown in FIG. 1J, an inorganic insulating material is deposited on the entire surface of the source and drain electrodes 133 and 136, the data line (not shown), the power line (not shown), and the third storage electrode 134. To form the first protective layer 138.

Subsequently, the first protective layer 138 and the interlayer insulating layer 123 thereunder are patterned by a mask process, so that the drain contact hole 143 exposing the drain electrode 136 is exposed in the device area DA. Form.

At the same time, a gate pad contact hole 145 exposing the gate pad electrode 121 is formed in the gate pad part GPA, and a data pad exposing the data pad electrode 127 in the data pad part DPA. The contact hole 146 is formed.

Next, as illustrated in FIG. 1K, an organic insulating material, benzocyclobutene (BCB) or photo acryl, is applied onto the first protective layer 138 to overcome a step of the lower component, thereby providing a flat surface. The second protective layer 140 having is formed.

Subsequently, the second protective layer 140 is patterned by a mask process so as to be connected to the drain contact hole 143 provided in the first protective layer 138 to drain the electrode 136 of the thin film transistor Tr. A drain contact hole 143 is formed to expose the drain. In this case, the second passivation layer 140 may be formed so as to be removed from the non-display area including the gate and the data pad portions GPA and DPA outside the display area so as to correspond only to the display area.

The formation of the second protective layer 140 made of the organic insulating material only corresponding to the display area and removal of the non-display area enhances adhesion, and inhibits penetration of moisture or oxygen from the outside by strengthening the adhesion force. To do this.

The organic light emitting device substrate is bonded to a second substrate (not shown) for encapsulation later to form an organic light emitting device. In this case, a seal pattern (not shown) that borders the display area and is formed as an adhesive is formed on the non-display area, and the organic light emitting device substrate 110 and the second substrate (not shown) are formed by the seal pattern (not shown). Adhesion is made, and the adhesion between the second protective layer 140 made of an organic insulating material and the seal pattern is poor, resulting in poor adhesion, and tearing occurs due to the weakening of the adhesive force. And the like can penetrate and cause degradation of the organic light emitting layer. Therefore, in order to solve this problem, the second protective layer 140 is removed to remove the non-display area.

On the other hand, the drain contact hole 143 is substantially the first electrode (not shown) of the organic light emitting diode (not shown) formed on the drain electrode 136 and the second protective layer 140 of the driving TFT. 147).

Next, as shown in FIG. 1L, a transparent conductive material having a high work function value on the front surface of the second protective layer 140 in which the drain contact hole 143 is formed, for example, indium-tin-oxide (ITO) or indium. The first electrode 147 is formed in contact with the drain electrode 136 through the drain contact hole 143 by depositing zinc oxide (IZO) on the entire surface and patterning the mask.

At the same time, in the gate pad part GPA, an auxiliary gate pad electrode 150 is formed on the first passivation layer 138 to contact the gate pad electrode 121 through the gate pad contact hole 145. In the data pad part DPA, an auxiliary data pad electrode 152 is formed on the first passivation layer 138 to contact the data pad electrode 127 through the data pad contact hole 146.

On the other hand, to improve the luminous efficiency of the organic light emitting diode (not shown) before depositing the transparent conductive material on the second protective layer 140, a metal material having excellent reflectivity, for example, aluminum (Al), aluminum alloy (AlNd ), Any one of silver (Ag) is deposited first, and then the transparent conductive material is deposited and the two material layers are patterned to form a lower layer (not shown) made of a metallic material having excellent reflectivity and a conductive material having a high work function value. The first electrode 147 may be formed to have a double layer structure of an upper layer. When the first electrode having the lower layer (not shown) of the material having excellent reflectivity is formed, the substrate 110 for the organic light emitting diode of the top emission type is formed.

Next, as shown in FIG. 1M, an organic insulating material such as photoacryl, benzocyclobutene, or polyimide is deposited on the first electrode 147 to form a first organic insulating layer (not shown). The bank 155 is formed in correspondence with the gate and data lines (not shown) by patterning the pattern. In this case, the bank 155 may be formed to overlap the edge of the first electrode 147 provided in each pixel area P.

Therefore, in the display area, the banks 155 are formed in the shape of bordering each pixel area P to form a lattice planarly, and the banks 155 are also removed from the non-display area.

Next, as shown in FIG. 1N, a second organic insulating layer (not shown) is formed on the bank 155 by applying an organic insulating material different from the material forming the bank 155, and patterning the bank. By forming the spacer 160 over the substrate 155, the substrate 110 for an organic light emitting device according to the exemplary embodiment of the present invention is completed.

On the other hand, if the manufacturing process as described above takes a total of nine mask process has the effect of omitting one mask process compared to the manufacturing method that proceeds the conventional 10 mask process.

2A through 2B are cross-sectional views illustrating manufacturing steps of one pixel region of an array substrate for an organic light emitting diode having a thin film transistor having a semiconductor layer of polysilicon according to a second embodiment of the present invention. In the case of the second embodiment of the present invention, only the steps of forming the bank and the spacer are different from those of the first embodiment, and the steps of forming the other components are the same, and therefore only the steps different from the first embodiment will be described. In this case, the same reference numerals are given to the same components as those in the first embodiment.

As shown in FIG. 2A, an organic insulating material having photosensitive properties such as photoacryl, benzocyclobutene, and polyimide is deposited on the first electrode 147 to form an organic insulating layer 153.

Subsequently, an exposure mask 197 having a transmissive area TA, a reflective area BA, and a transflective area HTA is positioned on the organic insulating layer 153, and diffraction exposure or halftone exposure is performed through the exposure mask 197.

Next, as shown in FIG. 2B, when the organic insulating layer (153 in FIG. 2A) subjected to diffraction exposure or halftone exposure is developed, it is applied to the transmission region (TA in FIG. 1N) of the exposure mask (197 in FIG. 2A). A spacer 160 having a first height is formed at a part of a boundary of each corresponding pixel region P, and each pixel corresponding to the transflective region (HTA of FIG. 2A) of the exposure mask 197 of FIG. 2A is formed. A bank 155 is formed at the boundary of the region P to overlap the edge of the first electrode 147 below the spacer 160.

In this case, portions of the second insulating layer (153 of FIG. 2A) corresponding to the blocking region (BA of FIG. 2A) of the exposure mask (197 of FIG. 2A) are all removed during the development process, so that each pixel region P is formed. By exposing the first electrode 147 therein, the array substrate 110 for an organic light emitting device according to the second embodiment of the present invention is completed.

In this case, the organic light emitting diode array substrate 110 according to the embodiment of the present invention performs a total of eight mask processes until the step of forming the banks and the spacers. By shortening a mask process, it has the effect of reducing manufacturing time and manufacturing cost.

3 is a cross-sectional view of one pixel area of a substrate for an organic light emitting device having a thin film transistor having a semiconductor layer of polysilicon according to a third embodiment of the present invention. In the third embodiment of the present invention, the first protective layer made of an inorganic insulating material is omitted compared to the first and second embodiments, and the gate and data pad contact holes are formed in the interlayer insulating film. The steps of forming the other components are the same as those of the first and second embodiments, respectively, and therefore only the steps with differentiation will be described. In this case, the same reference numerals are given to the same components as those in the first embodiment.

First, the ohmic contact layer 133b is formed by forming an interlayer insulating film 123 over the gate wiring (not shown), the gate electrode 120 and the gate pad electrode 121, and patterning the same, as described in the first embodiment. ) And a gate pad contact hole 145 exposing the gate pad electrode 121.

Next, a data line (not shown), a data pad electrode 127, and source and drain electrodes 133 and 136 are formed on the interlayer insulating layer 123.

Subsequently, an organic insulating material is coated on the data line (not shown), the data pad electrode 127, and the source and drain electrodes 133 and 136, and is patterned by performing a mask process on the surface of the display area. A protective layer 141 having a shape and having a drain contact hole 143 exposing the drain electrode 136 is formed.

In this case, the protective layer 141 is formed only in the display area, and thus the data pad electrode 127 is completely exposed in the data pad part DPA positioned in the non-display area outside the display area.

Next, the first electrode is in contact with the drain electrode 136 through the drain contact hole 143 in each pixel region P by depositing a transparent conductive material on the passivation layer 144 and patterning the mask process. 147 is formed.

At the same time, in the gate pad part GPA, an auxiliary gate pad electrode 150 is formed on the interlayer insulating layer 123 to contact the gate pad electrode 121 through the gate pad contact hole 145. In the pad part DPA, an auxiliary data pad electrode 152 is formed on the interlayer insulating layer 123 to cover the data pad electrode 127.

Subsequently, the process of forming the bank 155 and the spacer 160 proceeds in the same manner as in the first or second embodiment to complete the substrate 110 for an organic light emitting device according to the third embodiment of the present invention. do.

According to the method of manufacturing the substrate 110 for an organic light emitting device according to the third embodiment, a total of 10 mask processes are performed until the formation of the bank 155 and the spacer 160 is performed 7 or 8 times. By shortening the mask process twice or three times compared with the conventional process of performing the mask process, the manufacturing time and manufacturing cost can be reduced.

On the other hand, although not shown in the drawing, as described above, the shadow mask having an opening corresponding to the pixel region P corresponding to the substrate for the organic light emitting device manufactured according to the first, second and third embodiments of the present invention ( An organic light emitting layer (not shown) is formed on the first electrode 147 in a region surrounded by the bank 155 by placing the spacer 160 in contact with the spacer 160 and performing vacuum thermal deposition. Metal materials with low work function values over the organic light emitting layer (not shown) in front of the display area, for example, aluminum (Al), aluminum neodymium alloy (AlNd), aluminum magnesium alloy (AlMg), magnesium silver alloy (MgAg) One of silver (Ag) is deposited to form a second electrode (not shown). In this case, the first electrode 147, the organic light emitting layer (not shown), and the second electrode (not shown) form an organic light emitting diode (not shown).

Subsequently, a counter substrate (not shown) is positioned corresponding to the organic light emitting device substrate 110 having the above-described configuration, and then the substrate 110 and the organic light emitting device substrate 110 are in a vacuum atmosphere or an inert gas atmosphere. Form and seal a seal pattern (not shown) along the edge of the counter substrate (not shown), or interpose a face seal (not shown) between the organic light emitting device substrate 110 and the counter substrate (not shown). The organic electroluminescent element (not shown) is completed by bonding together.

110 substrate 111 buffer layer
113: semiconductor layer 113a: active layer
113b: ohmic contact layer 113: LDD layer
115: first storage electrode 116: gate insulating film
118: second storage electrode 120: gate electrode
120a: lower layer of gate electrode 120b: upper layer of gate electrode
121: gate pad electrode 121a: lower layer of gate pad electrode
121b: upper layer of the gate pad electrode 123: interlayer insulating film
125 semiconductor contact hole 127 data pad electrode
133: source electrode 134: third storage electrode
136: drain electrode 138: first protective layer
140: second protective layer 143: drain contact hole
145: gate pad contact hole 146: data pad contact hole
147: first electrode 150: auxiliary gate pad electrode
152: auxiliary data pad electrode 155: bank
160: spacer DA: element region
DPA: Data Pad Section GPA: Gate Pad Section
StgA: Storage Area
StgC1, StgC2: 1st, 2nd storage capacitor
Tr: Thin Film Transistor

Claims (20)

A display area and a non-display area are defined outside the display area, and in the display area, a pixel area is defined by crossing gate lines and data lines, a device area in which a thin film transistor is formed in the pixel area, and a storage capacitor is formed. Forming a semiconductor layer of polysilicon in the device region on the substrate where the region is defined, and forming a semiconductor pattern of polysilicon in the storage region;
Forming a gate insulating film over the semiconductor layer and the semiconductor pattern;
A gate electrode having a multi-layer structure formed on the gate insulating layer, the lower layer having a first width corresponding to a central portion of the semiconductor layer and an upper layer having a second width smaller than the first width, and forming a gate electrode; Forming a storage electrode;
Impurity doping is performed to form an ohmic contact layer doped with a first dose of impurities corresponding to a portion of the semiconductor layer exposed to the outside of the lower layer of the gate electrode, and the gate electrode exposed to the outside of the upper layer of the gate electrode. The portion corresponding to the lower layer of the to form an LDD layer doped with a second dose of impurities smaller than the first dose, the semiconductor pattern is doped with a second dose of impurities to improve the conductivity of the semiconductor pattern Forming a second storage electrode;
Forming an interlayer insulating layer exposing the ohmic contact layer over the gate electrode and the first storage electrode;
Forming source and drain electrodes on the interlayer insulating layer, the source and drain electrodes being in contact with the ohmic contact layer and spaced apart from each other, and simultaneously forming a third storage electrode corresponding to the first storage electrode;
Forming a first passivation layer exposing the drain electrode over the source and drain electrodes and a third storage electrode;
Forming a first electrode in contact with the drain electrode over the protective layer;
Forming a bank having a first height at a boundary at each pixel region over the first electrode, and simultaneously forming a spacer having a second height higher than the first height at a boundary of each pixel region;
Method for producing a substrate for an organic light emitting device comprising a.
The method of claim 1,
Before forming the first passivation layer, forming a second passivation layer exposing the drain electrode over the data line and the source and drain electrodes.
The method according to claim 1 or 2,
Forming a bank having a first height at a boundary at each pixel region over the first electrode, and simultaneously forming a spacer having a second height higher than the first height at a boundary of each pixel region;
Coating a photosensitive organic insulating material on the first electrode to form an organic material layer;
Performing diffraction exposure or halftone exposure on the organic material layer using an exposure mask having a transmission region, a blocking region, and a semi-transmissive region;
The bank having the first height is formed at the boundary of each pixel region by developing the diffractive exposure or the halftone exposed organic material layer, and at the same time the selectively having the second height at the boundary of each pixel region. Forming spacers
Method for producing a substrate for an organic light emitting device comprising a.
The method according to claim 1 or 2,
Forming a bank having a first height at a boundary at each pixel region over the first electrode, and simultaneously forming a spacer having a second height higher than the first height at a boundary of each pixel region;
Applying a photosensitive first organic insulating material over the first electrode to form a first organic material layer;
Patterning the first organic material layer to form the bank having the first height at a boundary of each pixel region;
Applying a second organic insulating material over the bank to form a second organic material layer;
Patterning the second organic material layer to form the spacer having the second height selectively on the bank located at the boundary of each pixel region
Method for producing a substrate for an organic light emitting device comprising a.
The method according to claim 1 or 2,
Forming a semiconductor layer of polysilicon in the device region, and forming a semiconductor pattern of polysilicon in the storage region,
Forming an amorphous silicon layer on the substrate;
Crystallizing the amorphous silicon layer with a polysilicon layer;
Patterning the polysilicon layer
Method for producing a substrate for an organic light emitting device comprising a.
The method according to claim 1 or 2,
A gate electrode having a multi-layer structure formed on the gate insulating layer, the lower layer having a first width corresponding to a central portion of the semiconductor layer and an upper layer having a second width smaller than the first width, and forming a gate electrode; 1 forming the storage electrode,
Forming a transparent conductive material layer and a metal material layer over the gate insulating film;
Forming a first photoresist pattern having a first thickness corresponding to the storage area on the metal material layer, and forming a second photoresist pattern having a second thickness thicker than the first thickness in the device area;
The first storage sequentially stacked in the storage area by sequentially removing the metal material layer and the transparent conductive material layer exposed to the outside of the first and second photoresist patterns by using an etching solution having an etching ratio. Forming a gate electrode and a dummy metal pattern, and forming the gate electrode formed of a transparent conductive material sequentially stacked on the device region, the lower layer having the first width, and the upper layer having a second width and a metal material. Making a step;
Exposing the metal dummy pattern by ashing to remove the first photoresist pattern of the first thickness;
Removing the metal dummy pattern to expose the first storage electrode;
Removing the second photoresist pattern
Method for producing a substrate for an organic light emitting device comprising a.
The method according to claim 1 or 2,
And the source electrode and the third storage electrode are formed to be connected to each other.
The method according to claim 1 or 2,
And the first protective layer is formed of an organic insulating material so as to have a flat surface corresponding to the display area.
The method of claim 1,
The forming of the gate electrode includes forming a gate wiring extending in one direction on each of the pixel regions over the gate insulating layer and forming a gate pad electrode at one end of the gate wiring,
The forming of the source and drain electrodes may include a data line defining the pixel region crossing the gate line over the interlayer insulating layer and a data pad electrode at one end of the data line, and simultaneously being spaced apart from the data line. Method of manufacturing a substrate for an organic light emitting device comprising the step of forming a power wiring.
The method of claim 9,
The forming of the interlayer insulating layer may include forming an active contact hole exposing the ohmic contact layer and a gate pad contact hole exposing the gate pad electrode.
The forming of the first electrode may include forming an auxiliary gate pad electrode on the interlayer insulating layer to contact the gate pad electrode through the gate pad contact hole, and forming an auxiliary data pad electrode covering the data pad electrode. A method of manufacturing a substrate for an organic electroluminescent device comprising.
The method of claim 2,
The forming of the gate electrode includes forming a gate wiring extending in one direction on each of the pixel regions over the gate insulating layer and forming a gate pad electrode at one end of the gate wiring,
The forming of the source and drain electrodes may include a data line defining the pixel region crossing the gate line over the interlayer insulating layer and a data pad electrode at one end of the data line, and simultaneously being spaced apart from the data line. Forming a power wiring;
The forming of the second protective layer includes forming a gate pad contact hole exposing the gate pad electrode and a data pad contact hole exposing the data pad electrode. .
The method of claim 11,
The forming of the first electrode may include forming an auxiliary gate pad electrode contacting the gate pad electrode through the gate pad contact hole on the second passivation layer, and contacting the data pad electrode through the data pad contact hole. A method of manufacturing a substrate for an organic light emitting device comprising the step of forming an auxiliary data pad electrode.
The method according to claim 1 or 2,
Forming a buffer layer on the front surface of the substrate before forming the semiconductor layer and the semiconductor pattern of the polysilicon on the substrate.
The method according to claim 1 or 2,
Forming the first electrode,
Depositing a metal material having excellent reflection efficiency on the first protective layer to form a lower metal layer, depositing a transparent conductive material on the lower metal layer to form an upper conductive layer, and forming the upper conductive layer and the lower metal layer. Forming the first electrode having a double layer structure by patterning continuously, or
Or forming the first electrode having a single layer structure by forming and patterning a transparent conductive material layer over the first protective layer.
Method for producing a substrate for an organic light emitting device comprising a.
A display area and a non-display area are defined outside the display area, and in the display area, a pixel area is defined by crossing gate lines and data lines, a device area in which a thin film transistor is formed in the pixel area, and a storage capacitor is formed. A region is formed in the device region on the defined substrate, and is larger than the first dose amount outside the second region and the second region doped with a first dose amount of impurities on both sides of the first region and the first region. A semiconductor layer of polysilicon composed of a third region doped with a second dose of impurities, a first storage electrode of impurity polysilicon formed in the storage region;
A gate insulating film formed over the semiconductor layer and the first storage electrode;
A plurality of second storage electrodes formed on the gate insulating layer corresponding to the first storage electrode, a lower layer formed corresponding to the first and second regions of the semiconductor layer of the polysilicon, and an upper layer formed corresponding to the second region; A gate electrode having a layer structure;
An interlayer dielectric layer covering the second storage electrode and the gate electrode and exposing the third region of the semiconductor layer, respectively;
A source and drain electrode formed on the interlayer insulating layer and in contact with the third region of the semiconductor layer and spaced apart from each other, and a third storage electrode formed to correspond to the second storage electrode;
A first passivation layer covering the source and drain electrodes and the third storage electrode and exposing the drain electrode and formed in the display area;
A first electrode in contact with the drain electrode over the first passivation layer and formed in each pixel area;
A bank overlapping an edge of the first electrode and having a first height and formed at a boundary of each pixel region, and a spacer selectively formed on the bank;
Substrate for an organic light emitting device comprising a.
The method of claim 15,
A substrate for an organic light emitting diode having a second protective layer formed of an inorganic insulating material in the display area and the non-display area below the first protective layer and exposing the drain electrode.
17. The method according to claim 15 or 16,
The second storage electrode and the lower layer of the gate electrode is made of a transparent conductive material, has a thickness of 100 ~ 500Å,
The upper layer of the gate electrode is an organic light emitting device substrate, characterized in that made of one or two or more metal materials.
17. The method according to claim 15 or 16,
The first storage electrode, the gate insulating layer, and the second storage electrode constitute a first storage capacitor.
The second storage electrode, the interlayer insulating layer, and the third storage electrode constitute a second storage capacitor.
And the first and second storage capacitors are connected in a parallel structure.
17. The method according to claim 15 or 16,
A gate wiring formed at a boundary of each pixel region on the same layer where the gate electrode is formed;
A data line formed on the same layer where the source and drain electrodes are formed to cross the gate line at a boundary of each pixel region;
Power wiring formed to be spaced apart from the data wiring
Substrate for an organic light emitting device comprising a.
17. The method according to claim 15 or 16,
The organic light emitting device substrate of claim 1, wherein a buffer layer is formed on the entire surface of the substrate under the semiconductor layer and the first storage electrode.

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