KR20120067678A - Method for fabricating storage node of capacitor and semiconductor including the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a method for forming a storage node of a capacitor are provided to control the increase of capacitance of a bit line by preventing a short circuit between a bit line and a guard. CONSTITUTION: An insulating layer(120) is formed on a semiconductor substrate(100) including a cell region, a peripheral region, and a border region. A storage node connection contact connected to the cell region of the semiconductor substrate by passing through the insulating layer is formed. A mold layer(150) is formed on the storage node connection contact and the insulating layer. A first opening unit exposing the storage node connection contact is formed. A second opening unit exposing the insulating layer is formed. Storage nodes are connected with the storage node connection contact. A guard(220) is composed of a same material layer with the storage nodes.

Description

Method for forming a storage node of a capacitor and a semiconductor device comprising the same {Method for fabricating storage node of capacitor and semiconductor including the same}

The present invention relates to a semiconductor device, and more particularly, to a method of forming a storage node (SN) of a capacitor connected to a semiconductor substrate and a semiconductor device including the same.

As an increase in the memory capacity of a semiconductor device is required, miniaturization of circuit patterns constituting the semiconductor device is required. The circuit pattern of the semiconductor device is gradually miniaturized from the 50 nm class to the 40 nm class and the 30 nm class, and thus, it is difficult to form the patterns constituting the semiconductor device with a required profile. In a DRAM semiconductor device in which a transistor and a capacitor constitute one memory cell, a cell region in which memory cells are disposed and a cell region are disposed according to the miniaturization of a circuit pattern. Steps are becoming more severe in the peri region in which peripheral circuit elements and wirings for driving the elements of the circuit are arranged. Due to the step difference between the cell region and the peripheral region, it is difficult to form the storage node in the shape of a cylinder only in the cell region.

This step difference between the peripheral region and the cell region is more than when the gate of the transistor of the cell region is formed into a buried gate shape in which the gate is buried in the active region of the semiconductor substrate. Can be terrible. The cell transistors of the cell region are configured to have a buried gate, but the peripheral transistors of the peripheral region may be configured as planar transistors. The storage node of the capacitor formed to be connected to the cell transistor in the cell region may be formed such that a bottom is positioned at a position higher than a position of the wirings formed to be disposed above the planar transistors in the peripheral region. In this case, in the wet process for exposing the cylindrical outer wall surface of the storage node, in order to suppress the occurrence of wet attack on the wiring or other patterns on the peripheral area, this wet process is limited to the cell area only. May be required.

In order to selectively perform the storage node forming process only in the cell region, a method of introducing a guard that surrounds the cell region around the storage nodes may be considered. When the storage node is formed, the guard may be formed in the form of a fence or a moat surrounding the outer edge of the array of storage nodes. Since the guard is formed together with the storage node, a short circuit and a storage node connection contact under the guard may be caused. The storage node connection contact may be formed as a self aligned contact (SAC) to connect the storage node and the source of the transistor formed on the substrate. If a short circuit occurs between the SAC and the bitline, the guard and the bitline formed to be connected to the SAC are shorted, thereby increasing the capacitance of the bitline and thus sensing the operation of the memory cell. A malfunction may be caused in which a margin is reduced. In order to suppress the degradation of the electrical characteristics of the bit line, a method for improving the short circuit between the guard and the bit line is required.

The present invention proposes a method for forming a storage node of a capacitor capable of suppressing a short circuit between a guard and a lower bit line when introducing a guard that surrounds the storage nodes, and a semiconductor device including the same.

One aspect of the invention, forming an insulating layer on a semiconductor substrate including a cell region, a peripheral region and a boundary region therebetween; Forming storage node connection contacts penetrating through the insulating layer and connected to a semiconductor substrate portion of the cell region; Forming a mold layer on the storage node connection contacts and the insulating layer; Selectively etching the mold layer to form a first opening portion exposing the storage node connection contacts and a second opening portion exposing the portion of the insulating layer on the boundary region; Depositing conductive layers on the first and second openings and separating nodes to form guards on the storage nodes connected to the storage node connection contacts and the insulating layer portions; And protecting the mold layer portion overlapping on the peripheral region by the guard and selectively removing the mold layer portion overlapping on the cell region to expose the outer wall of the storage node. We present a method of node formation.

Another aspect of the invention provides a method for forming a buried gate of a transistor in a cell region of a semiconductor substrate including a cell region, a peripheral region, and a boundary region therebetween; Forming bit lines on the semiconductor substrate, the bit lines being insulated by the first insulating layer and the first insulating layer and crossing the buried gates; Forming first openings exposing a portion overlapping the buried gate and a second opening portion exposing a portion overlapping the boundary region in the first insulating layer; Forming a second insulating layer filling the first and second openings and covering a portion of the first insulating layer on the peripheral region; Recessing the second insulating layer to expose a portion of the first insulating layer on the cell region; Selectively removing the exposed portion of the first insulating layer to form through grooves; Forming a first conductive layer filling the through grooves and separating the nodes to form storage node connection contacts; Forming a mold layer on the storage node connection contacts and the second insulating layer; Selectively etching the mold layer to form third openings exposing the storage node connection contacts and a fourth opening portion exposing a portion of the second insulating layer on the boundary region; Depositing a second conductive layer on the third and fourth openings and separating the second conductive layer to form a guard positioned on the storage nodes connected to the storage node connection contact and a portion of the second insulating layer; And protecting the mold layer portion overlapping on the peripheral region by the guard and selectively removing the mold layer portion overlapping on the cell region to expose the outer wall of the storage node. We present a method of node formation.

The first insulating layer and the second insulating layer may be formed to include silicon oxide or silicon nitride to have an etch selectivity.

The forming of the first and second openings may include setting the first openings in a reverse pattern opposite to the shape of the investment gate, and forming the first openings in the overlapping region. Forming a first etching mask on the first insulating layer to set an opening; And etching the portion of the first insulating layer exposed by the first etching mask to form the first and second openings that are self-aligned to the bit line.

The second opening may be formed to have a line width of 2 to 3 times that of the first opening.

Recessing the second insulating layer may include forming a second etching mask that exposes a portion of the second insulating layer overlapping the cell region; And selectively etching the portion of the second insulating layer exposed by the second etching mask to expose the portion of the first insulating layer.

Another aspect of the invention is a semiconductor substrate including a cell region, a peripheral region and a boundary region therebetween; An insulating layer formed on the semiconductor substrate; Storage node connection contacts penetrating the insulating layer and connected to a semiconductor substrate portion of the cell region; Storage nodes of a capacitor connected to the storage node connection contacts; A guard formed on the insulating layer portion on the boundary region outside the array of storage nodes and formed of the same material layer as the storage node; And a mold layer in which a side of the guard contacts and remains as an interlayer insulating layer on the portion of the insulating layer on the peripheral region.

According to the present invention, when the guard is formed on the outside of the storage nodes of the capacitor, the guard is insulated from the lower semiconductor substrate, thereby effectively preventing a short circuit between the guard and the bit line or bit line connection contact disposed below. Can be. Since a short circuit between the guard and the bit line can be prevented, an increase in the capacitance of the bit line due to the short circuit can be suppressed, and a decrease in the signal sensing margin of the bit line due to the short circuit can be prevented. When forming the storage node connection contact connecting the storage node and the substrate, the connection contact can be excluded from the overlapping part of the guard while forming an opening for the connection contact using a damascene process. The guard can be prevented from connecting to the guard.

1 is a schematic view showing a semiconductor device including a capacitor according to an embodiment of the present invention.
2 to 10 are views illustrating a method of forming a storage node of a capacitor according to an embodiment of the present invention.

According to an exemplary embodiment of the present invention, in a DRAM semiconductor device in which a capacitor is disposed on a transistor of a memory cell, when the storage node of the capacitor is formed in a cylindrical shape, it is formed in a ring shape surrounding a cell region in which the storage nodes are arranged. Form the guard with the storage node. When the wet etching process is performed during the formation of the storage node in the cell region, the guard is formed to prevent unwanted intrusion from occurring due to the wet etching affecting the peripheral region outside the cell region. At this time, the connection contact is not introduced to the lower side of the guard so that the guard is floating, thereby effectively suppressing the occurrence of a short between the guard and the bit line or the bit line connection contact disposed below. Can be. As a result, the capacitance of the bit line increases due to the short circuit between the bit line and the guard, so that the sensing margin is reduced during the signal sensing operation of the bit line, thereby effectively preventing the operation of the memory cell.

In order to prevent a short circuit between the guard and the bit line, when forming the storage node connection contacts formed vertically through the bit lines and the bit line connection contacts, the connection contacts are induced not to be disposed under the guard. When forming the through opening for the storage connection contact, by forming a damascene groove in the sacrificial layer and forming an insulating layer filling the damascene groove, and then removing the sacrificial layer, the openings are formed on the lower side of the guard. The insulation layer can be guided to the lower side of the guard, without being disposed in the side wall.

Referring to a schematic diagram of a semiconductor device including a capacitor according to an embodiment of the present invention shown in FIG. 1, the semiconductor substrate 10 includes a cell region in which cell transistors and capacitors 21, 23, and 25 are arranged in a matrix. And a peripheral region in which peripheral circuits for signal sensing or signal writing, such as a sense amplifier, are arranged. Cell transistors are integrated in the semiconductor substrate 10 of the cell region, and storage nodes 21 of a capacitor connected to the substrate 10 to be connected to the cell transistors are formed in a cylindrical shape. The dielectric layer 23 and the plate node 25 are formed on the storage node 21 to form a cell capacitor. The cell capacitor is connected to the substrate 10 by a storage node connection contact 40 formed vertically between bit lines 30 disposed below and bit line connection contacts connecting the substrate 10 with the bit line 30. Connected with

At this time, by arranging the guard 22 in the boundary region between the cell region and the peripheral region, a portion or bit of the insulating layer 50 stacked on the peripheral region in the process of forming the storage nodes 21 of the capacitor in the cell region. The wiring 35 arranged to be connected to the line 30 can be prevented from being invaded by wet etching or the like. In this case, the guard 22 is floated without being connected to the substrate 10. That is, by preventing the connection contact 40 from being formed under the guard 22, it is possible to effectively prevent the failure of short-circuit of the guard 22 and the bit line 30. The bit line 30 may be connected to another wiring of the upper layer by the wiring 35 and the metal contact 60 connected thereto, and the plate node 25 may also be connected to the other wiring by the metal contact 60.

In order to prevent the connection contact 40 from being disposed below the guard 22, a process of forming a damascene groove in the sacrificial layer and the sacrificial layer and forming an insulating layer to fill the connection contact 40 is formed. Introduce.

Referring to FIG. 2, a device isolation layer 103 having a shallow trench isolation structure is formed in the silicon (Si) semiconductor substrate 100 so as to set the active region 101, and buried in the active region 101 of the cell region. After the gate groove 104 is formed, an investment gate 110 filling the investment gate groove 104 is formed. The investment gate 110 includes a gate dielectric layer formed on the surface of the investment gate groove 104, and a gate cap layer 111 for insulation is provided on the investment gate 110 to include an silicon nitride layer. Insulate (110). Junctions such as sources and drains due to impurity implantation are formed in the surface portions of the active region 101 exposed on both sides of the investment gate 110 to form a cell transistor. Although not shown in the peripheral region set outside the cell region, a peripheral transistor for a peripheral circuit for driving a memory cell and reading data, such as a sense amplifier, may be formed on the surface of the semiconductor substrate 100 in the form of a planar transistor. In the boundary region between the cell region and the peripheral region, that is, the boundary region surrounding the outer portion of the cell region, a guard is disposed when forming a storage node of a subsequent capacitor.

After forming the cell transistors including the buried gate 110, the first insulating layer 120 is formed by depositing an insulating material such as a silicon oxide layer. Thereafter, the bit line 300 insulated by the first insulating layer 120 is formed including a metal conductive layer such as tungsten (W). In this case, a barrier metal layer 301 such as titanium nitride (TiN) may be introduced under the bit line 300, and the connection between the bit line 300 and the cell transistor integrated in the lower substrate 100 may be introduced. The bit line connection contact 302 may be formed to penetrate the first insulating layer 120. The bit line cap layer 303 may be formed of an insulating material such as a silicon nitride layer to prevent the bit line 300 from eroding when the self-aligned etching is performed in the subsequent storage node connection contact. The sidewalls may include an insulating spacer 305 including a silicon nitride layer.

A capacitor connected to the source of the cell transistor is integrated to configure the memory cell of the DRAM device above the bit line 300. A storage node connection contact is formed to electrically connect the storage node of the capacitor and the substrate 100. In an exemplary embodiment of the present invention, a damascene process is applied to a process of forming a storage node connection contact, thereby suppressing occurrence of a failure in which the connection contact cannot be connected to the substrate 100 by miniaturization of a pattern.

To this end, a damascene first etch mask 130 is formed on the first insulating layer 120. The portion overlapping the cell region of the first insulating layer 120 is used as the sacrificial layer portion in the damascene process. The damascene process allows the storage node connection contact to be excluded without being placed in the boundary region where the guard is to be formed. To this end, the damascene first etching mask 130 may include a reverse region opposite to the portion 401 where the storage node connection contacts are to be disposed, that is, the first insulating layer 120 overlapping the investment gate 111. It is formed to have a first opening portion 131 exposing). In addition, the second opening 132 may be formed to expose a portion of the first insulating layer 120 overlapping the boundary region between the cell region where the guard is to be disposed and the peripheral region.

Referring to the plan view illustrating the shape of the bit line 300, the bit line connection contact 302, and the first etching mask 130 of FIG. 3, the first etching mask 130 is connected to the storage node connection contact using a SAC process. The first opening portion exposing a reverse region opposite to the portion 401 where the storage node connection contacts are to be disposed and a portion of the first insulating layer 120 overlapping the investment gate 111 may be formed. 131). Since the investment gate 111 intersects the bit line 300 vertically, the first opening part 131 is set to overlap the layout of the investment gate 111 so that the investment gate 111 intersects the bit line 300. It is set to an extended line shape. The first etching mask 130 may be formed to include a photoresist pattern formed by exposure and development.

The second opening portion 132 is set to have a long line shape so as to overlap the boundary region where the guard is to be disposed, and the second opening portion 132 has a rectangular ring surrounding a cell region arranged in a rectangular matrix. ) Is set to the shape. Since the investment gate 111 is repeatedly disposed in a substantially line and space shape, the second opening portion 132 may have three times the line width and pitch of the investment gate 111 having a line and space shape. It can be set to have a line width of about 1.5 times. The second opening portion 132 is set to have a line width that is at least two times larger than the line width of the investment gate 111 or the line width of the first opening portion 131.

Since the first etching mask 130 is introduced to form storage node connection contacts in the cell area, the peripheral area where the wiring 350 connected by using the bit line 300 and the connection contact 351 of the cell area is disposed. It is set to cover the area. As described above, the first etching part includes a first opening part 131 exposing a portion overlapping the buried gate 111, which is a word line, and a second opening part 132 exposing a boundary area where the guard is to be disposed. After the mask 130 is formed on the first insulating layer 120, a damascene etching process of selectively etching a portion of the first insulating layer 120 exposed by the first etching mask 130 is performed.

Referring to FIG. 4, the first damascene groove 121 exposing a portion overlapping the buried gate 111 by selectively etching a portion of the first insulating layer 120 exposed by the first etching mask 130. ) And a second damascene groove 122 exposing the boundary where the guard is to be located. The buried gate 111 formed on the boundary portion is a dummy pattern constituting the dummy cell, and the second damascene groove 122 may be formed to expose the dummy cell portion. In this case, the bit line cap layer 303 and the spacer 305 positioned on the upper side and the side of the bit line 300 remain with the first insulating layer 120 without being etched by the damascene etching with an etching selectivity. . Accordingly, etching is performed by the SAC process that is self-aligned to the bit line 300, so that the first damascene groove 121 and the second damascene groove 122 are first insulated from the side of the bit line 300. It is formed through the layer 120.

Referring to FIG. 5, a second insulating layer 140 is formed to fill the first and second damascene grooves 121 and 122. The second insulating layer 140 may be formed by depositing an insulating material having an etch selectivity with the first insulating layer 120, for example, silicon nitride. After the deposition of the second insulating layer 140, the cell etching area and the boundary area may be exposed, and the second etching mask 150 covering the peripheral area may be formed including a photoresist pattern formed by an exposure and development process. . A portion of the second insulating layer 140 exposed to the second etching mask 150 is recessed so that portions overlapping the cell region and the boundary region have a step difference, and a portion of the first insulating layer 120 is exposed. The recessed second insulating layer pattern 141 is formed.

Referring to FIG. 6, the portion of the first insulating layer 120 exposed by the second insulating layer pattern 141 is selectively removed. The removal process is performed by wet etching using an etching selectivity of the silicon oxide forming the first insulating layer 120 and the silicon nitride forming the second insulating layer pattern 141. One portion of the insulating layer 120 may be selectively etched. By selectively removing the first insulating layer 120, a through hole 145 through which the storage node connection contact is to be formed is formed to penetrate the second insulating layer pattern 141. The through groove 145 is formed in a reverse pattern shape opposite to the shape of the first opening portion 121 of the first etching mask 130 shown in FIG. 3. Accordingly, the through groove 145 extends in the extending direction of the investment gate 111 extending to cross the bit line 300, and exposes the portion between the investment gates 111. It is formed to intersect with. At this time, the first portion 142 of the second insulating layer pattern 141 filling the second opening portion 122 of the boundary portion where the guard is to be formed, and the second insulation providing the shape of the through grooves 145. Since the second portion 143 of the layer pattern 141 is provided, the storage connection contact to be formed to fill the through hole 145 is not disposed at the position where the guard is to be formed.

Referring to FIG. 7, a conductive layer filling the through grooves 145, for example, a conductive polysilicon layer doped with impurities, is deposited to be connected to a portion of the semiconductor substrate 100 exposed by the through grooves 145, and the chemical The storage node connection contact 400 is formed by planarization using mechanical polishing (CMP) and the like, by node separation. The planarization for node separation is performed to expose the cap layer 303 of the bit line 300, so that the conductive layer filling the through groove 145 is separated by the bit line 300. In this case, a portion of the first insulating layer 120 in the peripheral area may also be exposed by planarization. The storage node connection contact 400 is self-aligned at the side of the bit line 300 and penetrates through the second insulating layer pattern 141 to be connected to the substrate 100. In this case, the first portion 142 of the second insulating layer pattern 141 remains in the portion where the guard is to be located so that the conductive layer for the connection contact does not remain.

Referring to FIG. 8, the bit line cap layer portion over the bit line 300 positioned in the peripheral area is selectively removed to expose the bit line 300, and a conductive layer filling the portion where the cap layer is removed is deposited to connect to the contact. A wire 351 is formed to be connected to the connection contact 351. Accordingly, the bit line 300 of the cell region and the wiring 350 of the peripheral region are connected by the connection contact 351. A third insulating layer 350 that insulates the wiring 350 is formed by depositing an insulating material such as a silicon nitride layer, and a cell capacitor having a cylindrical storage node is formed. The third insulating layer 350 may be used as an etch stopper during the formation of the storage node.

Different silicon oxide layers, such as PSG and TEOS layers, are deposited to form a mold layer 150 including a first mold layer 151 and a second mold layer 153. do. The PSG layer may exhibit a relatively high etching rate as compared to the TEOS layer, and thus may be formed of the first mold layer 151. In order to prevent the storage node from falling, a floating fixing layer 155 is formed by depositing an insulating material having an etching selectivity, such as a silicon nitride layer, and a third etching mask 156 is formed on the floating fixing layer 155 by a hard mask. hard mask). The portions exposed by the third etching mask 156 are selectively etched to form third openings 157 exposing the lower storage node connection contact 400. The third openings 157 are formed at positions where the storage nodes are to be formed. In addition, the fourth opening portion 159 is formed on the boundary area where the guard is to be disposed, through the ring-shaped through groove surrounding the outside where the storage nodes are disposed. The fourth opening portion 159 is positioned on the first portion 142 of the second insulating layer pattern 141, and the storage node connection contacts 400 are not exposed to the fourth opening portion 159. The silicon insulating layer constituting the first portion 142 of the second insulating layer pattern 141 is exposed.

Referring to FIG. 9, a conductive layer such as titanium nitride (TiN) is deposited on the third opening portion 157 and the fourth opening portion 159, and the nodes are separated by a planarization method such as CMP. Cylindrical storage nodes 210 and a ring-shaped guard 220 surrounding the area where they are arranged are formed. In this case, the conductive layers may be deposited to form a cylindrical shape, but in some cases, the storage nodes 210 may be formed in a pillar shape to fill the third opening portion 157 and the fourth opening portion 159. have.

Referring to FIG. 10, a fourth etching mask 170 including a photoresist pattern is formed to expose the cell region, and the mold layer 150 of the portion exposed to the fourth etching mask 170 is selectively wetted. Etching exposes the outer wall 211 of the storage node 210. To this end, a portion of the floating pinned layer 155 and the third etching mask 156 may be etched to expose a portion of the lower mold layer 150. In the wet etching process, the guard 220 prevents the wet etchant used for the wet etching from penetrating into the mold layer 150 and the wiring 350 on the peripheral area. Accordingly, the mold layer 150 may remain on the peripheral area to be used as an interlayer insulating layer. Thereafter, a dielectric layer and a plate node are formed on the storage node 210 to form a capacitor, thereby constituting a memory cell of a DRAM device including a capacitor and a transistor.

In the method of forming a storage node of a capacitor according to the embodiment of the present invention as described above, when the guard 220 is formed together with the storage node 210, the storage node connection contacts 400 are formed under the guard 220. The first portion 142 of the second insulating layer pattern 141 remains. Accordingly, the guard 220 is positioned in a floating state on the first portion 142 of the second insulating layer pattern 141, so that the bit line 300 or the bit line connection contact 302 is located below. And short circuit can be effectively prevented. Since the storage node connection contact 400 is not positioned below the guard 220, the storage connection contact 400 is not formed in the bit line 300 or the bit line connection contact 302 in a self-aligned manner. Short circuit between 300 and guard 220 can be effectively prevented. Accordingly, the capacitance of the bit line 300 is increased due to the short circuit with the guard 220, thereby effectively preventing the decrease in data sensing sensitivity and margin, thereby improving the memory cell operation reliability of the DRAM device. have.

100 ... substrate 111 ... investment gate,
210 ... storage node 220 ... guard
300 ... bit line.

Claims (7)

Forming an insulating layer on the semiconductor substrate including the cell region, the peripheral region and the boundary region therebetween;
Forming storage node connection contacts penetrating through the insulating layer and connected to a semiconductor substrate portion of the cell region;
Forming a mold layer on the storage node connection contacts and the insulating layer;
Selectively etching the mold layer to form a first opening portion exposing the storage node connection contacts and a second opening portion exposing the portion of the insulating layer on the boundary region;
Depositing conductive layers on the first and second openings and separating nodes to form guards on the storage nodes connected to the storage node connection contacts and the insulating layer portions; And
Protecting the mold layer portion overlapping on the peripheral region by the guard and selectively removing the mold layer portion overlapping on the cell region to expose an outer wall of the storage node. Forming method.
Forming a buried gate of a transistor in said cell region of a semiconductor substrate comprising a cell region, a peripheral region and a boundary region therebetween;
Forming bit lines on the semiconductor substrate, the bit lines being insulated by the first insulating layer and the first insulating layer and crossing the buried gates;
Forming first openings exposing a portion overlapping the buried gate and a second opening portion exposing a portion overlapping the boundary region in the first insulating layer;
Forming a second insulating layer filling the first and second openings and covering a portion of the first insulating layer on the peripheral region;
Recessing the second insulating layer to expose a portion of the first insulating layer on the cell region;
Selectively removing the exposed portion of the first insulating layer to form through grooves;
Forming a first conductive layer filling the through grooves and separating the nodes to form storage node connection contacts;
Forming a mold layer on the storage node connection contacts and the second insulating layer;
Selectively etching the mold layer to form third openings exposing the storage node connection contacts and a fourth opening portion exposing a portion of the second insulating layer on the boundary region;
Depositing a second conductive layer on the third and fourth openings and separating the second conductive layer to form a guard positioned on the storage nodes connected to the storage node connection contact and a portion of the second insulating layer; And
Protecting the mold layer portion overlapping on the peripheral region by the guard and selectively removing the mold layer portion overlapping on the cell region to expose an outer wall of the storage node. Forming method.
The method of claim 2,
And the first insulating layer and the second insulating layer are formed of silicon oxide or silicon nitride to have an etch selectivity therebetween.
The method of claim 2,
Forming the first and second openings (opening)
A first etching mask configured to set the first opening part in a reverse pattern opposite to the shape of the investment gate and set the second opening part in an area overlapping the boundary area on the first insulating layer. Forming; And
And etching the portion of the first insulating layer exposed by the first etching mask to form the first and second openings self-aligned to the bit line.
The method of claim 2,
The second opening portion (opening) is a storage node forming method of the capacitor is formed to have a line width of 2 to 3 times than the first opening portion.
The method of claim 2,
Recessing the second insulating layer
Forming a second etching mask exposing a portion of the second insulating layer overlapping the cell region; And
Selectively etching the portion of the second insulating layer exposed to the second etching mask to expose the portion of the first insulating layer.
A semiconductor substrate including a cell region, a peripheral region, and a boundary region therebetween;
An insulating layer formed on the semiconductor substrate;
Storage node connection contacts penetrating the insulating layer and connected to a semiconductor substrate portion of the cell region;
Storage nodes of a capacitor connected to the storage node connection contacts;
A guard formed on the insulating layer portion on the boundary region outside the array of storage nodes and formed of the same material layer as the storage node; And
And a mold layer in side contact with the guard and remaining as an interlayer insulating layer on the portion of the insulating layer on the peripheral region.

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