KR20120045201A - Non-volatile memory apparatus and method for status detecting of flag cell - Google Patents

Non-volatile memory apparatus and method for status detecting of flag cell Download PDF

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Publication number
KR20120045201A
KR20120045201A KR1020100106596A KR20100106596A KR20120045201A KR 20120045201 A KR20120045201 A KR 20120045201A KR 1020100106596 A KR1020100106596 A KR 1020100106596A KR 20100106596 A KR20100106596 A KR 20100106596A KR 20120045201 A KR20120045201 A KR 20120045201A
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South Korea
Prior art keywords
flag cell
flag
reliability
cell group
data
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KR1020100106596A
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Korean (ko)
Inventor
김유성
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에스케이하이닉스 주식회사
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Priority to KR1020100106596A priority Critical patent/KR20120045201A/en
Publication of KR20120045201A publication Critical patent/KR20120045201A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification

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Abstract

A flag cell group selected by selecting any one of a memory cell array connected between a plurality of word lines and a plurality of bit lines, a flag cell unit including a plurality of flag cell groups indicating a program state of the memory cell array, and a plurality of flag cell groups A nonvolatile memory device including a controller for determining a reliability of a flag cell group selected from data read from the present invention, and a flag cell state detection method therefor.

Description

Non-volatile Memory Apparatus and Method for Status Detecting of Flag Cell}

The present invention relates to a semiconductor integrated circuit, and more particularly, to a nonvolatile memory device and a flag cell state detection method therefor.

A nonvolatile memory device represented by a flash memory device includes a multi-level cell that stores multi-bit data in a single memory cell from a single level cell (SLC) that stores a single level of data in one memory cell. Multi Level Cell (MLC).

In a nonvolatile memory device including a multi-level cell, one word line has logically multiple pages, and each bit represents one bit information. For example, a wordline of a memory cell that can store two bits of data logically contains two pages, each of which is divided into a least significant bit (LSB) and a most significant bit (MSB). .

In order to perform a normal program and read operation with respect to the nonvolatile memory device including the multi-bit cell, it is determined whether only the LSB is programmed or even the MSB is programmed.

For this purpose, a flag cell was introduced. The flag cell is used to represent state information in which the memory cell is programmed. When the memory cell is programmed or read, the flag cell reads data of the flag cell first to determine the program state.

A plurality of flag cells, that is, a group of flag cells, are connected to one word line, and when the data of the flag cells connected to a specific word line is read, the program state of all the word lines can be known.

Currently, in checking a program state through a flag cell, one of a plurality of flag cell groups is selected to read data of the flag cell to check the program state of each word line.

1 is a flowchart illustrating a general flag cell state detection method.

As shown in the figure, data recorded in each flag cell is read from one of the flag cell groups constituted by the plurality of groups from the plurality of flag cells included in the group (S101).

Then, status information is output in accordance with the result of reading data from the plurality of flag cells (S103). In this case, for example, the majority rule can be used.

As a result of the determination in step S103, if it is determined that the program is not completed until the most significant bit (MSB) (S105), the least significant bit (LSB) of the memory cell is read (S107), and if the program is completed to the most significant bit, the memory is read. The most significant bit of the cell is read (S109).

Data is written in a flag cell in a manner similar to programming data in a nonvolatile memory cell, and thus has the potential to distort the data written to the flag cell. Therefore, when checking the program state using only one of the plurality of flag cell groups as in the present, the reliability thereof cannot be guaranteed.

The present invention provides a nonvolatile memory device capable of reliably determining a program state of a memory cell and a flag cell state detection method therefor.

Another object of the present invention is to provide a nonvolatile memory device capable of accurately determining a program state of a memory cell even when data of a flag cell is distorted, and a method for detecting a flag cell state therefor.

In accordance with an aspect of the present invention, there is provided a nonvolatile memory device including: a memory cell array connected between a plurality of word lines and a plurality of bit lines; A flag cell unit including a plurality of flag cell groups representing a program state of the memory cell array; And a controller for selecting any one of the plurality of flag cell groups to determine the reliability of the selected flag cell group from data read from the selected flag cell group.

Meanwhile, a flag cell state detection method according to an embodiment of the present invention is a flag cell state detection method of a nonvolatile memory device including a memory cell array and a flag cell unit indicating a program state of the memory cell array. Selecting one of a plurality of flag cell groups included; Reading data of the selected flag cell group; Determining the reliability of the selected flag cell group from the read result; And if it is determined that the reliability of the selected flag cell group is not guaranteed, selecting one of the unselected flag cell groups.

In the present invention, when one of a plurality of flag cell groups is selected and reliability of data read therefrom is not guaranteed, another flag cell group is selected to determine the reliability of the flag cell group.

Therefore, the flag cell group containing the error is selected, thereby solving the problem that the program state of the memory cell array is misleading, and thus, there is an advantage of accurately determining the program state.

Furthermore, when the reliability of the selected flag cell group is not guaranteed, the reliability of all the flag cell groups can be determined to more accurately determine the program state.

1 is a flowchart illustrating a general flag cell state detection method;
2 is a configuration diagram of a nonvolatile memory device according to an embodiment of the present invention;
3 is a diagram for explaining the structure of a nonvolatile memory cell and a flag cell;
4 is a flowchart illustrating a flag cell state detection method according to an embodiment of the present invention;
5 is a flowchart for explaining a reliability determination process illustrated in FIG. 4;
6 is a flowchart illustrating a flag cell state detection method according to another embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

2 is a configuration diagram of a nonvolatile memory device according to an embodiment of the present invention.

As shown in FIG. 2, the nonvolatile memory device 10 according to an exemplary embodiment of the present invention may include a data storage unit 110, a page buffer unit 120, a Y decoder 130, an X decoder 140, And a voltage supply unit 150 and a controller. In addition, the data storage unit 110 includes a memory cell array 112 and a flag cell unit 114.

The memory cell array 112 may include a plurality of memory cells for data storage, a plurality of drain select switches driven by the drain select signal DSL, and a plurality of source select switches driven by the source select signal SSL. Include. A drain select switch, n + 1 memory cells connected in series to the drain select switch, and a source select switch connected to the source terminal of the last memory cell connected in series form one cell string and are connected to one word line WL. The memory cells to be connected form one page.

The bit lines BLe and BLo extend from the drain terminal of each drain select switch and are connected to the page buffer unit 120.

The flag cell unit 114 includes a plurality of flag cells for indicating a program state of each word line, and a group of flag cells connected to one word line includes, for example, as many flag cells as the number of word lines. It may include.

3 is a diagram for describing the structures of a nonvolatile memory cell and a flag cell.

As illustrated, memory cells connected to one word line form a unit page and logically have a plurality of pages. 3 illustrates a unit page of a memory cell capable of storing 2-bit data LSB and MSB.

Meanwhile, the flag cell group connected to one word line includes a plurality of flag cells, for example, as many flag cells as the number n-1 of word lines.

The page buffer unit 120 is connected to the bit lines BLe and BLo connected to the memory cells constituting the memory cell array 112 to program data in the memory cells or to read data stored in the memory cells. It includes a buffer circuit.

The Y decoder 130 provides an input / output path of a page buffer circuit connected to a memory cell to be accessed according to input address information, and the X decoder 140 is a word line of a memory cell to be accessed according to input address information. Select.

The voltage supply unit 150 generates and supplies an operating voltage under the control of the controller 160.

The program operation for the memory cell array 112 is generally performed in the word line direction. When a program for each word line is completed, a flag cell connected to the corresponding word line is programmed.

In order to determine a program state of the memory cell array 112 from data stored in the flag cell unit 114 including a plurality of flag cell groups, the plurality of flag cells are controlled by the X decoder 140 under the control of the controller 160. One of the groups is selected. Data stored in each flag cell of the selected flag cell group is read by operations of the Y decoder 130 and the page buffer unit 120 under the control of the controller 160.

The controller 160 counts the number of flag cells in which data of a predetermined level is recorded in the selected flag cell group according to the read result of the page buffer unit 120, and generates a comparison value from the count result. In addition, the generated comparison value is compared with the offset value to determine the reliability of the selected flag cell group.

If the data of the selected flag cell group is guaranteed reliability, the flag cell state information is output. On the other hand, if the reliability of the data of the selected flag cell group is not guaranteed, another flag cell group is selected to determine reliability.

In an embodiment of the present invention, the reference for generating a comparison value from the number of flag cells in which data of a predetermined level is recorded in the selected flag cell group is set to N (number of counts-N / 2) when the number of word lines is N. Can be set. In addition, the offset value can be set to (0.1N to 0.3N).

For example, when only the least significant bit is programmed for the memory cell array, the flag cell may store high level data, that is, logic '1' data. When the most significant bit is programmed, the flag cell may have low level data, Logical '0' data may be stored.

Accordingly, by counting the number of flag cells in which logical '0' data is written in the selected flag cell group, and generating a comparison value and comparing the offset value with the offset value, it is determined whether the memory cell array has been programmed to the most significant bit.

When counting the number of data of a predetermined level from any one selected flag cell group and outputting flag cell state information, it may not be free from a read error of the flag cell. However, as in the present invention, when the reliability of the selected flag cell group is not satisfactory, selecting another flag cell group to determine the reliability has an advantage of more accurately confirming the program state of the memory cell array.

4 is a flowchart illustrating a flag cell state detection method according to an embodiment of the present invention.

The flag cell group connected to any one word line is selected by the X decoder 140 under the control of the controller 160 (S201).

Accordingly, the page buffer unit 120 reads data from the flag cells included in the selected flag cell group and stores the data in the latch (S203), and the controller 160 determines reliability from the data stored in the latch (S205). That is, reliability is determined based on the number of flag cells in which data of a predetermined level is recorded in the selected flag cell group.

If reliability is ensured as a result of the determination in step S205, state information generated from the selected flag cell group is output (S211).

On the other hand, if the reliability is not guaranteed, the controller 160 generates address information for selecting another flag cell group for determining the program state, and accordingly, the X decoder 140 selects another flag cell group (S207). .

The page buffer unit 120 reads data of the flag cell group selected in step S207 (S209), and the controller 160 outputs state information of the flag cells according to the read result of the page buffer unit 120 (S211). .

As described above, when the data of the flag cell group selected initially is not secured, another flag cell group is selected and the program state of the memory cell array is determined from the data of the secondly selected flag cell group. This results in an increase in the number of samples that can determine the program state, thereby accurately determining the program state of the memory cell array.

FIG. 5 is a flowchart for describing a reliability determination process illustrated in FIG. 4.

As the page buffer unit 120 reads the data of the flag cell group selected by the X decoder 140, the controller 160 counts the number of flag cells in which data of a predetermined level is recorded in the corresponding flag cell group. (S301).

Then, a comparison value is generated from the count result of step S301. When the number of word lines is N, the comparison value may be set to (count count-N / 2), for example. When the comparison value is generated, the comparison value is compared with the offset value (S303). In one embodiment of the present invention, the offset value may be set to (0.1N to 0.3N).

It is assumed that one flag cell group is selected from a flag cell group of a memory cell array including 32 word lines. As a result of reading the data stored in the selected flag cell group, the comparison value becomes (20-32 / 2 = 4) when the number of flag cells having a logic low level, that is, '0' data, is counted as 20. If the offset value is 0.2N, that is, 6.4, since the comparison value is smaller than the offset value, it is determined that the data of the flag cell group is not reliable.

Thereafter, another flag cell group is selected, and when the number of flag cells in which '0' data is stored is 25 (25-32 / 2 = 9) as a result of reading data stored in the secondly selected flag cell group, Since it is larger than the offset value (0.2N = 6.4), it is determined that the data of the flag cell group is reliable.

Whenever a program is sequentially performed on 32 word lines, data is written to a flag cell. However, in the above example, data of a flag cell group selected primarily includes incorrectly written data. Therefore, the program state of the memory cell array can be accurately determined by selecting another flag cell group to determine reliability.

6 is a flowchart illustrating a flag cell state detection method according to another embodiment of the present invention.

In this embodiment, a method of more accurately determining a program state of a nonvolatile memory device by increasing the number of samples is provided.

The flag cell group connected to any one word line is selected by the X decoder 140 under the control of the controller 160 (S401).

Accordingly, the page buffer unit 120 reads data from the flag cells included in the selected flag cell group and stores the data in the latch (S403), and the controller 160 determines reliability from the data stored in the latch (S405). That is, reliability is determined based on the number of flag cells in which data of a predetermined level is recorded in the selected flag cell group.

If the reliability is guaranteed as a result of the determination in step S405, the state information generated from the selected flag cell group is output (S407).

On the other hand, if the reliability is not guaranteed, the controller 160 generates address information for selecting another flag cell group for determining the program state, and accordingly, the X decoder 140 selects another flag cell group (S409). .

The page buffer unit 120 reads data of the flag cell group selected in step S409 (S411), and the controller 160 determines reliability according to the read result of the page buffer unit 120 (S413).

If it is determined that the reliability is guaranteed as a result of the determination in step S413, the controller 160 proceeds to step S407 of outputting status information, and otherwise checks whether a flag cell group not yet selected exists (S415). ). If there is an unselected flag cell group, the process proceeds to step S409 to change the flag cell group and determine reliability, and outputs status information when the reliability of all the flag cell groups is determined. Step S407 is performed.

In this embodiment, when the reliability of the selected flag cell group is not guaranteed, the reliability of the flag cell group is determined until all flag cell groups are selected.

Therefore, even if there are a plurality of flag cell groups in which flag data is incorrectly written, the program state of the memory cell array can be accurately confirmed.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

10: nonvolatile memory device
110: data storage
112: memory cell array
114: flag cell part
120: page buffer
130: Y decoder
140: X decoder
150: voltage supply
160: controller

Claims (12)

A memory cell array connected between a plurality of word lines and a plurality of bit lines;
A flag cell unit including a plurality of flag cell groups representing a program state of the memory cell array; And
A controller for selecting any one of the plurality of flag cell groups to determine reliability of the selected flag cell group from data read from the selected flag cell group;
Nonvolatile memory device comprising a. The method of claim 1,
And the controller outputs flag cell state information when it is determined that the reliability of the selected flag cell group is guaranteed. The method of claim 1,
And if the controller determines that the reliability of the selected flag cell group is not guaranteed, the controller selects one of the unselected flag cell groups. The method of claim 2,
And the controller outputs flag cell state information as data is read from any one of the unselected flag cell groups. The method of claim 2,
And the controller determines reliability of a flag cell group selected from the unselected flag cell groups. The method of claim 5, wherein
And if the controller determines that the reliability of the selected flag cell group is not guaranteed, the controller determines reliability until all flag cell groups are selected. The method of claim 1,
The controller generates a comparison value by counting the number of flag cells in which data of a predetermined level is recorded from the selected flag cell group, and compares the comparison value with a preset offset value to determine the reliability of the selected flag cell group. Non-volatile memory device to determine. A flag cell state detection method of a non-volatile memory device comprising a memory cell array and a flag cell unit indicating a program state of the memory cell array.
Selecting one of a plurality of flag cell groups included in the flag cell unit;
Reading data of the selected flag cell group;
Determining the reliability of the selected flag cell group from the read result; And
Selecting one of the unselected flag cell groups if it is determined that the reliability of the selected flag cell group is not guaranteed;
A flag cell state detection method for a nonvolatile memory device comprising a. The method of claim 8,
And reading out data by outputting flag cell state information when any one of the unselected flag cell groups is selected. The method of claim 8,
If it is determined that the reliability of the selected flag cell group is not secured, changing the flag cell group until all unselected flag cell groups are selected to determine the reliability of the flag cell state for the non-volatile memory device. Detection method. The method of claim 8,
The determining of the reliability may include generating a comparison value by counting the number of flag cells in which data of a predetermined level is recorded from the selected flag cell group, and comparing the comparison value with a preset offset value. A flag cell state detection method for a device. The method of claim 8,
And outputting flag cell state information when it is determined that the reliability of the selected flag cell group is secured.
KR1020100106596A 2010-10-29 2010-10-29 Non-volatile memory apparatus and method for status detecting of flag cell KR20120045201A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130055062A (en) * 2011-11-18 2013-05-28 삼성전자주식회사 Method of reading data in nonvolatile memory device and method of operating nonvolatile memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130055062A (en) * 2011-11-18 2013-05-28 삼성전자주식회사 Method of reading data in nonvolatile memory device and method of operating nonvolatile memory device
KR101878455B1 (en) * 2011-11-18 2018-07-16 삼성전자주식회사 Method of reading data in nonvolatile memory device and method of operating nonvolatile memory device

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