KR20120004729A - Semiconductor memory device - Google Patents
Semiconductor memory device Download PDFInfo
- Publication number
- KR20120004729A KR20120004729A KR1020100065375A KR20100065375A KR20120004729A KR 20120004729 A KR20120004729 A KR 20120004729A KR 1020100065375 A KR1020100065375 A KR 1020100065375A KR 20100065375 A KR20100065375 A KR 20100065375A KR 20120004729 A KR20120004729 A KR 20120004729A
- Authority
- KR
- South Korea
- Prior art keywords
- signal
- precharge
- output line
- operation mode
- output
- Prior art date
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2227—Standby or low power modes
Abstract
The present invention relates to a semiconductor memory device with a minimum current consumption, and to receive a precharge signal that is toggled according to an operation command. A semiconductor memory device including a charge control unit and a precharge unit for precharging an input / output line pair to a predetermined voltage level in response to a precharge control signal is provided.
Description
The present invention relates to a semiconductor design technology, and more particularly, to a semiconductor memory device.
In general, a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) transfers data to a memory cell or to an external device through a local input / output line pair (LIO, LIOB) in a read operation mode or a write operation mode. When the read operation mode or the write operation mode ends, the local input / output line pairs LIO and LIOB are precharged to the core voltage level. In addition, the semiconductor memory device is provided with a burst operation function that can read or write data two or more times in succession. Even when performing such a burst operation function, a local input / output line pair (LIO, LIOB) is performed between data processing operations. Precharge).
1 is a block diagram of a conventional semiconductor memory device.
Referring to FIG. 1, the
The
The
The
The
Hereinafter, the operation of the conventional
2A illustrates a timing diagram of the
First, referring to FIG. 2A, when the read command RD is input in synchronization with the rising edge of the clock signal CLK, the
Next, referring to FIG. 2B, when the write command WT is input in synchronization with the rising edge of the clock signal CLK, the
However, the conventional
As described above, the
Therefore, in the write operation mode, the precharge operation is performed every time the write command WT is input, so that the
An object of the present invention is to provide a semiconductor memory device with a minimum current consumption in a write operation mode.
According to an aspect of the present invention, the present invention receives a precharge signal toggled according to an operation command and limits the toggling section of the precharge signal according to an operation mode classification signal to output a precharge control signal. And a control unit and a precharge unit for precharging the input / output line pairs to a predetermined voltage level in response to the precharge control signal.
According to another aspect of the present invention, the present invention receives a precharge signal toggled according to a read command and a write command to limit the toggling section of the precharge signal to a read operation mode section to output a precharge control signal, In the write operation mode section, a precharge controller for outputting a precharge control signal only when the data mask signal is activated, and a precharge for precharging the input / output line pairs to a predetermined voltage level in response to the precharge control signal. Contains wealth.
The present invention has the effect of preventing unnecessary current consumption by limiting a toggling period of the precharge signal so as not to perform an unnecessary precharge operation in the write operation mode.
1 is a block diagram of a conventional semiconductor memory device.
FIG. 2A is a timing diagram for describing an operation of the semiconductor memory device of FIG. 1 according to a read operation mode. FIG.
FIG. 2B is a timing diagram for describing an operation of the semiconductor memory device of FIG. 1 according to a write operation mode. FIG.
3 is a configuration diagram of a semiconductor memory device according to an embodiment of the present invention.
FIG. 4A is a timing diagram for describing an operation of the semiconductor memory device of FIG. 3 according to a read operation mode; FIG.
4B is a timing diagram for describing an operation of the semiconductor memory device of FIG. 3 according to a write operation mode.
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention.
3 is a block diagram of a semiconductor memory device according to an embodiment of the present invention.
Referring to FIG. 3, the
The
The
The
The
The
Hereinafter, the operation of the
4A illustrates a timing diagram of the
First, referring to FIG. 4A, when the read command RD is input in synchronization with the rising edge of the clock signal CLK, the
Meanwhile, the operation of the
Next, referring to FIG. 4B, when the write command WT is input in synchronization with the rising edge of the clock signal CLK, the
Meanwhile, the
As a result, since the operation mode division signal pair local input / output line pairs LIO and LIOB are not precharged in the remaining sections except for the section in which the data mask signal DM is activated in the write operation mode, the global input / output line GIO Local I / O line pairs LIO and LIOB are toggled only in accordance with the toggle state. Accordingly, since the
According to the exemplary embodiment of the present invention, unnecessary precharge operation is not performed in the write operation mode, thereby preventing unnecessary current consumption from the
Although the technical spirit of the present invention has been described in detail with reference to the above embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible with various substitutions, modifications, and changes within the scope of the technical idea of the present invention.
200: semiconductor memory device 210: write driver
220: read driver 230: precharge unit
240: precharge control unit 242: toggling section limiting unit
244: activation section determination unit 246: output unit
250: core area LIO, LIOB: local I / O line pair
GIO: Global I / O Line
Claims (8)
A precharge unit for precharging an input / output line pair to a predetermined voltage level in response to the precharge control signal
And a semiconductor memory device.
The operation mode classification signal is a signal for distinguishing a read operation mode or a write operation mode according to whether it is activated.
A precharge unit for precharging an input / output line pair to a predetermined voltage level in response to the precharge control signal
And a semiconductor memory device.
The precharge control unit,
A toggling period limiter configured to limit a toggling period of the precharge signal in response to an operation mode classification signal;
An activation section determiner configured to determine an activation section of the precharge control signal in response to a precharge strobe signal and the data mask signal in the write operation mode section; And
And an output unit configured to output the precharge control signal in response to an output signal of the toggling section limiter and an output signal of the activation section determiner.
The operation mode classification signal is a signal for distinguishing a read operation mode or a write operation mode according to whether it is activated.
The input / output line pairs are local input / output line pairs (LIO, LIOB).
A read driver for transferring data contained in the local input / output line pair to a global input / output line (GIO) in response to a read driver strobe signal;
A write driver for transferring data carried in the global input / output line to the local input / output line pair in response to a write driver strobe signal; And
And a core area for storing data carried in the local input / output line pair or providing the stored data to the local input / output line pair.
The read driver includes an input / output sense amplifier (IOSA).
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020100065375A KR20120004729A (en) | 2010-07-07 | 2010-07-07 | Semiconductor memory device |
US13/178,033 US8559254B2 (en) | 2010-07-07 | 2011-07-07 | Precharging circuit and semiconductor memory device including the same |
CN201110189332.5A CN102347067B (en) | 2010-07-07 | 2011-07-07 | Pre-charge circuit and comprise the semiconductor storage unit of described pre-charge circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020100065375A KR20120004729A (en) | 2010-07-07 | 2010-07-07 | Semiconductor memory device |
Publications (1)
Publication Number | Publication Date |
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KR20120004729A true KR20120004729A (en) | 2012-01-13 |
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ID=45611151
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020100065375A KR20120004729A (en) | 2010-07-07 | 2010-07-07 | Semiconductor memory device |
Country Status (1)
Country | Link |
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KR (1) | KR20120004729A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20140141091A (en) * | 2013-05-31 | 2014-12-10 | 에스케이하이닉스 주식회사 | Circuit for transfering data and memory including the same |
-
2010
- 2010-07-07 KR KR1020100065375A patent/KR20120004729A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20140141091A (en) * | 2013-05-31 | 2014-12-10 | 에스케이하이닉스 주식회사 | Circuit for transfering data and memory including the same |
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