KR20120004729A - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
KR20120004729A
KR20120004729A KR1020100065375A KR20100065375A KR20120004729A KR 20120004729 A KR20120004729 A KR 20120004729A KR 1020100065375 A KR1020100065375 A KR 1020100065375A KR 20100065375 A KR20100065375 A KR 20100065375A KR 20120004729 A KR20120004729 A KR 20120004729A
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KR
South Korea
Prior art keywords
signal
precharge
output line
operation mode
output
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KR1020100065375A
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Korean (ko)
Inventor
김승봉
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020100065375A priority Critical patent/KR20120004729A/en
Priority to US13/178,033 priority patent/US8559254B2/en
Priority to CN201110189332.5A priority patent/CN102347067B/en
Publication of KR20120004729A publication Critical patent/KR20120004729A/en

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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4091Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4096Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22Control and timing of internal memory operations
    • G11C2207/2227Standby or low power modes

Abstract

The present invention relates to a semiconductor memory device with a minimum current consumption, and to receive a precharge signal that is toggled according to an operation command. A semiconductor memory device including a charge control unit and a precharge unit for precharging an input / output line pair to a predetermined voltage level in response to a precharge control signal is provided.

Description

Technical Field [0001] The present invention relates to a semiconductor memory device,

The present invention relates to a semiconductor design technology, and more particularly, to a semiconductor memory device.

In general, a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) transfers data to a memory cell or to an external device through a local input / output line pair (LIO, LIOB) in a read operation mode or a write operation mode. When the read operation mode or the write operation mode ends, the local input / output line pairs LIO and LIOB are precharged to the core voltage level. In addition, the semiconductor memory device is provided with a burst operation function that can read or write data two or more times in succession. Even when performing such a burst operation function, a local input / output line pair (LIO, LIOB) is performed between data processing operations. Precharge).

1 is a block diagram of a conventional semiconductor memory device.

Referring to FIG. 1, the semiconductor memory device 100 may include a write driver 110 for transferring data carried on a global input / output line GIO to a local input / output line pair LIO and LIOB in a write operation mode, and a read operation mode. Read driver 120 for transferring data carried on the local input / output line pairs LIO and LIOB to the global input / output line GIO, and the local input / output line pairs LIO and LIOB in response to the precharge signal LIOPCG. The precharge unit 130 for precharging stores data stored in the local input / output line pairs LIO and LIOB in the write operation mode, and transfers the stored data to the local input / output line pairs LIO and LIOB in the read operation mode. It includes a core region 140 for.

The write driver 110 transfers data carried in the global input / output line GIO to the local input / output line pairs LIO and LIOB in response to the write driver strobe signal WSTB. That is, the write driver 110 drives the local input / output line pairs LIO and LIOB to a predetermined voltage in response to data transmitted through the global input / output line GIO. In response to the data mask signal DM, the write driver 110 skips the corresponding data among the data loaded on the global input / output line GIO and transfers the remaining data to the local input / output line pairs LIO and LIOB. For example, when the burst length is '8', eight data BL0 to BL7 are continuously loaded on the global input / output line GIO. In this case, the data mask signal DM corresponds to the first data BL0. ) Is activated, only seven data BL1 to BL7 except the first data BL0 are transferred to the local input / output line pairs LIO and LIOB.

The read driver 120 transmits data carried in the local input / output line pairs LIO and LIOB to the global input / output line GIO in response to the read driver strobe signal IOSTB. In general, the read driver 120 uses an input / output sense amplifier (IOSA).

The precharge unit 130 includes first to third PMOS transistors PM1, PM2, and PM3 to precharge the local input / output line pairs LIO and LIOB to the core voltage level VCORE. In this case, the precharge signal LIOPCG is applied to the gate terminals of the first to third PMOS transistors PM1, PM2, and PM3 through the first and second inverters INV1 and INV2, and the precharge signal LIOPCG. When the first and third PMOS transistors PM1, PM2, and PM3 are turned on when is activated to a logic low level, the local input / output line pairs LIO and LIOB are precharged to the core voltage level VCORE.

The core region 140 includes a bit line sense amplifier (BLSA), a memory cell array, and the like, and transfers data stored in a memory cell to a local input / output line pair (LIO, LIOB) or local input / output according to a read / write operation mode. The data carried in the line pair LIO and LIOB is stored in the memory cell.

Hereinafter, the operation of the conventional semiconductor memory device 100 having the above configuration will be described with reference to FIGS. 2A and 2B.

2A illustrates a timing diagram of the semiconductor memory device 100 according to the read operation mode, and FIG. 2B illustrates a timing diagram of the semiconductor memory device 100 according to the write operation mode.

First, referring to FIG. 2A, when the read command RD is input in synchronization with the rising edge of the clock signal CLK, the read driver 120 responds to the read driver strobe signal IOSTB in response to a local input / output line pair LIO. , And sequentially amplify the data contained in LIOB) and transfers the data to the global input / output line (GIO). At this time, the precharge unit 130 precharges the local input / output line pairs LIO and LIOB to the core voltage VCORE level prior to the read operation in response to the precharge signal LIOOCG, that is, between the read commands RD. Let's do it. In this case, data sequentially transmitted from the corresponding memory cell of the core region 140 is sequentially amplified by the bit line sense amplifier BLSA and loaded on the local input / output line pairs LIO and LIOB. Since the data amplified by the BLSA is transmitted to the local input / output line pairs LIO and LIOB as a small signal having a smaller swing width than the output of the write driver 110, the local input / output line pairs LIO and LIOB may be used. In order for the data loaded in succession to be correctly transmitted to the global input / output line GIO, the precharge operation is performed for each read command RD.

Next, referring to FIG. 2B, when the write command WT is input in synchronization with the rising edge of the clock signal CLK, the write driver 110 responds to the write driver strobe signal WSTB to output the global input / output line GIO. The data contained in the data is sequentially transmitted to the local input / output line pairs (LIO and LIOB). In this case, since the write driver 110 drives the local input / output line pairs LIO and LIOB with a sufficiently large driving force, the data loaded on the local input / output line pairs LIO and LIOB may have a full signal having a large swing width. Has The precharge unit 130 precharges the local input / output line pairs LIO and LIOB between the write commands WT in response to the precharge signal LIOPCG similarly to the read operation mode.

However, the conventional semiconductor memory device 100 has the following problems.

As described above, the precharge unit 130 performs a precharge operation between the read command RD and the write command WT. In the read operation mode, the precharge operation is necessarily required, but in the write operation mode, the precharge operation is not necessarily required. The reason for this is that in the read operation mode, small signal data having a small swing width is loaded on the local input / output line pairs (LIO and LIOB). In the write operation mode, the precharge operation is unnecessary because data in the form of a full signal having a large swing width is loaded on the local input / output line pairs LIO and LIOB. However, as shown in FIG. 2B, in the write operation mode, the precharge signal LIOPCG is continuously toggled according to the write command WT continuously input. In other words, the global input / output line GIO is toggled every two write commands WT, while the local input / output line pairs LIO and LIOB are toggled every one write command WT.

Therefore, in the write operation mode, the precharge operation is performed every time the write command WT is input, so that the write driver 110 may select any one of the local input / output line pairs LIO and LIOB precharged to the core voltage VCORE level. By pulling down one again, there is a problem that unnecessary current consumption occurs from the write driver 110.

An object of the present invention is to provide a semiconductor memory device with a minimum current consumption in a write operation mode.

According to an aspect of the present invention, the present invention receives a precharge signal toggled according to an operation command and limits the toggling section of the precharge signal according to an operation mode classification signal to output a precharge control signal. And a control unit and a precharge unit for precharging the input / output line pairs to a predetermined voltage level in response to the precharge control signal.

According to another aspect of the present invention, the present invention receives a precharge signal toggled according to a read command and a write command to limit the toggling section of the precharge signal to a read operation mode section to output a precharge control signal, In the write operation mode section, a precharge controller for outputting a precharge control signal only when the data mask signal is activated, and a precharge for precharging the input / output line pairs to a predetermined voltage level in response to the precharge control signal. Contains wealth.

The present invention has the effect of preventing unnecessary current consumption by limiting a toggling period of the precharge signal so as not to perform an unnecessary precharge operation in the write operation mode.

1 is a block diagram of a conventional semiconductor memory device.
FIG. 2A is a timing diagram for describing an operation of the semiconductor memory device of FIG. 1 according to a read operation mode. FIG.
FIG. 2B is a timing diagram for describing an operation of the semiconductor memory device of FIG. 1 according to a write operation mode. FIG.
3 is a configuration diagram of a semiconductor memory device according to an embodiment of the present invention.
FIG. 4A is a timing diagram for describing an operation of the semiconductor memory device of FIG. 3 according to a read operation mode; FIG.
4B is a timing diagram for describing an operation of the semiconductor memory device of FIG. 3 according to a write operation mode.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention.

3 is a block diagram of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 3, the semiconductor memory device 200 may include a write driver 210 for transferring data carried on a global input / output line GIO to a local input / output line pair LIO and LIOB in a write operation mode, and a read operation mode. A read driver 220 for transferring data contained in the local input / output line pairs LIO and LIOB to the global input / output line GIO and a local input / output line pair LIO and LIOB in response to the precharge control signal PCGS. Precharge unit 230 for precharging the precharge signal and precharge signal LIOPCG toggled according to an operation command, and toggling the precharge signal LIOPCG according to the operation mode classification signal WTS. A precharge control unit 240 for restricting and outputting the precharge control signal PCGS and data stored in the local input / output line pairs LIO and LIOB in the write operation mode, and storing the stored data in the read operation mode. It comprises a core region (250) for delivering the local IO line pair (LIO, LIOB). Here, the operation command includes a read command input in a read operation mode and a write command input in a write operation mode, and the operation mode classification signal WTS is a read operation mode or write depending on whether it is activated. The operation mode classification signal for distinguishing the operation modes.

The write driver 210 transfers data carried in the global input / output line GIO to the local input / output line pairs LIO and LIOB in response to the write driver strobe signal WSTB. That is, the write driver 210 drives the local input / output line pairs LIO and LIOB to a predetermined voltage in response to data transmitted through the global input / output line GIO. Meanwhile, the write driver 210 skips the corresponding data among the data loaded on the global input / output line GIO in response to the data mask signal DM, and transfers the remaining data to the local input / output line pairs LIO and LIOB. For example, when the burst length is '8', eight data BL0 to BL7 are continuously loaded on the global input / output line GIO. In this case, the data mask signal DM corresponds to the first data BL0. ) Is activated, only seven data BL1 to BL7 except the first data BL0 are transferred to the local input / output line pairs LIO and LIOB.

The read driver 220 transmits data carried on the local input / output line pairs LIO and LIOB to the global input / output line GIO in response to the read driver strobe signal IOSTB. In general, the read driver 120 uses an input / output sense amplifier (IOSA).

The precharge unit 230 includes first to third PMOS transistors PM1, PM2, and PM3 to precharge the local input / output line pairs LIO and LIOB to the core voltage level VCORE. Here, the precharge control signal PCGS is applied to the gate terminals of the first to third PMOS transistors PM4, PM5, and PM6. Accordingly, when the precharge control signal PCGS is activated to the logic low level, the first and third PMOS transistors PM4, PM5, and PM6 are turned on, so that the local input / output line pairs LIO and LIOB become the core voltage VCORE. ) Is precharged to the level.

The precharge control unit 240 outputs the precharge control signal PCGS by limiting the toggling section of the precharge signal LIOPCG to the read operation mode section, but in the write operation mode section, the data mask signal DM is activated. Only when the precharge control signal PCGS is output to the active state. The precharge control unit 240 includes a toggling section limiting unit 242 for limiting a toggling section of the precharge signal LIOPCG in response to an operation mode classification signal WTS, a data mask signal DM, and data. An activation section determination unit 244 for determining an activation section of the precharge control signal PCGS in response to a precharge signal LIOPCGDM for the mask and an operation mode classification signal WTS, and a toggling section limiter 242. And an output unit 246 for outputting the precharge control signal PCGS in response to the output signal of the control unit and the output signal of the activation section determination unit 244. The toggling period limiter 242 receives a precharge signal LIOPCG and an operation mode division signal WTS, and includes a first NOR gate NOR1 for performing an NOR operation, and a first NO gate. And a first inverter INV3 for receiving the output signal of NOR1 and inverting the same. The activation interval determiner 244 receives a precharge signal LIOPCGDM and an operation mode classification signal WTS for a data mask, and includes a first NAND gate NAND1 for performing an AND operation; Performing an AND operation by receiving the second inverter INV4 for outputting the inverted output signal of the first NAND gate NAND1, the output signal of the second inverter INV4, and the data mask signal DM And a second NAND gate NAND2 for the same. The output unit 246 receives an output signal of the first inverter INV3 and an output signal of the second NAND gate NAND2, and receives a third NAND gate NAND3 and a third NAND gate for performing an AND operation. And a third inverter INV5 for inverting and outputting the output signal of NAND3.

The core region 250 includes a bit line sense amplifier BLSA, a memory cell array (not shown), and the like, and store data stored in a memory cell according to a read / write operation mode in a local input / output line pair (LIO, LIOB). Data stored in a pair of local input / output line LIO and LIOB is stored in a memory cell.

Hereinafter, the operation of the semiconductor memory device 200 according to the present invention having the above configuration will be described with reference to FIGS. 4A and 4B.

4A illustrates a timing diagram of the semiconductor memory device 200 according to the read operation mode, and FIG. 4B illustrates a timing diagram of the semiconductor memory device 200 according to the write operation mode.

First, referring to FIG. 4A, when the read command RD is input in synchronization with the rising edge of the clock signal CLK, the read driver 220 responds to the read driver strobe signal IOSTB to output a local input / output line pair LIO. , And sequentially amplify the data contained in LIOB) and transfers the data to the global input / output line (GIO). At this time, the precharge unit 230 before and after the read operation in response to the precharge control signal PCGS applied from the precharge control unit 240, that is, the local input / output line pairs LIO and LIOB for each read command RD. Is precharged to the core voltage VCORE level. In this case, data sequentially transmitted from the corresponding memory cell of the core region 250 is sequentially amplified by the bit line sense amplifier BLSA and loaded on the local input / output line pairs LIO and LIOB. Since the data amplified by the BLSA is transmitted to the local input / output line pairs LIO and LIOB as a small signal having a smaller swing width than the output of the write driver 110, the local input / output line pairs LIO and LIOB may be used. In order for the data loaded in succession to be correctly transmitted to the global input / output line GIO, the precharge operation is performed for each read command RD.

Meanwhile, the operation of the precharge controller 240 will be described in brief. In the read operation mode, since the data mask signal DM maintains a logic low level, the output signal of the activation section determiner 244 maintains a logic high level. . The output signal of the toggling period limiter 242 is toggled in the same manner as the precharge signal LIOPCG as the operation mode classification signal WTS maintains a logic low level. Accordingly, the precharge control signal PCGS output through the output unit 246 may be output in a form in which the precharge signal LIOPCG is toggled in the same manner. That is, in the read operation mode, the precharge control signal PCGS that is toggled in the same manner as the precharge signal LIOPCG is applied to the precharge unit 230.

Next, referring to FIG. 4B, when the write command WT is input in synchronization with the rising edge of the clock signal CLK, the write driver 210 responds to the write driver strobe signal WSTB to output the global input / output line GIO. The data contained in the data is sequentially transmitted to the local input / output line pairs (LIO and LIOB). In this case, since the write driver 110 drives the local input / output line pairs LIO and LIOB with a sufficiently large driving force, the data loaded on the local input / output line pairs LIO and LIOB may have a full signal having a large swing width. Has

Meanwhile, the precharge unit 230 does not perform the precharge operation according to the precharge control signal PCGS applied from the precharge control unit 240 regardless of the input of the write command WT. However, the precharge unit 230 performs the precharge operation only when the data mask signal DB is activated. More specifically, in the write operation mode, since the data mask signal DM maintains the logic low level, the output signal of the activation section determiner 244 maintains the logic high level. In addition, since the operation mode division signal WTS maintains a logic high level, the output signal of the toggling period limiter 242 has a logic high level. Therefore, since the precharge control signal PCGS output through the output unit 246 has a logic high level, the first to third PMOS transistors P4, P5, and P6 are precharged as they are turned off. It will not perform the action. In this state, when the data mask signal DM is activated and transitioned to a logic high level, the output signal of the activation section determination unit 244 is inverted and outputted with the precharge signal LIOPCGDM for the data mask, and the toggle section The output signal of the limiter 242 maintains a logic high level as it is. Therefore, the precharge control signal PCGS output through the output unit 246 is output by inverting the precharge signal LIOPCGDM for the data mask. In this case, since the precharge control signal PCGS has a logic low level only during the period in which the data mask signal DM is activated, the first to third PMOS transistors P4, P5, and P6 are turned on to precharge the precharge control signal PCGS. Will perform the action.

As a result, since the operation mode division signal pair local input / output line pairs LIO and LIOB are not precharged in the remaining sections except for the section in which the data mask signal DM is activated in the write operation mode, the global input / output line GIO Local I / O line pairs LIO and LIOB are toggled only in accordance with the toggle state. Accordingly, since the write driver 210 does not need to pull down any one of the local input / output line pairs LIO and LIOB again as the precharge operation is not performed, the write driver 210 can save the current consumption. .

According to the exemplary embodiment of the present invention, unnecessary precharge operation is not performed in the write operation mode, thereby preventing unnecessary current consumption from the write driver 210.

Although the technical spirit of the present invention has been described in detail with reference to the above embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible with various substitutions, modifications, and changes within the scope of the technical idea of the present invention.

200: semiconductor memory device 210: write driver
220: read driver 230: precharge unit
240: precharge control unit 242: toggling section limiting unit
244: activation section determination unit 246: output unit
250: core area LIO, LIOB: local I / O line pair
GIO: Global I / O Line

Claims (8)

A precharge control unit configured to receive a precharge signal toggled according to an operation command and to output a precharge control signal by limiting a toggling period of the precharge signal according to an operation mode classification signal; And
A precharge unit for precharging an input / output line pair to a predetermined voltage level in response to the precharge control signal
And a semiconductor memory device.
The method of claim 1,
The operation mode classification signal is a signal for distinguishing a read operation mode or a write operation mode according to whether it is activated.
The precharge signal is toggled according to a read command and a write command, and the precharge control signal is output by limiting the toggling period of the precharge signal to a read operation mode period, but the data mask signal is activated in the write operation mode period. A precharge control unit for outputting the precharge control signal in an activated state only when the control unit is activated; And
A precharge unit for precharging an input / output line pair to a predetermined voltage level in response to the precharge control signal
And a semiconductor memory device.
The method of claim 3,
The precharge control unit,
A toggling period limiter configured to limit a toggling period of the precharge signal in response to an operation mode classification signal;
An activation section determiner configured to determine an activation section of the precharge control signal in response to a precharge strobe signal and the data mask signal in the write operation mode section; And
And an output unit configured to output the precharge control signal in response to an output signal of the toggling section limiter and an output signal of the activation section determiner.
The method of claim 4, wherein
The operation mode classification signal is a signal for distinguishing a read operation mode or a write operation mode according to whether it is activated.
The method according to claim 3 to 5,
The input / output line pairs are local input / output line pairs (LIO, LIOB).
The method of claim 6,
A read driver for transferring data contained in the local input / output line pair to a global input / output line (GIO) in response to a read driver strobe signal;
A write driver for transferring data carried in the global input / output line to the local input / output line pair in response to a write driver strobe signal; And
And a core area for storing data carried in the local input / output line pair or providing the stored data to the local input / output line pair.
The method of claim 7, wherein
The read driver includes an input / output sense amplifier (IOSA).
KR1020100065375A 2010-07-07 2010-07-07 Semiconductor memory device KR20120004729A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020100065375A KR20120004729A (en) 2010-07-07 2010-07-07 Semiconductor memory device
US13/178,033 US8559254B2 (en) 2010-07-07 2011-07-07 Precharging circuit and semiconductor memory device including the same
CN201110189332.5A CN102347067B (en) 2010-07-07 2011-07-07 Pre-charge circuit and comprise the semiconductor storage unit of described pre-charge circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100065375A KR20120004729A (en) 2010-07-07 2010-07-07 Semiconductor memory device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140141091A (en) * 2013-05-31 2014-12-10 에스케이하이닉스 주식회사 Circuit for transfering data and memory including the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140141091A (en) * 2013-05-31 2014-12-10 에스케이하이닉스 주식회사 Circuit for transfering data and memory including the same

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