KR20110133769A - Stacked semiconductor package - Google Patents

Stacked semiconductor package Download PDF

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Publication number
KR20110133769A
KR20110133769A KR1020100053357A KR20100053357A KR20110133769A KR 20110133769 A KR20110133769 A KR 20110133769A KR 1020100053357 A KR1020100053357 A KR 1020100053357A KR 20100053357 A KR20100053357 A KR 20100053357A KR 20110133769 A KR20110133769 A KR 20110133769A
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South Korea
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substrate
package
semiconductor chip
borland
pad
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KR1020100053357A
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Korean (ko)
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박경숙
민복규
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주식회사 하이닉스반도체
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Priority to KR1020100053357A priority Critical patent/KR20110133769A/en
Publication of KR20110133769A publication Critical patent/KR20110133769A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
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    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE: A stacked semiconductor package is provided to arrange an external connection terminal on the entire area of a lower package, thereby suppressing warpage of the semiconductor package during a molding process or a thermal processing process. CONSTITUTION: A lower package(100) includes a first substrate(110) and a first semiconductor chip(120). The first substrate includes one side(110A) and the other side(110B) facing the one side. The first semiconductor chip is attached to the central part of the other side of the first substrate by a first adhesive member(170). An upper package(200) is mounted on the first borland of the first substrate. The upper package includes a second substrate(210), a second semiconductor chip(220), and a second external connection terminal(250).

Description

적층 반도체 패키지{STACKED SEMICONDUCTOR PACKAGE}Multilayer Semiconductor Packages {STACKED SEMICONDUCTOR PACKAGE}

본 발명은 적층 반도체 패키지에 관한 것이다.The present invention relates to a laminated semiconductor package.

반도체 장치는 고성능 및 고집적화를 목적으로 개발되고 있다. 고성능 및 고집적화된 반도체 장치를 제조하기 위해서는 패키징 기술의 뒷받침이 무엇보다 중요하다. 이는 패키징 기술에 따라서 반도체 장치의 크기, 열방출 능력, 전기적 수행 능력, 신뢰성, 가격 등이 크게 변하기 때문이다.Semiconductor devices have been developed for the purpose of high performance and high integration. The backing of packaging technology is of paramount importance for the manufacture of high performance and highly integrated semiconductor devices. This is because the size, heat dissipation capability, electrical performance, reliability, price, etc. of the semiconductor device greatly change depending on the packaging technology.

패키징 기술은 SIP(Single Inline Package), DIP(Dual Inline Package), QFP(Quad Flat Package), BGA(Ball Grid Array) 순으로 발전되어 왔다. 최근에는, 단위 체적당 실장효율을 높이기 위하여 CSP(Chip Scale Package), MCP(Multi Chip Package), SCSP(Stacked CSP) WLCSP(Wafer Level CSP), POP(Package On Package) 등과 같은 패키징 기술도 개발되었다. Packaging technologies have been developed in the order of a single inline package (SIP), a dual inline package (DIP), a quad flat package (QFP), and a ball grid array (BGA). Recently, packaging technologies such as Chip Scale Package (CSP), Multi Chip Package (MCP), Stacked CSP (WSPSP), Wafer Level CSP (WLCSP), and Package On Package (POP) have been developed to increase the mounting efficiency per unit volume. .

이들 중에서 POP 패키징 기술은 개별적으로 조립(packaging) 및 전기적 검사(electrical test)가 완료된 패키지를 수직 방향으로 적층(stack)하여 적층 반도체 패키지를 구성하는 기술로, 일반적으로 POP 형태의 적층 반도체 패키지에서는 적층되는 패키지들간 조인트 신뢰성(joint reliability)이 매우 중요하다. Among them, POP packaging technology is a technique for forming a stacked semiconductor package by stacking packages that have been individually assembled and electrically tested in a vertical direction. Joint reliability between packages is very important.

도 1은 종래 기술에 의한 POP 형태의 적층 반도체 패키지를 도시한 단면도이다.1 is a cross-sectional view illustrating a laminated semiconductor package having a POP type according to the prior art.

도 1을 참조하면, 종래 기술에 의한 적층 반도체 패키지는 하부 패키지(10) 및 상부 패키지(20)를 포함한다.Referring to FIG. 1, the multilayer semiconductor package according to the related art includes a lower package 10 and an upper package 20.

하부 패키지(10)는 제1기판(11), 제1반도체 칩(12)을 포함한다. 제1기판(11) 일면 중심부에는 제1반도체 칩(12)이 형성되고, 제1반도체 칩(12) 바깥쪽 제1기판(11) 일면 가장자리에는 제1볼랜드(11A)가 형성된다. 제1볼랜드(11A)에는 상부 패키지(20)가 실장된다. The lower package 10 includes a first substrate 11 and a first semiconductor chip 12. The first semiconductor chip 12 is formed at the center of one surface of the first substrate 11, and the first borland 11A is formed at the edge of one surface of the first substrate 11 outside the first semiconductor chip 12. The upper package 20 is mounted on the first borland 11A.

미설명된 도면부호 13, 14, 15 및 16은 각각 하부 패키지(10)에 포함된 제1본딩 와이어, 제1몰드부, 제1외부접속단자 및 제1접착부재를 나타내고, 11B는 제1기판(11)에 형성된 제2볼랜드를 나타낸다. 그리고, 21, 22, 23, 24, 25 및 26은 상부 패키지(20)를 구성하는 제2기판, 제2반도체 칩, 제2본딩 와이어, 제2몰드부, 제2외부접속단자 및 제2접착부재를 나타낸다.Unexplained reference numerals 13, 14, 15, and 16 denote a first bonding wire, a first mold portion, a first external connection terminal, and a first adhesive member included in the lower package 10, respectively, and 11B denotes a first substrate. The second borland formed in (11) is shown. In addition, 21, 22, 23, 24, 25, and 26 may include a second substrate, a second semiconductor chip, a second bonding wire, a second mold part, a second external connection terminal, and a second adhesive constituting the upper package 20. Indicates absence.

전술한 종래 기술에 의한 적층 반도체 패키지는 조인트 신뢰성이 취약한 문제점이 있다. 구체적으로, 몰딩 공정이나 열가공 공정시 적층 반도체 패키지를 구성하는 부품들간 열팽창 계수 차이에 따른 응력에 의해 휨(warpage)이 발생되고, 이로 인해 제2외부접속단자(25)가 들뜨게 되어 접합 불량이 발생된다. 이러한 접합 불량은, 하부 패키지(10)와 상부 패키지(20)를 연결하는 제2외부접속단자(25)를 다수 설치함으로써 해결할 수 있으나, 종래 기술에서는 제2외부접속단자(25)가 설치되는 제1볼랜드(11A)의 위치가 제1반도체 칩(12) 바깥쪽 제1기판(11) 가장자리 부분으로 국한되기 때문에, 상, 하부 패키지(10,20)를 견고하게 결속하기 어렵다. The multilayer semiconductor package according to the related art described above has a problem in that joint reliability is weak. Specifically, warpage occurs due to stress due to a difference in coefficient of thermal expansion between components constituting the laminated semiconductor package during a molding process or a heat processing process, and thus the second external connection terminal 25 is lifted up, resulting in poor bonding. Is generated. Such poor bonding can be solved by installing a plurality of second external connection terminals 25 connecting the lower package 10 and the upper package 20. However, in the related art, the second external connection terminal 25 is installed. Since the position of one borland 11A is limited to the edge portion of the first substrate 11 outside the first semiconductor chip 12, it is difficult to firmly bind the upper and lower packages 10 and 20.

또한, 제1반도체 칩(12) 상, 하부의 상부 패키지 및 제1기판(11)에 막혀 제1반도체 칩(12) 동작시 제1반도체 칩(12)에서 발생되는 열이 외부로 방출되지 못하여 반도체 장치의 특성 열화를 초래하는 문제점이 있다.In addition, when the first semiconductor chip 12 operates, the heat generated from the first semiconductor chip 12 may not be released to the outside by being blocked by the upper package and the first substrate 11 on the first semiconductor chip 12. There is a problem that causes deterioration of characteristics of the semiconductor device.

본 발명은, 조인트 신뢰성 및 열방출 특성을 향상시킬 수 있는 적층 반도체 패키지를 제공하는데, 그 목적이 있다.An object of the present invention is to provide a laminated semiconductor package capable of improving joint reliability and heat dissipation characteristics.

본 발명의 일 견지에 따른 적층 반도체 패키지는, 중심부에 일면 및 상기 일면과 대향하는 타면을 관통하는 개구가 형성되고 상기 일면에 상기 개구를 따라서 제1접속패드가 형성되고 상기 일면에 상기 제1접속패드와 이격되어 다수개의 제1볼랜드들이 분포된 제1기판, 상기 제1기판 타면에 부착되며 상기 개구에 대응되는 제1본딩패드를 갖는 제1반도체 칩, 상기 제1기판의 제1접속패드와 상기 제1반도체 칩의 제1본딩 패드를 연결하는 제1연결부재를 포함하는 하부 패키지와, 상기 하부 패키지의 상기 제1볼랜드 상에 실장되는 상부 패키지를 포함하는 것을 특징으로 한다.In the multilayer semiconductor package according to an aspect of the present invention, an opening penetrating through one surface and the other surface facing the one surface is formed at a central portion thereof, and a first connection pad is formed along the opening on the one surface, and the first connection is formed on the one surface. A first semiconductor chip spaced apart from the pad and having a plurality of first borlands distributed thereon, a first semiconductor chip attached to the other surface of the first substrate and having a first bonding pad corresponding to the opening, and a first connection pad of the first substrate And a lower package including a first connection member connecting the first bonding pad of the first semiconductor chip, and an upper package mounted on the first borland of the lower package.

상기 하부 패키지는, 상기 제1반도체 칩을 포함한 상기 제1기판 타면을 밀봉하는 제1몰드부와, 상기 제1연결부재를 포함한 상기 개구를 밀봉하는 제2몰드부를 더 포함하는 것을 특징으로 한다.The lower package may further include a first mold part sealing the other surface of the first substrate including the first semiconductor chip, and a second mold part sealing the opening including the first connection member.

상기 제1연결부재는 본딩 와이어를 포함하는 것을 특징으로 한다.The first connection member is characterized in that it comprises a bonding wire.

상기 상부 패키지는, 상면 및 하면을 가지며 상기 상면에 제2접속패드가 형성되고 상기 하면에 상기 하부 패키지의 제1볼랜드들에 대응되는 제3볼랜드들이 형성된 제2기판과, 상기 제2기판 상면 상에 형성되며 제2접속패드와 연결되는 제2본딩패드를 갖는 제2반도체 칩과, 상기 제1볼랜드들 및 상기 제1볼랜드들 각각에 대응되는 제3볼랜드들을 연결하는 외부접속단자들을 포함하는 것을 특징으로 한다.The upper package includes a second substrate having an upper surface and a lower surface, a second connection pad formed on the upper surface, and third borlands formed on the lower surface corresponding to the first borlands of the lower package, and an upper surface of the second substrate. A second semiconductor chip having a second bonding pad formed on the second connection pad and connected to the second connection pad, and an external connection terminal connecting the first borlands and third borland corresponding to each of the first borlands. It features.

상기 제2외부접속단자는 솔더볼을 포함하는 것을 특징으로 한다.The second external connection terminal is characterized in that it comprises a solder ball.

상기 상부 패키지는, 상기 제2기판의 제2접속패드와 상기 제2반도체 칩의 제2본딩패드를 연결하는 제2연결부재와, 상기 제2반도체 칩을 포함한 상기 제2기판 상면을 밀봉하는 제3몰드부를 더 포함하는 것을 특징으로 하는 적층 반도체 패키지.The upper package may include a second connecting member connecting the second connection pad of the second substrate and the second bonding pad of the second semiconductor chip and an upper surface of the second substrate including the second semiconductor chip. The laminated semiconductor package further comprises a three mold portion.

본 발명에 의하면, 적층 반도체 패키지의 조인트 신뢰성 및 열방출 특성이 향상되는 효과가 있다.According to the present invention, there is an effect that the joint reliability and heat dissipation characteristics of the laminated semiconductor package are improved.

도 1은 종래의 적층 반도체 패키지를 도시한 단면도이다.
도 2는 본 발명의 실시예에 의한 적층 반도체 패키지를 도시한 단면도이다.1 is a cross-sectional view illustrating a conventional laminated semiconductor package.
2 is a cross-sectional view illustrating a multilayer semiconductor package according to an embodiment of the present invention.

이하, 첨부된 도면들을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명의 실시예에 의한 적층 반도체 패키지를 도시한 단면도이다.2 is a cross-sectional view illustrating a multilayer semiconductor package according to an embodiment of the present invention.

도 2를 참조하면, 본 발명의 실시예에 의한 적층 반도체 패키지는 하부 패키지(100) 및 상부 패키지(200)를 포함한다.2, a multilayer semiconductor package according to an embodiment of the present invention includes a lower package 100 and an upper package 200.

하부 패키지(100)는 제1기판(110) 및 제1반도체 칩(120)를 포함한다. 그 외에, 제1연결부재(130), 제1,제2몰드부(140,150) 및 제1외부접속단자(160)를 더 포함한다.The lower package 100 includes a first substrate 110 and a first semiconductor chip 120. In addition, the apparatus further includes a first connection member 130, first and second mold parts 140 and 150, and a first external connection terminal 160.

제1기판(110)은 플레이트 형상을 갖는다. 플레이트 형상을 갖는 제1기판(110)은 일면(110A), 일면(110A)과 대향하는 타면(110B)을 갖는다. 제1기판(110)은 복수개의 층들에 형성된 회로 패턴들 및 서로 다른 층에 배치된 회로 패턴들을 연결하는 바아(via)을 포함할 수 있다. The first substrate 110 has a plate shape. The first substrate 110 having a plate shape has one surface 110A and the other surface 110B facing the one surface 110A. The first substrate 110 may include a via connecting the circuit patterns formed on the plurality of layers and the circuit patterns disposed on different layers.

제1기판(110) 중심부에는 일면(110A) 및 타면(110B)을 관통하는 개구(111)가 형성되고, 제1기판(110) 일면(110A)는 제1접속패드(112) 및 다수개의 제1볼랜드(113)들이 형성되고, 타면(110B)에는 제2볼랜드(114)가 형성된다.An opening 111 penetrating through one surface 110A and the other surface 110B is formed in a central portion of the first substrate 110, and the first surface 110A of the first substrate 110 may include a first connection pad 112 and a plurality of materials. One borland 113 is formed, the second borland 114 is formed on the other surface (110B).

제1접속패드(112)는 제1기판(110) 일면(110A)에 개구(111)를 따라서 형성되고, 제1볼랜드(113)들은 제1접속패드(112)와 이격되어 제1기판(110) 일면(110)에 분포된다. 제1볼랜드(113)들은 상부 패키지(200)가 실장되는 부분으로, 하부 패키지(100)와 상부 패키지(200)가 견고하게 결속될 수 있도록 제1볼랜드(113)들은 제1기판(110) 일면(110A) 전영역에 걸쳐 배치된다. 그리고, 제2볼랜드(114)는 제1기판(110) 타면(110B) 가장자리에 배치된다. The first connection pad 112 is formed along the opening 111 at one surface 110A of the first substrate 110, and the first borland 113 is spaced apart from the first connection pad 112 so as to space the first substrate 110. ) Is distributed on one surface 110. The first borlands 113 are portions in which the upper package 200 is mounted, and the first borlands 113 are formed on one surface of the first substrate 110 so that the lower package 100 and the upper package 200 can be firmly bound. It is arrange | positioned over 110A. The second borland 114 is disposed at the edge of the other surface 110B of the first substrate 110.

제1접속패드(112), 제1볼랜드(113) 및 제2볼랜드(114)는 제1기판(110)에 형성된 상기 회로 패턴들 및 비아 등을 통해 상호 연결된다. The first connection pad 112, the first borland 113, and the second borland 114 are connected to each other through the circuit patterns and vias formed on the first substrate 110.

제1반도체 칩(120)은 제1기판(110) 타면(110B) 중심부에 제1접착부재(170)를 매개로 부착된다.The first semiconductor chip 120 is attached to the center of the other surface 110B of the first substrate 110 through the first adhesive member 170.

제1반도체 칩(120)은 제1기판(110)과 대응하는 제1면 및 제1면과 대향하는 제2면을 갖는다. 제1반도체 칩(120) 제1면 중심부에는 제1기판(110)의 개구(111)에 대응되는 제1본딩패드(121)가 형성된다.The first semiconductor chip 120 has a first surface corresponding to the first substrate 110 and a second surface facing the first surface. A first bonding pad 121 corresponding to the opening 111 of the first substrate 110 is formed at the center of the first surface of the first semiconductor chip 120.

제1연결부재(130)는 개구(111)를 통과하여 제1기판(110)의 제1접속패드(112)와 제1반도체 칩(120)의 제1본딩패드(121)를 연결한다. 본 실시예에서, 제1연결부재(130)는 본딩 와이어(bonding wire)로 형성된다.The first connection member 130 passes through the opening 111 to connect the first connection pad 112 of the first substrate 110 and the first bonding pad 121 of the first semiconductor chip 120. In the present embodiment, the first connection member 130 is formed of a bonding wire.

제1몰드부(140)는 제2볼랜드(114)를 포함한 제1기판(110) 타면(110B) 가장자리를 노출하고 제1반도체칩(120)을 포함한 제1기판(110) 타면(110B) 중심부를 밀봉한다. 제2몰드부(150)는 제1연결부재(130)를 포함한 개구(111)를 밀봉한다. 본 실시예에서, 제1, 제2몰드부(140, 150)는 에폭시 몰드 컴파운드(EMC)로 구성된다.The first mold part 140 exposes the edge of the other surface 110B of the first substrate 110 including the second borland 114, and the center of the other surface 110B of the first substrate 110 including the first semiconductor chip 120. Seal it. The second mold part 150 seals the opening 111 including the first connection member 130. In the present embodiment, the first and second mold parts 140 and 150 are made of epoxy mold compound (EMC).

제1외부접속단자(160)는 제2볼랜드(114)에 장착된다. 본 실시예에서, 제1외부접속단자(160)는 솔더볼로 형성된다.The first external connection terminal 160 is mounted to the second borland 114. In the present embodiment, the first external connection terminal 160 is formed of solder balls.

상부 패키지(200)는 제1기판(110)의 제1볼랜드(113)들 상에 실장된다.The upper package 200 is mounted on the first borland 113 of the first substrate 110.

본 실시예에서, 상부 패키지(200)는, 제2기판(210), 제2반도체 칩(220) 및 다수개의 제2외부접속단자(250)들을 포함한다. 그 외에, 제2연결부재(230), 제3몰드부(240)를 더 포함한다.In the present embodiment, the upper package 200 includes a second substrate 210, a second semiconductor chip 220, and a plurality of second external connection terminals 250. In addition, the apparatus further includes a second connection member 230 and a third mold part 240.

제2기판(210)은, 예를 들어, 플레이트 형상을 갖는다. 플레이트 형상을 갖는 제2기판(210)은 상면(210A) 및 하면(210B)을 갖는다. 제2기판(210) 하면(210B)은 하부 패키지(100)의 제1기판(110) 일면(110A)과 마주한다. 제2기판(210)은 복수개의 층들로 이루어진 회로 패턴들 및 서로 다른 층에 배치된 회로 패턴들을 연결하는 바아(via)를 포함할 수 있다. The second substrate 210 has a plate shape, for example. The second substrate 210 having a plate shape has an upper surface 210A and a lower surface 210B. The lower surface 210B of the second substrate 210 faces one surface 110A of the first substrate 110 of the lower package 100. The second substrate 210 may include a bar connecting circuit patterns formed of a plurality of layers and circuit patterns disposed on different layers.

제2기판(210) 상면(210A) 가장자리에는 제2접속패드(211)가 형성되고, 제2기판(210) 하면(210B)에는 제3볼랜드(212)들이 형성된다. 제2접속패드(211), 제3볼랜드(212)들은 제2기판(210)에 형성된 상기 회로 패턴들 및 비아 등을 통해 상호 연결된다. Second connection pads 211 are formed at the edges of the second substrate 210, the top surface 210A, and third ball lands 212 are formed on the bottom surface 210B of the second substrate 210. FIG. The second connection pad 211 and the third borland 212 are connected to each other through the circuit patterns and vias formed on the second substrate 210.

제3볼랜드(212)들은 각각 제1기판(110)의 제1볼랜드(113)들에 대응된다. 대응되는 제1볼랜드(113) 및 제3볼랜드(212)는 상호 마주하며 미러(mirror) 형태로 형성된다.The third borlands 212 correspond to the first borlands 113 of the first substrate 110, respectively. The first borland 113 and the third borland 212 corresponding to each other are formed in a mirror form.

제2반도체 칩(220)은 제2접속패드(211) 안쪽 제2기판(210) 상면(210A)에 제2접착부재(260)를 매개로 부착된다. The second semiconductor chip 220 is attached to the upper surface 210A of the second substrate 210 inside the second connection pad 211 via the second adhesive member 260.

제2반도체 칩(220)은 제2기판(210)과 대응하는 제1면 및 제1면과 대향하는 제2면을 갖는다. 제2반도체 칩(220) 제1면은 제2접착부재(260)를 매개로 제2기판(210)에 부착되고, 제2반도체 칩(220) 제2면에는 제2본딩패드(221)가 형성된다. 본 실시예에서, 제2본딩 패드(221)는 제2반도체 칩(220) 제2면 가장자리에 형성된다.The second semiconductor chip 220 has a first surface corresponding to the second substrate 210 and a second surface opposite to the first surface. The first surface of the second semiconductor chip 220 is attached to the second substrate 210 via the second adhesive member 260, and the second bonding pad 221 is formed on the second surface of the second semiconductor chip 220. Is formed. In the present embodiment, the second bonding pad 221 is formed at the edge of the second surface of the second semiconductor chip 220.

제2연결부재(230)는 제2기판(210)의 제2접속패드(211)와 제2반도체 칩(220)의 제2본딩패드(221)를 연결한다. 본 실시예에서, 제2연결부재(230)는 본딩 와이어로 형성된다.The second connection member 230 connects the second connection pad 211 of the second substrate 210 and the second bonding pad 221 of the second semiconductor chip 220. In this embodiment, the second connection member 230 is formed of a bonding wire.

제3몰드부(240)는 제2반도체 칩(220) 및 제2연결부재(230)를 포함한 제2기판(210) 상면(220A)을 밀봉한다. 제3몰드부(240)는 에폭시몰드 컴파운드(EMC)를 포함한다.The third mold part 240 seals the upper surface 220A of the second substrate 210 including the second semiconductor chip 220 and the second connection member 230. The third mold part 240 includes an epoxy mold compound (EMC).

제2외부접속단자(250)들은 제2기판(210)의 제3볼랜드(212)와 제1기판(210)의 제1볼랜드(113) 사이에 각각 형성되어, 이들을 전기적 및 물리적으로 연결한다. 본 실시예에서, 제2외부접속단자(250)는 솔더볼로 형성된다.The second external connection terminals 250 are formed between the third borland 212 of the second substrate 210 and the first borland 113 of the first substrate 210 to electrically and physically connect them. In the present embodiment, the second external connection terminal 250 is formed of a solder ball.

이상에서 설명한 바에 의하면, 하부 패키지의 제1반도체 칩이 상부 패키지와 반대면에 형성되어 하부 패키지의 기판 전 영역에 걸쳐서 외부접속단자를 배치할 수 있다. 따라서, 하부 패키지와 상부 패키지가 보다 견고하게 결속되어 몰딩 공정이나 열가공 공정에서 반도체 패키지의 휨이 억제되므로 조인트 신뢰성이 향상된다. 또한, 하부 패키지의 제1반도체 칩에서 발생되는 열이 보다 효과적으로 방출되어 적층 반도체 패키지의 방열 특성이 향상된다. As described above, the first semiconductor chip of the lower package is formed on the surface opposite to the upper package, so that the external connection terminals can be disposed over the entire area of the substrate of the lower package. Therefore, the lower package and the upper package are more firmly bound so that bending of the semiconductor package is suppressed in the molding process or the heat processing process, thereby improving joint reliability. In addition, heat generated from the first semiconductor chip of the lower package is more effectively released, thereby improving heat dissipation characteristics of the multilayer semiconductor package.

앞서 설명한 본 발명의 상세한 설명에서는 본 발명의 실시예들을 참조하여 설명하였지만, 해당 기술분야의 숙련된 당업자 또는 해당 기술분야에 통상의 지식을 갖는 자라면 후술 될 특허청구범위에 기재된 본 발명의 사상 및 기술 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.In the detailed description of the present invention described above with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the present invention described in the claims and It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

100 : 하부 패키지
200 : 상부 패키지100: lower package
200: top package

Claims (6)

중심부에 일면 및 상기 일면과 대향하는 타면을 관통하는 개구가 형성되고 상기 일면에 상기 개구를 따라서 제1접속패드가 형성되고 상기 일면에 상기 제1접속패드와 이격되어 다수개의 제1볼랜드들이 분포된 제1기판, 상기 제1기판 타면에 부착되며 상기 개구에 대응되는 제1본딩패드를 갖는 제1반도체 칩, 상기 제1기판의 제1접속패드와 상기 제1반도체 칩의 제1본딩 패드를 연결하는 제1연결부재를 포함하는 하부 패키지;및
상기 하부 패키지의 상기 제1볼랜드 상에 실장되는 상부 패키지;
를 포함하는 것을 특징으로 하는 적층 반도체 패키지.An opening penetrating through one surface and the other surface facing the one surface is formed in the center portion, and a first connection pad is formed along the opening on one surface thereof, and the first connection pad is spaced apart from the first connection pad on the one surface to distribute a plurality of first borlands. A first semiconductor chip attached to a first substrate, the other surface of the first substrate and having a first bonding pad corresponding to the opening, connecting the first connection pad of the first substrate to the first bonding pad of the first semiconductor chip A lower package including a first connection member;
An upper package mounted on the first borland of the lower package;
Laminated semiconductor package comprising a. 제 1항에 있어서,
상기 하부 패키지는,
상기 제1반도체 칩을 포함한 상기 제1기판 타면을 밀봉하는 제1몰드부;및
상기 제1연결부재를 포함한 상기 개구를 밀봉하는 제2몰드부;
를 더 포함하는 것을 특징으로 하는 적층 반도체 패키지.The method of claim 1,
The lower package,
A first mold part sealing the other surface of the first substrate including the first semiconductor chip; and
A second mold part sealing the opening including the first connection member;
Laminated semiconductor package, characterized in that it further comprises. 제 1항에 있어서,
상기 제1연결부재는 본딩 와이어를 포함하는 것을 특징으로 하는 적층 반도체 패키지.The method of claim 1,
The first connecting member is a laminated semiconductor package, characterized in that it comprises a bonding wire. 제 1항에 있어서,
상기 상부 패키지는,
상면 및 하면을 가지며 상기 상면에 제2접속패드가 형성되고 상기 하면에 상기 하부 패키지의 제1볼랜드들에 대응되는 제3볼랜드들이 형성된 제2기판;
상기 제2기판 상면 상에 형성되며 제2접속패드와 연결되는 제2본딩패드를 갖는 제2반도체 칩;및
상기 제1볼랜드들 및 상기 제1볼랜드들 각각에 대응되는 제3볼랜드들을 연결하는 외부접속단자들;
을 포함하는 것을 특징으로 하는 적층 반도체 패키지.The method of claim 1,
The upper package,
A second substrate having an upper surface and a lower surface, and having a second connection pad formed on the upper surface, and having third ball lands formed on the lower surface corresponding to the first borlands of the lower package;
A second semiconductor chip formed on an upper surface of the second substrate and having a second bonding pad connected to a second connection pad; and
External connection terminals connecting the first borland and third borland corresponding to each of the first borland;
Laminated semiconductor package comprising a. 제 4항에 있어서,
상기 제2외부접속단자는 솔더볼을 포함하는 것을 특징으로 하는 반도체 패키지.The method of claim 4, wherein
The second external connection terminal is a semiconductor package, characterized in that it comprises a solder ball. 제 4항에 있어서,
상기 상부 패키지는,
상기 제2기판의 제2접속패드와 상기 제2반도체 칩의 제2본딩패드를 연결하는 제2연결부재;및
상기 제2반도체 칩을 포함한 상기 제2기판 상면을 밀봉하는 제3몰드부;
를 더 포함하는 것을 특징으로 하는 적층 반도체 패키지.The method of claim 4, wherein
The upper package,
A second connection member connecting the second connection pad of the second substrate and the second bonding pad of the second semiconductor chip; and
A third mold part sealing an upper surface of the second substrate including the second semiconductor chip;
Laminated semiconductor package, characterized in that it further comprises.
KR1020100053357A 2010-06-07 2010-06-07 Stacked semiconductor package KR20110133769A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014098324A1 (en) * 2012-12-17 2014-06-26 하나마이크론(주) Semiconductor device package
KR20150046822A (en) * 2013-10-22 2015-05-04 삼성전자주식회사 Semiconductor package and method of fabricating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014098324A1 (en) * 2012-12-17 2014-06-26 하나마이크론(주) Semiconductor device package
KR20150046822A (en) * 2013-10-22 2015-05-04 삼성전자주식회사 Semiconductor package and method of fabricating the same

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