KR20110108033A - Organic light emitting diode display device and stereoscopic image display using the same - Google Patents

Organic light emitting diode display device and stereoscopic image display using the same Download PDF

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KR20110108033A
KR20110108033A KR1020100027299A KR20100027299A KR20110108033A KR 20110108033 A KR20110108033 A KR 20110108033A KR 1020100027299 A KR1020100027299 A KR 1020100027299A KR 20100027299 A KR20100027299 A KR 20100027299A KR 20110108033 A KR20110108033 A KR 20110108033A
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light emitting
node
organic light
emitting diode
electrode connected
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KR1020100027299A
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KR101596970B1 (en
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김범식
한인효
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엘지디스플레이 주식회사
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Abstract

The present invention relates to an organic light emitting diode display device, comprising: data lines and scan lines crossing each other; And light emitting cells arranged in a matrix form defined by the data lines and the scan lines. Each of the light emitting cells includes an organic light emitting diode; A driving TFT controlling an amount of current flowing between the organic light emitting diodes according to a voltage of a gate electrode; A storage capacitor connected between a first node to which a reference voltage and a data voltage are applied, and a second node connected to the gate electrode of the driving TFT; And a first switch TFT which turns off the driving TFT by applying a high potential power voltage to the gate electrode of the driving TFT during a BDI period in which light emission of the organic light emitting diode is suppressed.

Description

ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND STEREOSCOPIC IMAGE DISPLAY USING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting diode display device for compensating threshold voltage variations and pixel power variations of a driving thin film transistor (TFT) for driving an organic light emitting diode (OLED) and a stereoscopic image display device using the same.

Various flat panel displays (FPDs) are being developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Such flat panel displays include liquid crystal displays (hereinafter referred to as "LCDs"), field emission displays (FEDs), plasma display panels (hereinafter referred to as "PDPs") and electric fields. Light emitting devices; and the like.

Electroluminescent devices are classified into inorganic electroluminescent devices and organic light emitting diode devices (OLEDs) according to the material of the light emitting layer. Self-emitting devices are self-luminous devices that have a high response speed and high luminous efficiency, luminance, and viewing angle. have.

The organic light emitting diode display may be driven by a driving method such as voltage driving, voltage compensation, current driving, digital driving, or external compensation, and in recent years, a voltage compensation driving method is most frequently selected.

The conventional voltage compensation driving method compensates the threshold voltage of the driving TFT by sensing the threshold voltage of the driving TFT after initializing the gate electrode voltage (or gate node voltage) of the driving TFT before emitting the organic light emitting diode OLED. In the conventional voltage compensation driving method, the time for initializing the gate node of the driving TFT is limited. Although the charge of the gate node of the driving TFT must be discharged uniformly within a limited initialization time, the initialization of the gate node may be uneven depending on the position of the panel or the characteristic variation of the device, and thus the image quality level may be degraded.

Black data insertion (BDI) for inserting black data into an input image is known as a method of improving a motion picture response time (MPRT) of a display device. However, in the conventional organic light emitting diode display device, since the gate node of the driving TFT cannot be directly controlled, it is difficult to implement BDI.

The present invention provides an organic light emitting diode display device suitable for driving a BDI and a stereoscopic image display device using the same.

The organic light emitting diode display according to the present invention includes data lines and scan lines crossing each other; And light emitting cells arranged in a matrix form defined by the data lines and the scan lines.

The stereoscopic image display device includes an organic light emitting diode display including data lines and scan lines crossing each other, and light emitting cells arranged in a matrix defined by the data lines and the scan lines; In 2D mode, while passing the light of the 2D image displayed on the organic light emitting diode display as it is, while in the 3D mode 2D for separating the light path of the left eye image and the right eye image displayed on the organic light emitting diode display / 3D switching optics; And 3D glasses including a left eye filter for transmitting light of the left eye image and a right eye filter for transmitting light of the right eye image.

Each of the light emitting cells includes an organic light emitting diode; A driving TFT controlling an amount of current flowing between the organic light emitting diodes according to a voltage of a gate electrode; A storage capacitor connected between a first node to which a reference voltage and a data voltage are applied, and a second node connected to the gate electrode of the driving TFT; And a first switch TFT which turns off the driving TFT by applying a high potential power voltage to the gate electrode of the driving TFT during a BDI period in which light emission of the organic light emitting diode is suppressed.

According to the present invention, the BDI section can be set by directly controlling the gate node of the driving TFT, and the BDI section can be freely changed, thereby improving the video response time of the organic light emitting diode display.

In addition, the present invention can implement a three-dimensional image display device using the organic light emitting diode display device, it is possible to improve the display quality of the stereoscopic image by inserting a BDI section between the left eye image and the right eye image.

Furthermore, the present invention can compensate for the variation of the threshold voltage of the driving TFT and the fluctuation of the high potential power voltage, and set the initialization period of the light emitting cell to one or more horizontal periods over two times, resulting from the position of the display panel or the variation of TFT characteristics. Initialization errors can be minimized.

1 is a block diagram illustrating an organic light emitting diode display device according to an exemplary embodiment of the present invention.
FIG. 2 is a circuit diagram showing in detail the light emitting cell shown in FIG. 1.
FIG. 3 is a waveform diagram illustrating driving signals of the light emitting cell shown in FIG. 2.
4 to 7 are circuit diagrams showing the operation of a light emitting cell step by step.
8 is a waveform diagram showing a BDI control method of the present invention.
9 is a diagram illustrating a stereoscopic image display device according to an exemplary embodiment of the present invention.
FIG. 10 is a timing diagram illustrating an example of BDI implementation of the stereoscopic image display shown in FIG. 9.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Component names used in the following description may be selected in consideration of ease of specification, and may be different from actual product part names.

1 to 3, an organic light emitting diode display device according to an exemplary embodiment of the present invention includes a display panel 10, a data driver 20, a scan driver 30, and a timing controller 40. Equipped.

The display panel 10 includes data lines and scan lines that cross each other, and light emitting cells 11 arranged in a matrix defined by the data lines and the scan lines.

The data driver 20 converts the digital video data RGB into the data voltage VD as shown in FIG. 3 under the control of the timing controller 40 and supplies the same to the data lines.

The scan driver 30 sequentially supplies the initialization pulses INI1 and INI2, the programming scan pulse PRO, and the emission control pulse EM to the scan lines under the control of the timing controller 40. The scan driver 30 supplies a first shift register and a second initialization pulse INI2 to the second scan lines SCAN2 to sequentially supply the first initialization pulse INI1 to the first scan lines SCAN1. A second shift register for sequentially supplying, a third shift register for sequentially supplying a programming scan pulse PRO synchronized with the data voltage VD to the third scan lines SCAN3, and an emission control pulse EM ) Includes a fourth shift register for sequentially supplying the second scan lines to the fourth scan lines SCAN4. The first shift register generates a first initialization pulse INI1 in response to the first start pulse. The second shift register generates a second initialization pulse INI2 in response to the second start pulse generated after the first start pulse. The third shift register generates a programming scan pulse PRO in response to the third start pulse generated immediately after the second start pulse. The fourth shift register generates the emission control pulse EM in response to the fourth start pulse generated immediately after the third start pulse.

The timing controller 40 supplies digital video data RGB to the data driver 20. In addition, the timing controller 40 generates timing control signals for controlling the operation timing of the data driver 20 and the scan driver 30 based on a timing signal input from an external device such as a vertical / horizontal synchronization signal and a clock signal. . For example, the timing controller 40 generates start pulses to control the scan start timing of the shift register of the scan driver 30.

Each of the light emitting cells 11 includes an organic light emitting diode OLED, seven TFTs M1 to TM6 and DT, and a storage capacitor Cstg. The light emitting cells 11 are commonly supplied with driving voltages such as a high potential power voltage VDD, a base voltage (or a low potential power voltage GND), a reference voltage Ref, and the like.

The high potential power supply voltage VDD is a DC voltage of 10V or more. The reference voltage Ref is set to a voltage at which the difference from the base voltage GND is less than the threshold voltage of the organic light emitting diode OLED. For example, the reference voltage Ref may be set to a voltage of about 2V. Therefore, when the reference voltage Ref is applied to the anode electrode of the organic light emitting diode OLED and the reference voltage Ref is applied to the cathode electrode of the organic light emitting diode OLED, the organic light emitting diode OLED is not turned on. Because it does not emit light.

 The reference voltage Ref may be set to a negative voltage so that a reverse bias can be applied to the organic light emitting diode OLED at the initialization of the driving TFT connected to the organic light emitting diode OLED. In this case, since the reverse bias is periodically applied to the organic light emitting diode OLED, the deterioration of the organic light emitting diode OLED can be reduced and its life can be extended.

The TFTs M1 to M6 and DT may be implemented as p-type MOS TFTs and n-type MOS TFTs. In addition, the TFTs M1 to M6 and DT may be implemented by a combination of a p-type MOS TFT and an n-type MOS TFT using a CMOS (Complementary Metal Oxide Semiconductor) process. 2 shows an example of TFTs implemented with a p-type MOS TFT, and it should be noted that the TFTs of the present invention are not limited to the p-type MOS TFT.

The first switch TFT M1 is connected to the gate electrode of the driving TFT DT in response to the first initialization pulse INI1 of the low logic level generated during the first time t1 ( Or a current path is formed between the gate node n2 and the high potential power voltage supply line. The drain electrode of the first switch TFT M1 is connected to the second node n2, and the source electrode thereof is connected to the high potential power supply voltage supply line VDD. The gate electrode of the first switch TFT M1 is connected to the first scan line SCAN1 to which the first initialization pulse INI1 is supplied.

The second switch TFT M2 is supplied with an anode electrode of the organic light emitting diode OLED and a reference voltage Ref in response to the second initialization pulse INI2 of the low logic level generated during the second time t2. A current path is formed between the fourth nodes n4. The source electrode of the second switch TFT M2 is connected to the fourth node n4 to which the reference voltage Ref is supplied, and the drain electrode thereof is connected to the anode electrode of the organic light emitting diode OLED. The gate electrode of the second switch TFT M2 is connected to the second scan line SCAN2 to which the second initialization pulse INI2 is supplied.

The third switch TFT M3 is a current between the data line DATA1 and the first node n1 in response to a low logic level programming scan pulse PRO generated during the second and third times t2 and t3. Form a pass. The source electrode of the third switch TFT M3 is connected to the data line DATA1, and the drain electrode thereof is connected to the first node n1. The gate electrode of the third switch TFT M3 is connected to the third scan line SCAN3 to which the programming scan pulse PRO is supplied.

The fourth switch TFT M4 is disposed between the second node n2 and the third node n3 in response to the low logic level programming scan pulse PRO generated during the second and third times t2 and t3. Form a current path. The second node n2 is formed between the gate electrode of the driving TFT DT and one electrode of the storage capacitor Cstg. The third node n3 is formed between the drain electrode of the driving TFT DT and the source electrode of the sixth switch TFT M6. The source electrode of the fourth switch TFT M4 is connected to the second node n2, and the drain electrode thereof is connected to the third node n3. The gate electrode of the fourth switch TFT M4 is connected to the third scan line SCAN3 to which the programming scan pulse PRO is supplied.

The fifth switch TFT M5 blocks the current path between the first node n1 and the fourth node n4 in response to the light emission control pulse EM of the high logic level generated during the third time t3. The current path is formed between the first node n1 and the fourth node n4 at times t1 to t2 and t4 other than the third time t3. The source electrode of the fifth switch TFT M5 is connected to the first node n1, and the drain electrode thereof is connected to the fourth node n4. The gate electrode of the fifth switch TFT M5 is connected to the fourth scan line SCAN4 to which the emission control pulse EM is supplied.

The sixth switch TFT M6 is a current path between the third node n3 and the anode electrode of the organic light emitting diode OLED in response to the high logic level light emission control pulse EM generated during the third time t3. Is blocked, and a current path is formed between the third node n3 and the anode electrode of the organic light emitting diode OLED for a time t1 to t2 and t4 other than the third time t3. The source electrode of the sixth switch TFT M6 is connected to the third node n3, and the drain electrode thereof is connected to the anode electrode of the organic light emitting diode OLED. The gate electrode of the sixth switch TFT M6 is connected to the fourth scan line SCAN4 to which the emission control pulse EM is supplied.

The driving TFT DT adjusts the amount of current flowing between the high potential power supply voltage supply line and the organic light emitting diode OLED according to the voltage (or gate node voltage) of the second node. The source electrode of the driving TFT DT is connected to the high potential power supply voltage supply line supplied with the high potential power supply voltage, and the drain electrode thereof is connected to the third node n3. The gate electrode of the driving TFT DT is connected to the second node N2.

The storage capacitor Cstg is connected between the first node n1 and the second node n2. The storage capacitor Cstg stores the threshold voltage of the driving TFT DT and stores the data voltage compensated by the threshold voltage of the driving TFT DT.

A multilayer organic compound layer is formed between the anode electrode and the cathode electrode of the organic light emitting diode OLED. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (Electron Injection layer, EIL). The organic light emitting diode OLED emits light with a brightness proportional to the current supplied through the driving TFT DT and the sixth TFT M6. The anode electrode of the organic light emitting diode OLED is connected to the sixth switch TFT M6, and the cathode electrode thereof is connected to the ground voltage supply line to which the ground voltage GND is supplied.

The operation of the light emitting cell 11 will be described step by step as follows.

During the first time t1, the first initialization pulse IN1 having a low logic level is applied to the first scan line SCAN1. The first switch TFT M1 is turned on in response to the first initialization pulse INI1. The fifth and sixth switch TFTs M5 and M6 remain in an on state according to the low logic level voltage of the fourth scan line SCAN4 for the first time t1. The second, third and fourth switch TFTs M2 to M4 have a first time since the voltages of the second and third scan lines SCAN2 and SCAN3 maintain a high logic level voltage during the first time t1. It remains off for (t1). As a result, the circuit of the light emitting cell 11 operates as shown in FIG. 4 so that the voltage of the second node n2 is initialized to the high potential power voltage VDD, and the voltage of the first node n1 is the reference voltage Ref. Is initialized to During the first time t1, the driving TFT DT is turned off due to the gate voltage of the high potential power supply voltage VDD, so that no current is supplied to the organic light emitting diode OLED. Therefore, during the first time t1, the first and second nodes n1 and n2 are first initialized and the organic light emitting diode OLED does not emit light.

During the second time t2, immediately after the second initialization pulse INI2 of the low logic level is applied to the second scan line SCAN2, the programming scan pulse PRO of the low logic level is applied to the third scan line SCAN3. ) Is applied. During the second time t2, the voltage of the first scan line SCAN1 changes to a voltage of a high logic level. During the second time t2, the second switch TFT M2 is turned on in response to the second initialization pulse INI2, and the third and fourth switch TFTs M3 and M4 are programmed scan pulses PRO. Is turned on in response to The fifth and sixth switch TFTs M5 and M6 remain on for a second time t2. As a result, the circuit of the light emitting cell 11 operates as shown in FIG. 5 for a second time t2, so that the voltages of the first and second nodes n1 and n2 and the voltage of the anode electrode of the organic light emitting diode OLED are shown. Is initialized to the reference voltage Ref. During the second time t2, the organic light emitting diode OLED does not emit light while maintaining the turn-off state because the anode voltage is low as the reference voltage Ref.

The initialization time of the light emitting cell 11 may be allocated to a time equal to or greater than one horizontal period including the first and second times t1 and t2. Therefore, the present invention can sufficiently secure the initialization time of the light emitting cells 11, thereby minimizing the initialization error of the light emitting cells 11 due to the position of the display panel 10 or the characteristic variation of the TFT elements.

During the third time t3, the voltages of the second and third scan lines SCAN2 and SCAN3 maintain a low logic level, and the data voltage VD is supplied to the data line DATA1. During the third time, the light emission control pulse EM of the high logic level is applied to the fourth scan line SCAN4, and the voltage of the first scan line SCAN1 maintains the high logic level. The second to fourth switch TFTs M2 to M4 maintain an on state for a third time t3. During the third time t3, the first switch TFT M1 remains in the off state, and the fifth and sixth switch TFTs M5 and M6 are turned off in response to the emission control pulse EM. As a result, the circuit of the light emitting cell 11 operates as shown in FIG. 6 for a third time t3 so that the data voltage VD is applied to the first node n1 and the driving TFT DT is applied to the second node n2. Threshold voltage is applied. Therefore, the storage capacitor Cstg stores the difference voltage between the data voltage VD and the threshold voltage of the driving TFT DT to compensate for the data voltage VD by the threshold voltage of the driving TFT DT. The third time t3 is set to approximately one horizontal period 1H.

During the fourth time t4, the voltages of the second and third scan lines SCAN2 and SCAN3 change to a high logic level, and the voltage of the first scan line SCAN1 remains at a high logic level. During the fourth time t4, the voltage of the fourth scan line SCAN4 changes to a low logic level. The fifth and sixth switch TFTs M5 and M6 are turned on for the third time t4, and the first to fourth switch TFTs M1 to M4 maintain an off state. As a result, the circuit of the light emitting cell 11 operates as shown in FIG. 7 for a fourth time t4 to supply a current to the organic light emitting diode OLED. The fourth time t4 is the remaining period after subtracting one horizontal period from one frame period. Therefore, the organic light emitting diode OLED emits light for approximately one frame period. The current I OLED of the organic light emitting diode OLED is not affected by the threshold voltage deviation of the driving TFT DT or the high potential power voltage VDD as shown in Equation 1 below.

Figure pat00001

Here, 'k' is a constant value that functions as a function of the mobility μ of the driving TFT DT, the parasitic capacitance Cox, and the channel ratio W / L.

On the other hand, the TFTs M1 to M6 and DT are not limited to the p-type MOS TFT but can also be implemented as an n-type MOS TFT. In this case, the drive signal waveforms of FIG. 3 are generated out of phase.

The present invention directly controls the gate node of the driving TFT DT by controlling the first switch TFT M1 with the first initialization pulse INI1. As a result, the present invention can implement the BDI of the organic light emitting diode display as shown in FIG.

Referring to FIG. 8, when the first and second initialization pulses INI1 and INI2 are normally generated and the programming scan pulse PRO is not generated, the gate node voltage of the driving TFT DT is the high potential power voltage VDD. Rises. Therefore, in the BDI period in which the programming scan pulse PRO is not generated, the driving TFT DT is maintained in an off state so that no current flows in the organic light emitting diode OLED. The BDI interval is a time between the rising time of the initialization pulse IN1 without the programming scan pulse PRO and the rising time of the programming scan pulse PRO.

The present invention can implement a stereoscopic image display device using an organic light emitting diode display device as shown in FIG.

Referring to FIG. 9, the stereoscopic image display device of the present invention includes an organic light emitting diode display device 100, a 2D / 3D switching optical device 200, and 3D glasses 300.

Since the organic light emitting diode display 100 has been described above with reference to FIGS. 1 to 7, a detailed description thereof will be omitted.

The 2D / 3D switching optical device 200 is attached to the display screen of the OLED display device 100 so as to face the pixel array of the OLED display device 100. The 2D / 3D switching optical device 200 passes the light of the 2D image displayed on the organic light emitting diode display 100 in 2D mode as it is, while the left eye image displayed on the organic light emitting diode display 100 in 3D mode. Separates the light propagation path of the light from the right eye image. To this end, the 2D / 3D switching optical device 200 converts the light of the left eye image into the first polarization and the light of the right eye image into the second polarization in the 3D mode. It may be implemented as an active retarder including a liquid crystal layer that alternately transmits light of the light and the right eye image.

The 3D glasses 300 includes a left eye polarization filter (or left eye liquid crystal shutter) for transmitting the light of the left eye image to the left eye of the user, and a right eye polarization filter (or left eye liquid crystal shutter) for transmitting the light of the right eye image to the user's right eye. do. The user can see the light of the left eye image to the left eye by wearing 3D glasses, and can view the light of the right eye image as the right eye image so that the user can feel a stereoscopic image.

As shown in FIG. 10, the left eye image data RGB LEFT and the right eye image data RGB RIGHT may be supplied to the organic light emitting diode display 100 of the stereoscopic image display device as shown in FIG. 9 in time division. The organic light emitting diode display 100 addresses the left eye image data RGB LEFT to the light emitting cells 11 during the N (N is a positive integer) frame period, and then the right eye image data for the N + 1 th frame period. (RGB RIGHT ) is addressed to the light emitting cells (11). The left eye image and the right eye image may be simultaneously incident on the left eye (or the right eye) of the user due to the liquid crystal delay of the 2D / 3D switching optical device 200 or the 3D glasses 300. In this case, the user may feel inverted due to the crosstalk between the left eye image and the right eye image. Accordingly, the present invention time- divides each frame period into the address period of the image data RGB LEFT and RGB RIGHT and the BDI period as shown in FIG. 10.

As illustrated in FIG. 8, the BDI period may be changed by controlling the gate node of the driving TFT DT using the first initialization pulse INI1. The BDI section is set to a time longer than the response delay time of the 2D / 3D switching optical device 200 or the 3D glasses 300 and shorter than one frame period. For example, the BDI interval may be set to a time longer than 0% and within 95% of one frame period. During the BDI period, the organic light emitting diode display 100 sequentially supplies the signals shown in FIG. 8 to the scan lines of the display panel.

Due to the setting of the BDI interval, even if the response of the 2D / 3D switching optical device 200 or the 3D glasses 300 is delayed, only light of the left eye image is incident on the left eye of the user, and only light of the right eye image is incident on the right eye of the user.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10 display panel 11: light emitting cell
20: data driver 30: scan driver
40: timing controller 100: organic light emitting diode display device
200: 2D / 3D switching optical element 300: 3D glasses

Claims (9)

  1. Data lines and scan lines crossing each other; And
    Light emitting cells arranged in a matrix form defined by the data lines and the scan lines,
    Each of the light emitting cells,
    Organic light emitting diodes;
    A driving TFT controlling an amount of current flowing between the organic light emitting diodes according to a voltage of a gate electrode;
    A storage capacitor connected between a first node to which a reference voltage and a data voltage are applied, and a second node connected to the gate electrode of the driving TFT; And
    And a first switch TFT that turns off the driving TFT by applying a high potential power voltage to a gate electrode of the driving TFT during a BDI period for suppressing light emission of the organic light emitting diode. Organic light emitting diode display.
  2. The method of claim 1,
    The high potential power voltage, the base voltage, and the reference voltage are supplied to the light emitting cells.
    The reference voltage is an organic light emitting diode display device, characterized in that the difference between the base voltage is less than the threshold voltage of the organic light emitting diode.
  3. The method of claim 2,
    The driving TFT includes a source electrode connected to a high potential power voltage supply line supplied with the high potential power voltage, a drain electrode connected to a third node, and a gate electrode connected to the second node. Organic light emitting diode display.
  4. The method of claim 3, wherein
    And the first switch TFT forms a current path between the second node and the high potential power voltage supply line in response to a first initialization pulse having a low logic level generated during a first time. Device.
  5. The method of claim 4, wherein
    The first switch TFT includes a drain electrode connected to the second node, a source electrode connected to the high potential power voltage supply line, and a gate electrode connected to a first scan line to which the first initialization pulse is supplied. An organic light emitting diode display device.
  6. The method of claim 5, wherein
    Each of the light emitting cells,
    A second switch TFT forming a current path between an anode electrode of the organic light emitting diode and a fourth node supplied with the reference voltage in response to a second initialization pulse of a low logic level generated during a second time;
    A third switch TFT forming a current path between any one of the data lines and the first node in response to a low logic level programming scan pulse generated during the second and third times;
    A fourth switch TFT forming a current path between the second node and a third node in response to the low logic level programming scan pulse;
    Interrupting a current path between the first node and the fourth node in response to a high logic level light emission control pulse generated during the third time, and during the time other than the third time, the first node and the fourth node; A fifth switch TFT forming a current path between the nodes;
    Blocking a current path between the third node and the anode electrode of the organic light emitting diode in response to the light emission control pulse of the high logic level, and an anode of the third node and the organic light emitting diode for a time other than the third time An organic light emitting diode display device further comprising a sixth switch TFT forming a current path between the electrodes.
  7. The method according to claim 6,
    The second switch TFT includes a source electrode connected to the fourth node, a drain electrode connected to the anode electrode of the organic light emitting diode, and a gate electrode connected to a second scan line to which the second initialization pulse is supplied. ,
    The third switch TFT includes a source electrode connected to any one of the data lines, a drain electrode connected to the first node, and a gate electrode connected to a third scan line supplied with the programming scan pulse,
    The fourth switch TFT includes a source electrode connected to the second node, a drain electrode connected to the third node, and a gate electrode connected to the third scan line,
    The fifth switch TFT includes a source electrode connected to the first node, a drain electrode connected to the fourth node, and a gate electrode connected to a fourth scan line to which the emission control pulse is supplied.
    The sixth switch TFT includes a source electrode connected to the third node, a drain electrode connected to an anode electrode of the organic light emitting diode, and a gate electrode connected to the fourth scan line. Display.
  8. An organic light emitting diode display including data lines and scan lines crossing each other, and light emitting cells arranged in a matrix defined by the data lines and the scan lines;
    In 2D mode, while passing the light of the 2D image displayed on the organic light emitting diode display as it is, while in the 3D mode 2D for separating the light path of the left eye image and the right eye image displayed on the organic light emitting diode display / 3D switching optics; And
    3D glasses including a left eye filter for transmitting light of the left eye image and a right eye filter for transmitting light of the right eye image,
    Each of the light emitting cells,
    Organic light emitting diodes;
    A driving TFT controlling an amount of current flowing between the organic light emitting diodes according to a voltage of a gate electrode;
    A storage capacitor connected between a first node to which a reference voltage and a data voltage are applied, and a second node connected to the gate electrode of the driving TFT; And
    And a first switch TFT that turns off the driving TFT by applying a high potential power voltage to a gate electrode of the driving TFT during a BDI period for suppressing light emission of the organic light emitting diode. Stereoscopic image display.
  9. The method of claim 8,
    Each of the light emitting cells,
    A second switch TFT forming a current path between an anode electrode of the organic light emitting diode and a fourth node supplied with a reference voltage in response to a second initialization pulse of a low logic level generated during a second time;
    A third switch TFT forming a current path between any one of the data lines and the first node in response to a low logic level programming scan pulse generated during the second and third times;
    A fourth switch TFT forming a current path between the second node and a third node in response to the low logic level programming scan pulse;
    Interrupting a current path between the first node and the fourth node in response to a high logic level light emission control pulse generated during the third time, and during the time other than the third time, the first node and the fourth node; A fifth switch TFT forming a current path between the nodes;
    Blocking a current path between the third node and the anode electrode of the organic light emitting diode in response to the light emission control pulse of the high logic level, and an anode of the third node and the organic light emitting diode for a time other than the third time An organic light emitting diode display device further comprising a sixth switch TFT forming a current path between the electrodes.
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