KR20110084774A - Light emitting device, light emitting device package, and fabrication method of lgithe emitting device - Google Patents

Light emitting device, light emitting device package, and fabrication method of lgithe emitting device Download PDF

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KR20110084774A
KR20110084774A KR1020100004505A KR20100004505A KR20110084774A KR 20110084774 A KR20110084774 A KR 20110084774A KR 1020100004505 A KR1020100004505 A KR 1020100004505A KR 20100004505 A KR20100004505 A KR 20100004505A KR 20110084774 A KR20110084774 A KR 20110084774A
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layer
light emitting
emitting device
conductive semiconductor
semiconductor layer
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KR1020100004505A
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Korean (ko)
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KR101644501B1 (en
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이건교
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엘지이노텍 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50—Wavelength conversion elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Abstract

Embodiments relate to a light emitting device, a light emitting device package, and a light emitting device manufacturing method.
The light emitting device according to the embodiment, the substrate; A plurality of compound semiconductor layers including a first conductive semiconductor layer under the substrate, an active layer under the first conductive semiconductor layer, and a second conductive semiconductor layer under the active layer; A first electrode electrically connected to the first conductive semiconductor layer; A second electrode electrically connected to the second conductive semiconductor layer; And a first phosphor layer formed on the substrate.

Description

LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE, AND FABRICATION METHOD OF LGITHE EMITTING DEVICE}

Embodiments relate to a light emitting device, a light emitting device package, and a light emitting device manufacturing method.

Group III-V nitride semiconductors are spotlighted as core materials of light emitting devices such as light emitting diodes (LEDs) or laser diodes (LDs) due to their physical and chemical properties. The III-V nitride semiconductor is usually made of a semiconductor material having a composition formula of In x Al y Ga 1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1).

A light emitting diode (LED) is a kind of semiconductor device that transmits and receives a signal by converting electricity into infrared light or light using characteristics of a compound semiconductor.

 It is widely used as a light emitting device for obtaining light of an LED or LD using such a nitride semiconductor material, and has been applied as a light source of various products such as keypad light emitting part of a mobile phone, an electronic board, a display device, and a lighting device.

The embodiment provides a light emitting device in which a phosphor layer having a uniform thickness is attached to the top side and / or the bottom side of the light emitting element, and a method of manufacturing the same.

The embodiment provides a light emitting device package in which a light emitting device having a phosphor layer is packaged.

The light emitting device according to the embodiment, the substrate; A plurality of compound semiconductor layers including a first conductive semiconductor layer under the substrate, an active layer under the first conductive semiconductor layer, and a second conductive semiconductor layer under the active layer; A first electrode electrically connected to the first conductive semiconductor layer; A second electrode electrically connected to the second conductive semiconductor layer; And a first phosphor layer formed on the substrate.

The light emitting device according to the embodiment, a translucent substrate; A plurality of compound semiconductor layers including a first conductive semiconductor layer under the light transmissive substrate, an active layer under the first conductive semiconductor layer, and a second conductive semiconductor layer under the active layer; A transparent electrode layer formed on the second conductive semiconductor layer; A second electrode formed on the transparent electrode layer; A second phosphor layer formed on the transparent electrode layer; And a first electrode electrically connected to the first conductive semiconductor layer.

The light emitting device package according to the embodiment includes a substrate; A plurality of compound semiconductor layers including a first conductive semiconductor layer under the substrate, an active layer under the first conductive semiconductor layer, and a second conductive semiconductor layer under the active layer; A first electrode formed under the first conductive semiconductor layer; And a second electrode formed under the second conductive semiconductor layer. A phosphor layer formed on the top side of the light emitting element; A body having a plurality of lead terminals electrically connected to electrodes of the light emitting element; And a resin layer formed around the light emitting element.

In one embodiment, a method of manufacturing a light emitting device includes: forming a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer on a light transmissive substrate; Forming an electrode layer on the second conductive semiconductor layer; Exposing a portion of the first conductive semiconductor layer; Forming a first electrode on the first conductive semiconductor layer and a second electrode on the electrode layer; And forming a phosphor layer under the light transmissive substrate.

The embodiment can provide a white light emitting diode chip.

Embodiments can reduce color coordinate dispersion.

Embodiments can improve color uniformity.

The embodiment may provide a phosphor layer with a uniform thickness.

The embodiment can improve the reliability of the light emitting device and the package having the same.

1 is a side sectional view showing a light emitting device according to the first embodiment.
2 to 6 are views illustrating a manufacturing process of the light emitting device of FIG. 1.
7 is a view illustrating a package including the light emitting device of FIG. 1.
8 is a side sectional view showing a light emitting device according to the second embodiment.
9 is a side sectional view showing a light emitting device according to the third embodiment.
FIG. 10 is a view illustrating a package including the light emitting device of FIG. 9.
11 is a side sectional view showing a light emitting device according to the fourth embodiment.

In describing an embodiment, each layer, region, pattern, or structure is formed “on” or “under” a substrate, each layer (film), region, pad, or pattern. When described as "on" and "under" include both the meanings of "directly" and "indirectly". In addition, the criteria for the top or bottom of each layer will be described with reference to the drawings. In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size. Technical features of each embodiment are not limited to each embodiment and may be selectively applied to other embodiments.

Hereinafter, exemplary embodiments will be described with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a light emitting device according to a first embodiment.

Referring to FIG. 1, the light emitting device 100 may include a substrate 101, a compound semiconductor layer 110, a reflective electrode layer 130, a first electrode 141, a second electrode 143, and a phosphor layer 150. Include.

The light emitting device 100 includes a plurality of compound semiconductor layers, for example, an LED using a compound semiconductor layer of a group III-V group element, and the LED is a colored LED or UV light emitting light such as blue, green, or red. (Ultra violet) may be an LED. The emission light of the LED may be implemented using various semiconductors within the technical scope of the embodiment.

The substrate 101 is a growth substrate made of an insulating material or a conductive material on which the compound semiconductor can be grown. The substrate 101 may be selected from the group consisting of sapphire substrate (Al 2 O 3 ), GaN, SiC, ZnO, Si, GaP, InP, Ga 2 O 3 , GaAs, and the like. For the purpose of describing the following embodiments, the substrate 101 will be described as a translucent substrate such as sapphire.

A plurality of protrusions having a lens shape or a stripe shape may be formed on or below the substrate 101, and the protrusions may improve light extraction efficiency.

A semiconductor layer (not shown) may be formed below the substrate 101. The semiconductor layer may be formed as a layer or a pattern using a compound semiconductor of Group 2 to Group 6 elements, and the material may be ZnO, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP , AlGaInP, or the like. The semiconductor layer may be formed of, for example, a buffer layer or an undoped semiconductor layer, and the buffer layer reduces the difference in lattice constant from the substrate. The undoped semiconductor layer (not shown) may be formed of, for example, an undoped GaN-based semiconductor.

A plurality of compound semiconductor layers 110 are formed under the substrate 101, and the compound semiconductor layers 110 may include a first conductive semiconductor layer 112, an active layer 114, and a second conductive semiconductor layer ( 116).

A first conductive semiconductor layer 112 is formed below the substrate 101, an active layer 114 is formed below the first conductive semiconductor layer 112, and a second conductive layer is formed below the active layer 114. The type semiconductor layer 116 is formed. Another semiconductor layer may be further disposed above or below the respective layers, but is not limited thereto.

The first conductive semiconductor layer 112 is a compound semiconductor of a Group III-V group element doped with a first conductive dopant, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP and the like can be selected. When the first conductive type is an N type semiconductor, the first conductive type dopant includes an N type dopant such as Si, Ge, Sn, Se, Te, or the like. The first conductive semiconductor layer 112 may be formed as a single layer or a multilayer, but is not limited thereto. The first conductive semiconductor layer 112 may have the same area or greater than the active layer 114.

An active layer 114 is formed under the first conductive semiconductor layer 112, and the active layer 114 may be formed as a single quantum well structure or a multi quantum well structure. The active layer 114 is a period of the well layer and the barrier layer, for example, the period of the InGaN well layer / GaN barrier layer, the period of the InGaN well layer / AlGaN barrier layer, using a compound semiconductor material of group III-5 group element, And at least one period of a period of the InGaN well layer / InGaN barrier layer.

A conductive clad layer may be formed on or under the active layer 114, and the conductive clad layer may be formed of a GaN-based semiconductor having a band gap different from the band gap of the active layer 114. .

The second conductive semiconductor layer 116 is formed on the active layer 114, and the second conductive semiconductor layer 116 is a compound semiconductor of a group III-V group element doped with a second conductive dopant. GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP and the like. When the second conductive type is a P type semiconductor, the second conductive type dopant includes a P type dopant such as Mg and Zn. The second conductive semiconductor layer 116 may be formed as a single layer or a multilayer, but is not limited thereto.

In addition, a third conductive semiconductor layer, for example, a semiconductor layer having a polarity opposite to that of the second conductive type, may be formed under the second conductive semiconductor layer 116. Accordingly, the plurality of compound semiconductor layers 110 may have at least one of an N-P junction, a P-N junction, an N-P-N junction, and a P-N-P junction structure. In the following description, a structure in which the second conductive semiconductor layer 116 is disposed below the plurality of compound semiconductor layers 110 will be described as an example.

A reflective electrode layer 130 is formed under the second conductive semiconductor layer 116, and the reflective electrode layer 130 is in ohmic contact with the second conductive semiconductor layer 116 to reflect incident light. do.

The reflective electrode layer 130 may be formed in a single layer or multiple layers by selectively using a material consisting of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, Hf, and a combination thereof. Can be. The reflective electrode layer 130 may be formed in multiple layers by selectively using the above materials and conductive oxide materials such as IZO, IZTO, IAZO, IGZO, IGTO, AZO, and ATO. For example, IZO / Ni, AZO / Ag , IZO / Ag / Ni, AZO / Ag / Ni and the like. The reflective electrode layer 130 may not be formed, but is not limited thereto. A transparent electrode layer such as ITO may be disposed between the reflective electrode layer 130 and the second conductive semiconductor layer 116, but is not limited thereto.

A first electrode 141 is disposed under the first conductive semiconductor layer 112, and a second electrode 143 under the reflective electrode layer 130 and / or the second conductive semiconductor layer 116. ) Is placed. The first electrode 141 may include an electrode pad, and the second electrode 143 may include an electrode pattern having various shapes and may include an electrode pad.

The material of the first electrode 141 may be formed of a metal in which any one or a plurality of materials of Cu, Ti, Cr, Ta, Al, In, Pd, Co, Ni, Ge, Ag, and Au are mixed. It does not limit to this. The material of the second electrode 143 is at least one of Ti, Al, Al alloy, In, Ta, Pd, Co, Ni, Si, Ge, Ag, Ag alloy, Au, Hf, Pt, Ru, Au, and the like. Or it may be formed in a single layer or multiple layers using an alloy.

The phosphor layer 150 is formed on the upper surface of the substrate 101. The phosphor layer 150 may be coated by screen printing or may be formed as a photo luminescent film (PLF).

The phosphor layer 150 absorbs the first light emitted from the active layer 114 to emit a second light having a different wavelength. The second light emitted from the phosphor layer 150 may have a complementary color relationship with the first light emitted from the active layer 114, and may be a target color light through a mixture of the first light and the second light. You can make white light.

The phosphor layer 150 is formed to have a uniform thickness on the chip top side, and excites a part of the first light emitted from the active layer 114 to emit the second light, thereby making it possible to combine the target light through the substrate. The first light and the second light can be emitted. Here, since the area in which the first light and the second light are emitted is emitted to the entire area of the substrate 101, color coordinate dispersion can be reduced and color uniformity can be improved.

2 to 6 are views illustrating a light emitting device manufacturing process according to the first embodiment.

Referring to FIG. 2, the substrate 101 may be loaded into growth equipment, and may be formed in a layer or pattern form using a compound semiconductor of Group 2 to 6 elements thereon.

The growth equipment may be an electron beam evaporator, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporator sputtering, metal organic chemical vapor (MOCVD) deposition) and the like, and the like is not limited to such equipment.

The substrate 101 may include a conductive substrate or an insulating substrate. For example, the substrate 101 may include a sapphire substrate (Al 2 0 3 ), GaN, SiC, ZnO, Si, GaP, InP, Ga 2 0 3 , and GaAs. It may be selected from the group consisting of. An upper surface of the substrate 101 may have a lens or stripe-shaped protrusion. In addition, a semiconductor layer is formed on the substrate 101, and the semiconductor layer may be formed as a layer or a pattern using a compound semiconductor of Group 2 to Group 6 elements, for example, a ZnO layer (not shown) and a buffer layer (not shown). ), At least one layer of the undoped semiconductor layer (not shown) may be formed.

A first conductive semiconductor layer 112 is formed on the substrate 101, an active layer 114 is formed on the first conductive semiconductor layer 112, and a second conductive semiconductor layer is formed on the active layer 114. 116 is formed. Other layers may be disposed above or below each layer, but are not limited thereto.

The first conductive semiconductor layer 112 is a compound semiconductor of a Group III-V group element doped with a first conductive dopant, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP and the like can be selected.

An active layer 114 is formed on the first conductive semiconductor layer 112, and the active layer 114 may be formed in a single quantum well structure or a multiple quantum well structure.

A conductive clad layer may be formed on or under the active layer 114, and the conductive clad layer may be formed of a GaN-based semiconductor or a material having a higher band gap than the active layer.

The second conductive semiconductor layer 116 is formed on the active layer 114, and the second conductive semiconductor layer 116 is a compound semiconductor of a group III-V group element doped with a second conductive dopant. GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP and the like.

The first conductive semiconductor layer 112, the active layer 114, and the second conductive semiconductor layer 116 may be defined as a compound semiconductor layer 110. In addition, a third conductive semiconductor layer, for example, a semiconductor layer having a polarity opposite to that of the second conductive type, may be formed on the second conductive semiconductor layer 116. Accordingly, the plurality of compound semiconductor layers 110 may have at least one of an N-P junction, a P-N junction, an N-P-N junction, and a P-N-P junction structure. In the following description, a structure in which the second conductive semiconductor layer 116 is disposed on the upper layers of the compound semiconductor layers 110 will be described as an example.

Referring to FIG. 3, mesa etching is performed to expose the first conductive semiconductor layer 112 to each individual chip region.

The exposed region of the first conductive semiconductor layer 112 is a region for forming the first electrode, and may be disposed in a region such as one side or the center of the chip.

The reflective electrode layer 130 may be formed on the second conductive semiconductor layer 116. The reflective electrode layer 130 may be performed before or after the mesa etching, but is not limited thereto.

After forming the reflective electrode layer 130, an electrode forming process is performed.

Referring to FIG. 4, a second electrode 143 is formed on the reflective electrode layer 130, and a first electrode 141 is formed on the first conductive semiconductor layer 112. The second electrode 143 may be in direct contact with the reflective electrode layer 130 or may be in direct contact with the reflective electrode layer 130 and the second conductive semiconductor layer 116. Here, an electrode groove is formed in the reflective electrode layer 130 so that the second electrode 143 and the second conductive semiconductor layer 116 may be in contact with each other.

The reflective electrode layer 130 may be in ohmic contact with the second conductive semiconductor layer 116, and may diffuse current into all regions. That is, the reflective electrode layer 130 functions as a current spreading layer and a light reflecting layer.

The reflective electrode layer 130 may be formed in a single layer or multiple layers by selectively using a material consisting of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, Hf, and a combination thereof. Can be. The reflective electrode layer 130 may be formed in multiple layers by selectively using the above materials and conductive oxide materials such as IZO, IZTO, IAZO, IGZO, IGTO, AZO, and ATO. For example, IZO / Ni, AZO / Ag , IZO / Ag / Ni, AZO / Ag / Ni and the like. The reflective electrode layer 130 may not be formed, but is not limited thereto.

Referring to FIG. 5, the substrate 101 is rotated to be disposed toward the top. In this case, a protective sheet or the like may be disposed under the chip to prevent damage to the electrode or the semiconductor layer under the chip.

The top surface of the substrate 101 may be wrapped and / or polished. The thickness of the substrate 101 may be about 100 ~ 400um, but is not limited thereto.

The phosphor layer 150 may be formed on the upper surface of the substrate 101. The phosphor layer 150 may form, for example, a liquid resin material in which phosphors are mixed by screen printing. The phosphor layer 150 may be formed to have a uniform thickness on the upper surface of the substrate 101.

The phosphor layer 150 may include phosphors of at least one color among phosphors such as yellow phosphors, green phosphors, and red phosphors.

The first light emitted from the active layer 114 may emit light in a spectrum such as a blue wavelength, a UV wavelength, a red wavelength, a green wavelength, and the second light emitted from the phosphor layer 150 may emit the first light. The light is absorbed and excited to emit light, and the first light and the second light may be mixed to be implemented as light of a target color. For example, when the first light is blue light and the second light is yellow light, the target light may be white light. The combination of the phosphor layer 150 and the light emitted from the active layer 112 may be variously changed within the technical scope of the embodiment.

Referring to Figures 5 and 6, they are separated into individual chip sizes. The separation into individual chip sizes may use a dicing process or a breaking process, but is not limited thereto.

FIG. 7 is a diagram illustrating a light emitting device package including FIG. 1 according to a second embodiment.

Referring to FIG. 7, the light emitting device package 200 includes a cavity 215 having an open upper portion in the body 210, and mounts the light emitting device 100 in the cavity 215.

A plurality of lead terminals 201 and 203 are disposed in the cavity 215, and the plurality of lead terminals 201 and 203 are separated by the separating part 217 of the body 210, and a lower surface thereof is the same as the bottom surface of the body. It will form a plane.

In the light emitting device 100, as illustrated in FIG. 1, the phosphor layer 150 is formed on the chip top side, and the first electrode 141 and the second electrode 143 protrude downward from the bottom of the chip. . The first electrode 141 and the second electrode 143 are mounted on the lead terminals 201 and 203 using the conductive bumps 205. That is, the light emitting device 100 is mounted on the lead terminals 201 and 203 in a flip chip method.

The resin layer 220 is formed in the cavity 215, and the resin layer 220 may use a material such as silicon or epoxy. Phosphor may be added to the resin layer 220, and the phosphor may have a complementary color relationship with the phosphor layer 150 or a complementary color relationship with light emitted from the active layer, but is not limited thereto.

Since the phosphor layer 150 is formed on the top side of the light emitting device 100, the light emitted to the upper portion of the chip may be mixed with each other. In addition, since the phosphor layer 150 is formed on the entire top side of the chip with a uniform thickness, it is possible to reduce the dispersion in the color coordinate region when measuring the color coordinates of each light emitting device package, and color uniformity may also be improved. have.

8 is a view showing a light emitting device according to a third embodiment. In the description of the third embodiment, the same parts as in the first embodiment are referred to the first embodiment, and redundant description thereof will be omitted.

Referring to FIG. 8, the light emitting device 100A is attached with the phosphor layer 150A on the substrate 101.

The phosphor layer 150A includes a transparent adhesive layer 153, a phosphor layer 152, and an insulating layer 154. The adhesive layer 153 may be implemented as a double-sided tape as a transparent adhesive such as silicone or epoxy. The adhesive layer 153 is attached on the substrate 101, the phosphor layer 152 is attached on the adhesive layer 153, and an insulating layer 154 is formed on the phosphor layer 152. The phosphor layer 152 may include a sheet to which phosphor is added, for example, a photo luminescent film (PLF).

The insulating layer 154 may be formed of SiO 2 , SiO x , SiO x N y , Al 2 O 3 , TiO 2, or the like as a protective layer.

9 is a cross-sectional view illustrating a light emitting device according to a fourth embodiment. In describing the fourth embodiment, reference is made to the description disclosed above.

Referring to FIG. 9, in the light emitting device 100B, the transparent electrode layer 120 may be formed on the second conductive semiconductor layer 116, and the phosphor layer 150B may be formed on the transparent electrode layer 120.

The transparent electrode layer 120 functions as a current diffusion layer, and the current diffusion layer includes an oxide or nitride of a transparent material, for example, indium tin oxide (ITO), ITO nitride (ITO), indium zinc oxide (IZO), or IZTO (IZTO). indium zinc tin oxide (IAZO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), aluminum zinc oxide (AZO), antimony tin oxide (ATO), gallium zinc oxide (GZO) It may optionally be formed from. Such a current spreading layer may not be formed, but is not limited thereto.

The phosphor layer 150B and the second electrode 143 are formed on the transparent electrode layer 120, and the phosphor layer 150B may be formed by a screen printing method. The second electrode 143 may be formed before the formation of the phosphor layer 150. For example, in the process of forming the phosphor layer 150B, after masking an area of the second electrode 143, the phosphor layer 150B is formed by the screen printing method.

In this embodiment, the phosphor layer 150B may be formed on the opposite side of the substrate 101, that is, on the chip top side, thereby converting light emitted from the upper side of the chip into other light.

10 is a cross-sectional view illustrating a package including the light emitting device of FIG. 9 as a fifth embodiment.

Referring to FIG. 10, the light emitting device package 200A is mounted on the substrate 250. The light emitting device package 200A and the substrate 250 function as a light emitting module.

In the light emitting device package 200A, a cavity 215 is formed in the body 210, and the light emitting device 100B disclosed in FIG. 9 is mounted in the cavity 215. In the light emitting device 100B, a phosphor layer 150B is disposed on a chip top side, and a substrate is disposed below the chip.

The body 210 includes a plurality of lead terminals 201A and 201B and a heat dissipation frame 207. The lead terminals 201A and 201B are disposed on both bottom surfaces of the cavity 215, and are connected to the electrodes of the light emitting device 100B by a wire 209.

The plurality of lead terminals 201A and 201B may protrude through the outside of the body and may be bent in multiple stages.

The light emitting device 100B is attached to the heat radiating frame 207, and a lower end thereof is exposed to the bottom surface of the body 210.

The substrate 250 includes electrode terminals 251 and 253, a heat dissipation plate 255, an insulating layer 270, and a metal plate 260. The electrode terminals 251 and 253 correspond to the lead terminals 201A and 201B, respectively. The heat dissipation plate 255 is attached to the heat dissipation frame 207 and dissipates heat generated from the light emitting device 100B.

The electrode terminals 251 and 253 are separately disposed on the insulating layer 270 and supply power through a through hole structure or a circuit pattern.

The metal plate 260 dissipates heat emitted from the plurality of light emitting device packages 200A to allow the light emitting device 100B to operate stably.

11 is a side cross-sectional view of a light emitting device according to a sixth embodiment. In describing the sixth embodiment, reference is made to the description disclosed above.

Referring to FIG. 11, in the light emitting device 100C, the first phosphor layer 150 may be disposed under the substrate 101, and the second phosphor layer 150B may be disposed above the transparent electrode layer 120. The first and second phosphor layers 150 and 150B may include the same kind of phosphor or different kinds of phosphors. The light emitting device 100C may be mounted in the same manner as in FIG. 7 or may be mounted in the same manner as in FIG. 11.

The light emitting device according to the embodiment (s) may be packaged and used as a light source of an indicator device, a lighting device, a display device, or the like. In addition, each embodiment is not limited to each embodiment, it can be selectively applied to other embodiments disclosed above, but is not limited to each embodiment.

Features, structures, effects, and the like described in the above embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified with respect to other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

Although the above description has been made with reference to the embodiments, these are only examples and are not intended to limit the present invention, and those of ordinary skill in the art to which the present invention pertains should not be exemplified above without departing from the essential characteristics of the present embodiments. It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiment can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

100, 100A, 100B, 100C: light emitting element, 101, substrate, 110: compound semiconductor layer, 130: reflective electrode layer, 141: first electrode, 143: second electrode, 150, 150A, 150B: phosphor layer, 200: light emission Device package, 201, 203: lead electrode, 210: body

Claims (20)

Board;
A plurality of compound semiconductor layers including a first conductive semiconductor layer under the substrate, an active layer under the first conductive semiconductor layer, and a second conductive semiconductor layer under the active layer;
A first electrode electrically connected to the first conductive semiconductor layer;
A second electrode electrically connected to the second conductive semiconductor layer; And
A light emitting device comprising a first phosphor layer formed on the substrate. Translucent substrate;
A plurality of compound semiconductor layers including a first conductive semiconductor layer under the light transmissive substrate, an active layer under the first conductive semiconductor layer, and a second conductive semiconductor layer under the active layer;
A transparent electrode layer formed on the second conductive semiconductor layer;
A second electrode formed on the transparent electrode layer;
A second phosphor layer formed on the transparent electrode layer;
A light emitting device comprising a first electrode electrically connected to the first conductive semiconductor layer. The semiconductor device of claim 1, further comprising at least one of a transparent electrode layer and a reflective electrode layer disposed under the second conductive semiconductor layer.
And the second electrode is electrically connected to at least one of the transparent electrode layer and the reflective electrode layer. The semiconductor device of claim 1, further comprising: a transparent electrode layer on the second conductive semiconductor layer; And a third phosphor layer on the transparent electrode layer. The light emitting device of claim 4, wherein the first and third phosphor layers include phosphors of the same kind or different kinds of phosphors. The semiconductor light emitting device of claim 1 or 2, further comprising a compound semiconductor layer of Group 2 to 6 elements between the first conductive semiconductor layer and the substrate. The method of claim 1, wherein the first phosphor layer comprises: an adhesive layer formed on the light transmissive substrate; An optical excitation film attached to the adhesive layer; Light emitting device comprising a transparent insulating layer formed on the optical excitation film. The light emitting device of claim 1, further comprising a protrusion on or below the substrate. Board; A plurality of compound semiconductor layers including a first conductive semiconductor layer under the substrate, an active layer under the first conductive semiconductor layer, and a second conductive semiconductor layer under the active layer; A first electrode formed under the first conductive semiconductor layer; And a second electrode formed under the second conductive semiconductor layer.
A phosphor layer formed on the top side of the light emitting element;
A body having a plurality of lead terminals electrically connected to electrodes of the light emitting element; And
A light emitting device package comprising a resin layer formed around the light emitting device. The method of claim 9, wherein the body includes a cavity having an open top,
And a plurality of lead terminals, the light emitting element, and the resin layer in the cavity. The method of claim 10, wherein the cavity of the body includes a heat dissipation frame disposed between the plurality of lead terminals,
The heat dissipation frame is a light emitting device package is attached to the upper surface, the lower surface of the light emitting device package is exposed. The light emitting device package of claim 9, further comprising a wire connecting the first and second electrodes of the light emitting device to the lead terminals of the body. The light emitting device package of claim 9 or 10, further comprising conductive bumps connected to the first and second electrodes of the light emitting device and the lead terminals of the body. The method of claim 9 or 10,
The substrate is a light transmissive substrate,
The substrate is disposed on the top side of the light emitting device,
The phosphor layer is attached to the light emitting device package on the substrate. The light emitting device package according to claim 9 or 10, wherein the substrate is disposed on a bottom side of the light emitting device, and the phosphor layer is disposed under the second conductive semiconductor layer. The light emitting device package of claim 9 or 10, wherein the light emitting device comprises at least one of a transparent electrode layer and a reflective electrode layer formed between the second conductive semiconductor layer and the phosphor layer. Forming a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer on the light transmissive substrate;
Forming an electrode layer on the second conductive semiconductor layer;
Exposing a portion of the first conductive semiconductor layer;
Forming a first electrode on the first conductive semiconductor layer and a second electrode on the electrode layer; And
Forming a phosphor layer under the light-transmitting substrate. The method of claim 17, wherein the phosphor layer is formed on the entire lower surface of the light transmissive substrate by a screen printing method or an optical excitation film. The method of claim 17, wherein the electrode layer comprises at least one of a transparent electrode layer and a reflective electrode layer. The method of claim 17, wherein the light transmissive substrate is a sapphire substrate.
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