KR20110075395A - Methof for fabricating ono layer in flash memory device with sonos structure - Google Patents

Methof for fabricating ono layer in flash memory device with sonos structure Download PDF

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KR20110075395A
KR20110075395A KR1020090131837A KR20090131837A KR20110075395A KR 20110075395 A KR20110075395 A KR 20110075395A KR 1020090131837 A KR1020090131837 A KR 1020090131837A KR 20090131837 A KR20090131837 A KR 20090131837A KR 20110075395 A KR20110075395 A KR 20110075395A
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film
flash memory
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silicon oxide
layer
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이두성
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주식회사 동부하이텍
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors

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Abstract

PURPOSE: A method for forming an ONO layer of a flash memory element of a SONOS structure is provided to form a nitrogen layer at upper/lower layers within a tunnel oxide layer and a blocking layer by performing an annealing and decoupled plasma nitration process. CONSTITUTION: A silicon oxide film(202) is deposited on a semiconductor substrate(200). A nitrogen layer is formed on an upper layer within the first silicon oxide layer. A silicon nitride layer is deposited on an upper part of a tunnel oxide layer. A second silicon oxide layer(206) is deposited on an upper part of the silicon nitride layer. A nitrogen layer is formed on an upper layer within the second silicon oxide layer.

Description

ＳＯＮＯＳ 구조의 플래시 메모리 소자의 ＯＮＯ막 형성방법{METHOF FOR FABRICATING ONO LAYER IN FLASH MEMORY DEVICE WITH SONOS STRUCTURE}A method of forming an ON film of a flash memory device having a SONO structure {METHOF FOR FABRICATING ONO LAYER IN FLASH MEMORY DEVICE WITH SONOS STRUCTURE}

본 발명은 플래시 메모리 소자(flash memory device)의 제조 방법에 관한 것으로, 특히 SONOS(silicon oxide nitride oxide silicon) 구조를 가지는 플래시 메모리 소자의 제조에서 ONO(oxide nitride oxide)막 중 터널 산화막(tunel oxide)과 블록킹 산화막(blocking oxide)의 형성 시 N, O 가스를 이용한 어닐링(annealing)과 디커플드 플라즈마 질화(decoupled plasma nitridation) 공정을 수행하여 터널 산화막과 블록킹 산화막내 상/하부층에 나이트로젠막을 형성시킴으로써 트랩 질화막(trap nitride layer)에서의 전자의 이동을 방지시켜 소자의 리텐션(retention) 특성을 향상시킬 수 있는 SONOS 구조의 플래시 메모리 소자의 ONO막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a tune oxide of an oxide nitride oxide (ONO) film in the manufacture of a flash memory device having a silicon oxide nitride oxide silicon (SONOS) structure. When forming a blocking oxide and a blocking oxide (annealing) and decoupled plasma nitridation process using an N, O gas to form a nitrogen film on the upper and lower layers in the tunnel oxide and blocking oxide A method of forming an ONO film of a flash memory device having a SONOS structure capable of preventing electrons from moving in a trap nitride layer to improve retention characteristics of the device.

통상적으로 플래시 메모리 소자는 전원이 공급되지 않아도 데이터가 지워지지 않은 비휘발성 메모리 소자로 플로팅 게이트(floating gate) 형 셀을 사용하는 구조가 널이 이용되어 왔다.In general, a flash memory device has a structure in which a floating gate type cell is used as a nonvolatile memory device in which data is not erased even when power is not supplied.

그러나, 최근 들어 반도체 소자의 고집적화가 급속히 진행됨에 따라 플로팅 게이트형 셀의 축소가 요구되고 있어 위와 같은 플로팅 게이트 구조의 플래시 메모리 소자로는 더 이상 고집적화에 한계가 있었다.However, in recent years, as the integration of semiconductor devices is rapidly progressed, reduction of the floating gate type cell is required, and thus there is a limit to the integration of flash memory devices having the floating gate structure.

이에 따라, 플래시 메모리 소자의 다른 구조로써 하나의 셀 당 적어도 둘 이상의 게이트 구조물을 가지는 멀티비트 셀(multi bit cell)을 이용하는 플래시 메모리 소자가 제안되고 있으며, 멀티비트 셀을 이용한 플래시 메모리 소자로써 SONOS(silicon oxide nitride oxide silicon) 구조를 가지는 플래시 메모리 소자가 있다. Accordingly, as another structure of the flash memory device, a flash memory device using a multi bit cell having at least two gate structures per cell has been proposed, and a SONOS (flash memory device using a multi bit cell) has been proposed. There is a flash memory device having a silicon oxide nitride oxide silicon) structure.

위와 같은 SONOS 구조의 플래시 메모리 소자는 반도체 기판상에 터널 산화막, 트랩 질화막, 블록킹 산화막으로 구성되는 ONO(oxide nitride oxide)막을 형성하고, 그 위에 실리콘 게이트(silicon gate)가 형성되며 게이트 양측으로는 소오스 전극(source electrode) 및 드레인 전극(drain electrode)이 형성되는 구조(structure)를 갖는다. The flash memory device of the above-described SONOS structure forms an oxide nitride oxide (ONO) film composed of a tunnel oxide film, a trap nitride film, and a blocking oxide film on a semiconductor substrate, a silicon gate is formed thereon, and a source on both sides of the gate. It has a structure in which an electrode (source electrode) and a drain electrode (drain electrode) is formed.

도 1은 종래 SONOS 구조의 플래시 메모리 소자의 형성 시 ONO막을 형성하는 공정 흐름을 도시한 것이다.FIG. 1 illustrates a process flow of forming an ONO film in the formation of a flash memory device having a conventional SONOS structure.

도 1을 참조하면, SONOS 구조의 플래시 메모리 소자에서 ONO막을 형성하는 공정에서는 먼저, 반도체 기판상 O2 가스를 이용한 화학기상증착(CVD : chemical vapor deposition) 방식을 이용하여 터널 산화막을 증착시키고(S100), 터널 산화막 상부에 트랩 질화막으로 사용되는 실리콘 질화막을 증착시킨 후(S102), 블록킹 산 화막으로 사용되는 실리콘 산화막을 순차적으로 증착시켜(S104) ONO막을 형성시키게 된다.Referring to FIG. 1, in the process of forming an ONO film in a flash memory device having a SONOS structure, first, a tunnel oxide film is deposited using a chemical vapor deposition (CVD) method using an O 2 gas on a semiconductor substrate (S100). The silicon nitride film used as the trap nitride film is deposited on the tunnel oxide film (S102), and the silicon oxide film used as the blocking oxide film is sequentially deposited (S104) to form an ONO film.

위와 같은 SONOS 구조의 플래시 메모리 소자에서는 종래 플로팅 게이트 구조의 플래시 메모리 소자가 플로팅 게이트에 전하를 챠징(charging)하는 것과는 달리, 실리콘 질화막에 전하를 챠징함으로써 셀 높이(cell height)가 낮고 갭필(gap-fill) 특성이 우수하며, 싱글 핀홀 디펙트(single pin hole defect)가 없는 장점이 있다.In the flash memory device of the above-described SONOS structure, unlike the conventional flash memory device of the floating gate structure, which charges the floating gate, the cell height is low and the gap fill is caused by charging the charge in the silicon nitride film. Excellent fill properties and no single pin hole defects.

그러나, 종래 SONOS 구조의 플래시 메모리 소자에서는 전자를 트랩시키는 실리콘 질화막(SiN) 내에서 전자의 이동에 따라 하나의 셀 안에 존재하는 2비트간의 간섭(disturbance)이 발생되고, 고온에서 리텐션(retention) 특성이 좋지 않아 소자의 신뢰성을 확보할 수 없는 문제점이 있었다.However, in the flash memory device of the conventional SONOS structure, two-bit interference existing in one cell is generated by the movement of electrons in the silicon nitride film (SiN) that traps electrons, and retention is performed at high temperature. There was a problem that the reliability of the device can not be secured due to poor characteristics.

따라서, 본 발명은 SONOS 구조를 가지는 플래시 메모리 소자의 제조에서 ONO막 중 터널 산화막과 블록킹 산화막의 형성 시 N, O 가스를 이용한 어닐링과 디커플드 플라즈마 질화 공정을 수행하여 터널 산화막과 블록킹 산화막내 상/하부층에 나이트로젠막을 형성시킴으로써 트랩 질화막에서의 전자의 이동을 방지시켜 소자의 리텐션 특성을 향상시킬 수 있는 SONOS 구조의 플래시 메모리 소자의 ONO막 형성방법을 제공하고자 한다.Therefore, in the fabrication of a flash memory device having a SONOS structure, an annealing and decoupled plasma nitridation process using N, O gas is performed to form a tunnel oxide film and a blocking oxide film in an ONO film. The present invention provides a method for forming an ONO film of a flash memory device having a SONOS structure in which a nitride film is formed on a lower layer to prevent electron movement in a trap nitride film, thereby improving retention characteristics of the device.

상술한 본 발명은 SONOS 플래시 메모리 소자의 ONO막 형성 방법으로서, 반도체 기판상 제1 실리콘 산화막을 증착시키는 단계와, 상기 제1 실리콘 산화막내 상부층에 나이트로젠막을 형성시키는 단계와, 상기 터널 산화막 상부에 실리콘 질화막을 증착시키는 단계와, 상기 실리콘 질화막 상부에 제2 실리콘 산화막을 증착시키는 단계와, 상기 제2 실리콘 산화막내 상부층에 나이트로젠막을 형성시키는 단계를 포함한다.The present invention described above is a method of forming an ONO film of a SONOS flash memory device, comprising: depositing a first silicon oxide film on a semiconductor substrate, forming a nitrogen film on an upper layer in the first silicon oxide film; Depositing a silicon nitride film, depositing a second silicon oxide film on the silicon nitride film, and forming a nitrogen film on an upper layer in the second silicon oxide film.

또한, 상기 제1 및 제2 실리콘 산화막은, N2 및 O2 가스를 이용하여 CVD 방식으로 증착되는 것을 특징으로 한다.In addition, the first and the second silicon oxide film is characterized in that the deposition by the CVD method using N 2 and O 2 gas.

또한, 상기 제1 및 제2 실리콘 산화막은, SiON막으로 형성되며, 상기 제1 및 제2 실리콘 산화막내 하부층에 나이트로젠막이 형성되는 것을 특징으로 한다.The first and second silicon oxide films may be formed of a SiON film, and a nitrogen film may be formed on a lower layer in the first and second silicon oxide films.

또한, 상기 나이트로젠막은, 디커플드 플라즈마 질화 공정을 통해 형성되는 것을 특징으로 한다.In addition, the nitrogen film is formed through a decoupled plasma nitriding process.

본 발명은 SONOS 구조의 플래시 메모리 소자의 ONO막 형성방법에 있어서, ONO막 중 터널 산화막과 블록킹 산화막의 형성 시 N, O 가스를 이용한 어닐링과 디커플드 플라즈마 질화 공정을 수행하여 터널 산화막과 블록킹 산화막내 상/하부층에 나이트로젠막을 형성시킴으로써 트랩 질화막에서의 전자의 이동을 방지시킴으로 써 채널과 폴리 실리콘으로의 챠지 리키지를 방지시켜 소자의 리텐션 특성을 향상시킬 수 있는 이점이 있다.In the method for forming an ONO film of a flash memory device having a SONOS structure, the tunnel oxide film and the blocking oxide are formed by performing annealing and decoupled plasma nitridation using N and O gas when the tunnel oxide film and the blocking oxide film are formed in the ONO film. By forming a nitrogen film in the upper and lower layers in the film, it is possible to prevent the migration of electrons in the trap nitride film, thereby preventing charge charge to the channel and the polysilicon, thereby improving the retention characteristics of the device.

이하, 첨부된 도면을 참조하여 본 발명의 동작 원리를 상세히 설명한다. 하기에서 본 발명을 설명함에 있어서 공지 기능 또는 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우에는 그 상세한 설명을 생략할 것이다. 그리고 후술되는 용어들은 본 발명에서의 기능을 고려하여 정의된 용어들로서 이는 사용자, 운용자의 의도 또는 관례 등에 따라 달라질 수 있다. 그러므로 그 정의는 본 명세서 전반에 걸친 내용을 토대로 내려져야 할 것이다. Hereinafter, with reference to the accompanying drawings will be described in detail the operating principle of the present invention. In the following description of the present invention, if it is determined that a detailed description of a known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. The following terms are defined in consideration of the functions of the present invention, and may be changed according to the intentions or customs of the user, the operator, and the like. Therefore, the definition should be based on the contents throughout this specification.

도 2는 본 발명의 실시 예에 적용되는 SONOS 구조의 플래시 메모리 소자의 단위 셀 구조 단면도를 도시한 것이다.2 is a cross-sectional view of a unit cell structure of a flash memory device having a SONOS structure applied to an embodiment of the present invention.

도 2을 참조하면, SONOS 구조의 플래시 메모리 소자는 반도체 기판(200) 상에 제1 실리콘 산화막(silicon oxide)(202), 실리콘 질화막(SiN)(204) 및 제2 실리콘 산화막(silicon oxide)(206)이 차례로 적층된 ONO막(208)과, ONO막(208) 상부에 형성된 제어 게이트(control gate)(210)와, 제어 게이트(210)의 양측 반도체 기판(200) 표면내에 불순물 영역을 형성하여 이루어진 소오스 영역(source area)(212), 드레인 영역(drain area)(214)으로 구성된다.Referring to FIG. 2, a flash memory device having a SONOS structure may include a first silicon oxide 202, a silicon nitride 204, and a second silicon oxide 205 on a semiconductor substrate 200. An impurity region is formed in the ONO film 208 in which the 206 is sequentially stacked, a control gate 210 formed on the ONO film 208, and surfaces of both semiconductor substrates 200 of the control gate 210. And a source region 212 and a drain region 214.

여기서, 제1 실리콘 산화막(202)은 터널 산화막(tunel oxide layer)이고, 실리콘 질화막(204)은 트랩 질화막으로서 트랩 사이트내 전하를 충전하거나 혹은 충전된 전하를 방출함으로써 셀의 문턱 전압(Vth)을 제어하여 메모리 기능을 수행하며, 제2 실리콘 산화막(206)은 충전 전하의 손실을 방지하는 블록킹 산화막(blocking oxide)이다.Here, the first silicon oxide layer 202 is a tunnel oxide layer, and the silicon nitride layer 204 is a trap nitride layer, and charges the charge in the trap site or discharges the charged charge, thereby reducing the threshold voltage Vth of the cell. The memory cell is controlled to perform a memory function, and the second silicon oxide layer 206 is a blocking oxide that prevents the loss of the charge.

도 3은 본 발명의 실시 예에 따른 SONOS 구조의 플래시 메모리 소자의 제조 시 리텐션(retention) 특성을 향상시키는 ONO막을 형성하는 공정 흐름을 도시한 것이다.FIG. 3 illustrates a process flow for forming an ONO film that improves retention characteristics when manufacturing a flash memory device having a SONOS structure according to an embodiment of the present invention.

먼저, (S300)단계에서 반도체 기판(200)상 터널 산화막(tunel oxide) 형성을 위해 챔버(chamber) 내에서 N2, O2 가스를 이용한 화학기상증착 방법을 이용하여 반도체 기판(200)상 제1 실리콘 산화막(202)을 형성시킨다. 이때 터널 산화막으로 사용되는 제1 실리콘 산화막(202)은 N2 가스 성분으로 인해 SiNO로 형성되며, 제1 실리콘 산화막(202)내 하부층에 나이트로젠막이 형성되어 전자의 이동을 방지시키게 된다.First, in operation S300, a chemical vapor deposition method using N 2 and O 2 gas in a chamber to form a tune oxide on the semiconductor substrate 200 is formed on the semiconductor substrate 200. 1 silicon oxide film 202 is formed. In this case, the first silicon oxide film 202 used as the tunnel oxide film is formed of SiNO due to the N 2 gas component, and a nitrogen film is formed on the lower layer in the first silicon oxide film 202 to prevent the movement of electrons.

위와 같이, 반도체 기판(200) 상 터널 산화막을 형성시킨 후, (S302)단계에서 제1 실리콘 산화막(202) 상부에 디커플드 플라즈마 질화(decoupled plasma nitridation) 공정 수행한다. 이에 따라 제1 실리콘 산화막(202)내 상부층에도 나이트로젠막이 형성되어 제1 실리콘 산화막(202)내 상/하부층에 전자의 이동을 방지시키는 나이트로젠막이 형성되게 된다.As described above, after the tunnel oxide film is formed on the semiconductor substrate 200, a decoupled plasma nitridation process is performed on the first silicon oxide film 202 in step S302. As a result, a nitrogen film is also formed on the upper layer in the first silicon oxide film 202 to form a nitrogen film that prevents the movement of electrons in the upper and lower layers of the first silicon oxide film 202.

이어, (S304)단계에서 제1 실리콘 산화막(202)의 상부에 트랩 질화막으로 사용되는 실리콘 질화막(SiN)(204)을 형성시킨다.Subsequently, in operation S304, a silicon nitride film (SiN) 204 used as a trap nitride film is formed on the first silicon oxide film 202.

위와 같이, 반도체 기판(200) 상 터널 산화막과 트랩 질화막을 형성시킨 후, (S306)단계에서 트랩 질화막의 상부에 블로킹 산화막으로 사용되는 제2 실리콘 산화막(206)을 형성시킨다. 이때 블로킹 산화막으로 사용되는 제2 실리콘 산화막(206)은 N2 가스 성분으로 인해 SiNO로 형성되며, 제2 실리콘 산화막(206)내 하부층에 나이트로젠막이 형성되어 전자의 이동을 방지시키게 된다.As described above, after the tunnel oxide film and the trap nitride film are formed on the semiconductor substrate 200, the second silicon oxide film 206 used as the blocking oxide film is formed on the trap nitride film in step S306. At this time, the second silicon oxide film 206 used as the blocking oxide film is formed of SiNO due to the N 2 gas component, and a nitrogen film is formed on the lower layer in the second silicon oxide film 206 to prevent electrons from moving.

위와 같이, 블록킹 산화막을 형성시킨 후, (S308)단계에서 제2 실리콘 산화막(206) 상부에 디커플드 플라즈마 질화(decoupled plasma nitridation) 공정 수행한다. 이에 따라 제2 실리콘 산화막(206)내 상부층에도 나이트로젠막이 형성되어 제2 실리콘 산화막(206)내 상/하부층에 전자의 이동을 방지시키는 나이트로젠막이 형성되게 된다.As described above, after the blocking oxide film is formed, a decoupled plasma nitridation process is performed on the second silicon oxide film 206 in step S308. As a result, a nitrogen film is formed on the upper layer of the second silicon oxide film 206, thereby forming a nitrogen film that prevents the movement of electrons in the upper and lower layers of the second silicon oxide film 206.

상기한 바와 같이, 본 발명에서는 SONOS 구조의 플래시 메모리 소자의 ONO막 형성방법에 있어서, ONO막 중 터널 산화막과 블록킹 산화막의 형성 시 N, O 가스를 이용한 어닐링과 디커플드 플라즈마 질화 공정을 수행하여 터널 산화막과 블록킹 산화막내 상/하부층에 나이트로젠막을 형성시킴으로써 트랩 질화막에서의 전자의 이동을 방지시킴으로써 채널과 폴리 실리콘으로의 챠지 리키지를 방지시켜 소자의 리텐션 특성을 향상시키게 된다.As described above, in the present invention, in the method of forming the ONO film of a flash memory device having a SONOS structure, annealing and decoupled plasma nitridation using N and O gases are performed by forming a tunnel oxide film and a blocking oxide film in the ONO film. The formation of a nitrogen film in the upper and lower layers of the tunnel oxide film and the blocking oxide film prevents the movement of electrons in the trap nitride film, thereby preventing charge leakage to the channel and the polysilicon, thereby improving the retention characteristics of the device.

한편 상술한 본 발명의 설명에서는 구체적인 실시 예에 관해 설명하였으나, 여러 가지 변형이 본 발명의 범위에서 벗어나지 않고 실시될 수 있다. 따라서 발명의 범위는 설명된 실시 예에 의하여 정할 것이 아니고 특허청구범위에 의해 정하여져야 한다.Meanwhile, in the above description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Accordingly, the scope of the invention should not be limited by the described embodiments but should be defined by the appended claims.

도 1은 종래 SONOS 구조의 플래시 메모리 소자의 제조 시 ONO막 형성 공정 흐름도,1 is a flowchart illustrating a process of forming an ONO film in manufacturing a flash memory device having a conventional SONOS structure;

도 2는 본 발명의 실시 예에 따른 SONOS 플래시 메모리 소자의 구조 단면도,2 is a structural cross-sectional view of a SONOS flash memory device according to an embodiment of the present invention;

도 3은 본 발명의 실시 예에 따른 SONOS 구조의 플래시 메모리 소자의 제조 시 ONO막 형성 공정 흐름도.3 is a flowchart illustrating a process of forming an ONO film during fabrication of a flash memory device having a SONOS structure according to an embodiment of the present invention.

<도면의 주요 부호에 대한 간략한 설명><Brief description of the major symbols in the drawings>

200 : 반도체 기판 202 : 제1 실리콘 산화막200 semiconductor substrate 202 first silicon oxide film

204 : 실리콘 질화막 206 : 제2 실리콘 질화막204 Silicon nitride film 206 Second silicon nitride film

208 : ONO막208: ONO film

Claims (4)

SONOS 플래시 메모리 소자의 ONO막 형성 방법으로서,As a method of forming the ONO film of a SONOS flash memory device, 반도체 기판상 제1 실리콘 산화막을 증착시키는 단계와,Depositing a first silicon oxide film on the semiconductor substrate; 상기 제1 실리콘 산화막내 상부층에 나이트로젠막을 형성시키는 단계와,Forming a nitrogen film on an upper layer in the first silicon oxide film; 상기 터널 산화막 상부에 실리콘 질화막을 증착시키는 단계와,Depositing a silicon nitride film on the tunnel oxide film; 상기 실리콘 질화막 상부에 제2 실리콘 산화막을 증착시키는 단계와,Depositing a second silicon oxide film on the silicon nitride film; 상기 제2 실리콘 산화막내 상부층에 나이트로젠막을 형성시키는 단계Forming a nitrogen film on an upper layer in the second silicon oxide film 를 포함하는 SONOS 플래시 메모리 소자의 ONO막 형성방법.An ONO film forming method of a SONOS flash memory device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 제1 및 제2 실리콘 산화막은,The first and second silicon oxide film, N2 및 O2 가스를 이용하여 CVD 방식으로 증착되는 것을 특징으로 하는 SONOS 플래시 메모리 소자의 ONO막 형성방법.A method of forming an ONO film of a SONOS flash memory device, characterized in that deposited by CVD using N 2 and O 2 gas. 제 1 항에 있어서,The method of claim 1, 상기 제1 및 제2 실리콘 산화막은,The first and second silicon oxide film, SiON막으로 형성되며, 상기 제1 및 제2 실리콘 산화막내 하부층에 나이트로젠막이 형성되는 것을 특징으로 하는 SONOS 플래시 메모리 소자의 ONO막 형성방법.A method of forming an ONO film of a SONOS flash memory device, wherein the nitride film is formed of a SiON film, and a nitride film is formed on the lower layers of the first and second silicon oxide films. 제 1 항에 있어서,The method of claim 1, 상기 나이트로젠막은,The nitrogen film is, 디커플드 플라즈마 질화 공정을 통해 형성되는 것을 특징으로 하는 SONOS 플래시 메모리 소자의 ONO막 형성방법.An ONO film forming method of a SONOS flash memory device, characterized in that formed through a decoupled plasma nitriding process.
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