KR20110074353A - Liquid crystal display - Google Patents

Abstract

PURPOSE: A liquid crystal display device is provided to reduce optical interference influence by controlling operations of drive circuits at a frequency faster than an input frame frequency. CONSTITUTION: A data drive circuit(12) drives data lines of a liquid crystal display panel. A gate drive circuit(13) drives gate lines of the liquid crystal display panel. Light sources generate the light to be irradiated on the liquid crystal display panel. A timing controller(11) divides one frame period into first and second sub-frame durations. The timing controller controls the operation timing of the drive circuits at a frame frequency higher than an input frame frequency.

Description

Liquid Crystal Display {LIQUID CRYSTAL DISPLAY}

The present invention relates to a liquid crystal display device capable of improving moving picture response time (hereinafter, referred to as "MPRT").

An active matrix liquid crystal display device displays a moving image using a thin film transistor (“TFT”) as a switching element. This liquid crystal display device is thinner and higher resolution than cathode ray tube ("CRT"), so it is applied to display in portable information equipment, office equipment, computer, etc., and is rapidly replacing CRT. .

When displaying a moving image through a liquid crystal display, motion blurring may appear due to the retention characteristics of the liquid crystal. In order to improve MPRT, a scanning backlight driving technique has been proposed. The scanning backlight driving technology sequentially flashes the light sources of the backlight unit along the scanning direction of the display line as shown in FIGS. 1 and 2 to provide an effect similar to the impulsive driving of the CRT, thereby blurring motion of the liquid crystal display. Improve ring.

However, the conventional scanning backlight driving technique has the following problems.

First, according to the conventional scanning backlight driving technique, the screen is dark because the light sources of the backlight unit are turned off for a predetermined time every frame period. In order to reduce the darkening of the screen, it is possible to consider a method of adjusting the light-out time according to the brightness of the screen, but in this case, since the light-out time is shortened or the light-out time disappears on the bright screen, the effect of improving the MPRT performance is reduced.

Second, according to the conventional scanning backlight driving technique, since the timing of turning on and off the light sources between the scanning blocks is different, there is a disadvantage in that optical interference between blocks occurs. For example, when the frame frequency is 120 Hz and the light sources are sequentially driven in units of three scanning blocks BLK1 to BLK3 as shown in FIG. 3, the light sources of each scanning block are turned off during the transition period TP of the liquid crystal. It is maintained and turned on within the saturation period SP of the liquid crystal. Immediately after the light sources of the first scanning block BLK1 are turned off, the light sources of the second scanning block BLK2 are turned on, and immediately after the light sources of the second scanning block BLK2 are turned off, the third scanning block BLK3 ) Light sources are turned on. Since the neighboring scanning blocks are not physically shielded, the light sources of the upper scanning block that are kept off are subject to light interference by the lower scanning block turning on. Due to this optical interference, the light sources of the first scanning block BLK1 may be affected as if the liquid crystal is turned on while the liquid crystal is falling by turning on the second scanning block BLK2 even after being turned off. Can be. In addition, the light sources of the second scanning block BLK2 may be affected as if the liquid crystals are turned on while the liquid crystal is falling by turning on the third scanning block BLK3 even after being turned off. In order to reduce the influence of the optical interference, the overlap length of the turn-off period and the turn-on period of neighboring scanning blocks should be reduced.

Accordingly, an object of the present invention is to provide a liquid crystal display device capable of reducing the influence of optical interference by reducing the overlap length of turn-off periods and turn-on periods of neighboring scanning blocks when driving a scanning backlight.

Another object of the present invention is to provide a liquid crystal display device which can prevent a decrease in luminance when driving a scanning backlight.

In order to achieve the above object, the liquid crystal display device according to an embodiment of the present invention comprises a liquid crystal display panel; A data driver circuit driving data lines of the liquid crystal display panel; A gate driving circuit driving gate lines of the liquid crystal display panel; One frame period is divided into first and second sub frame periods, and the same frame data is repeatedly supplied to the data driving circuit for the first and second sub frame periods, and the driving circuits are operated at a frame frequency higher than an input frame frequency. A timing controller for controlling an operation timing; Light sources generating light to be irradiated onto the liquid crystal display panel; And a light source driving circuit configured to sequentially light the light sources in units of a scanning block at a duty ratio of 50% or less within a period in which the liquid crystal of the liquid crystal display panel is segregated.

The timing controller controls the operation of the driving circuits at a frame frequency multiplied by twice the input frame frequency.

The liquid crystal display further includes a light source control circuit for generating a PWM signal for controlling the lighting of the light sources and a current control signal for controlling a driving current applied to the light sources.

The scanning block comprises first to third scanning blocks; The light source control circuit sets the duty ratio of the PWM signal to 50%.

The scanning block comprises first to third scanning blocks; The light source control circuit adjusts the duty ratio of the PWM signal to less than 50%.

In the first scanning block, the light source control circuit delays the turn-on time of the light sources compared to the turn-on time when the duty ratio is 50%, and turns the turn-off time of the light sources when the duty ratio is 50%. Fix to off time; In the second scanning block, the turn-on time of the light sources is delayed compared to the turn-on time when the duty ratio is 50%, and the turn-off time of the light sources is faster than the turn-off time when the duty ratio is 50%. ; In the third scanning block, the turn-on time of the light sources is fixed to the turn-on time when the duty ratio is 50%, and the turn-off time of the light sources is faster than the turn-off time when the duty ratio is 50%.

The level of the drive current is adjusted to be inversely proportional to the duty ratio of the PWM signal.

The liquid crystal display according to the present invention controls the operation of the driving circuits at a frequency faster than the input frame frequency, divides one frame into first and second sub-frames, and repeatedly displays the same data, thereby immediately after the data is written. The liquid crystals are all segmented at each point of the liquid crystal display panel before the time for one subframe has elapsed. The light sources are sequentially turned on at a duty ratio of 50% or less within the liquid crystal period. Accordingly, the liquid crystal display according to the present invention can reduce the influence of optical interference by reducing the overlap length of the turn-off period and the turn-on period of neighboring scanning blocks when driving the scanning backlight.

Furthermore, the liquid crystal display according to the present invention increases the light source driving current as the lighting time of the light sources is reduced in one frame, thereby preventing the luminance from being lowered during the driving of the scanning backlight.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 9.

4 shows a liquid crystal display according to an embodiment of the present invention.

Referring to FIG. 4, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal display panel 10, a data driving circuit 12 for driving data lines DL of the liquid crystal display panel 10, and a liquid crystal display. The gate driving circuit 13 for driving the gate lines GL of the panel 10, the timing controller 11 controlling the data driving circuit 12 and the gate driving circuit 13, and the liquid crystal display panel 10. A backlight unit 16 for irradiating light, a light source control circuit 14 for generating a light source control signal LCS, and a light source driving circuit 15 for scanning and driving light sources according to the light source control signal LCS. .

The liquid crystal display panel 10 includes two glass substrates and a liquid crystal layer formed therebetween. A plurality of data lines DL and a plurality of gate lines GL cross on the lower glass substrate of the liquid crystal display panel 10. The liquid crystal cells Clc are arranged in a matrix form on the liquid crystal display panel 10 due to the cross structure of the data lines DL and the gate lines GL. In the lower glass substrate of the liquid crystal display panel 10, TFTs, pixel electrodes 1 of liquid crystal cells Clc connected to TFTs, storage capacitors Cst, and the like are formed.

The black matrix, the color filter, and the common electrode 2 are formed on the upper glass substrate of the liquid crystal display panel 10. The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and has an in plane switching (IPS) mode and a fringe field switching (FFS) mode. In the same horizontal electric field driving method, the pixel electrode 1 is formed on the lower glass substrate. A polarizing plate is attached to each of the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10, and an alignment layer for setting a pretilt angle of the liquid crystal is formed on an inner surface of the liquid crystal display panel 10 in contact with the liquid crystal.

The timing controller 11 is a timing control signal for controlling the operation timing of the data driving circuit 12 and the gate driving circuit 13 based on timing signals Vsync, Hsync, DE, and DCLK from an external system board. Generate (DDC, GDC). The timing controller 11 multiplies the data timing control signal DDC and the gate timing control signal GDC to obtain a data driving circuit at a frame frequency of 120 x N (N is a positive integer of 2 or more) Hz, for example, a frame frequency of 240 Hz. 12 and the operation of the gate driving circuit 13 are controlled. The multiplying the frame frequency may be performed in an external system circuit.

In addition, the timing controller 11 time-divisions one frame period into a first sub frame period and a second sub frame period. After copying the digital video data RGB input from the system board by one frame unit using a frame memory or the like, the original digital video data RGB and the copied digital video data RGB are synchronized with the multiplied frame frequency. To the data driving circuit 12. Within one frame period, the original digital video data RGB is displayed on the screen for the first sub frame period, and the copy digital video data RGB is displayed on the screen for the second sub frame period.

The data driver circuit 12 includes a plurality of data drive integrated circuits. The data drive integrated circuit stores a shift line for sampling a clock signal, a register for temporarily storing digital video data, and stores data one line at a time in response to a clock signal from the shift register and simultaneously outputs the stored one line data. Digital / analog converter and positive polarity for selecting a positive / negative gamma voltage under reference to a gamma reference voltage in response to a digital data value from the latch. And a multiplexer for selecting a data line to which a negative data voltage is supplied, and an output buffer connected between the multiplexer and the data line. The data driving circuit 12 latches the digital video data RGB in response to the data timing control signal DDC multiplied by 120 × N (N is a positive integer of 2 or more) Hz input from the timing controller 11, The latched digital video data RGB is converted into a positive / negative analog data voltage using the positive / negative gamma compensation voltage and then supplied to the data lines DL.

The gate driving circuit 13 includes a plurality of gate drive integrated circuits. The gate drive integrated circuit includes a shift register, a level shifter for converting an output signal of the shift register into a swing width suitable for driving a TFT of a liquid crystal cell, an output buffer, and the like. The gate driving circuit 13 sequentially processes the scan pulse (or gate pulse) in response to the gate timing control signal GDC multiplied by 120 × N (N is a positive integer of 2 or more) Hz input from the timing controller 11. Output to the gate lines GL.

The backlight unit 16 includes a plurality of light sources to irradiate light to the liquid crystal display panel 10. The backlight unit 16 may be implemented as one of a direct type and an edge type. The direct type backlight unit 16 has a structure in which a plurality of optical sheets and a diffusion plate are stacked below the liquid crystal display panel 10 and a plurality of light sources are disposed below the diffusion plate. The edge type backlight unit 16 has a structure in which a plurality of optical sheets and a light guide plate are stacked below the liquid crystal display panel 10 and a plurality of light sources are disposed on the side of the light guide plate. The light sources can be implemented with line light sources such as Cold Cathode Fluorescent Lamps (CCFLs) or External Electrode Fluorescent Lamps (EEFLs), and are similar to Light Emitting Diodes (LEDs). It can be implemented with light sources.

The light source control circuit 14 generates a light source control signal LCS under the control of the timing controller 11, and the light sources sequentially follow the data scanning direction of the liquid crystal display panel 10 through the light source control signal LCS. The light sources are controlled by pulse width modulation (PWM) to be driven. The duty ratio of the PWM signal may be adjusted to 50% or less to improve the motion picture response time (MPRT). The light source control circuit 14 may analyze the input image and adjust the duty ratio of the PWM signal according to the analysis result, and control the light source driving circuit 15 to adjust the driving current of the light sources in conjunction with the duty ratio adjustment. have. The level of the drive current is adjusted to have an inverse relationship with the duty ratio of the PWM signal. That is, the smaller the duty ratio of the PWM signal is, the higher the level of the drive current is adjusted. This is to compensate for deterioration of luminance of the screen in response to an increase in the unlit time of the light sources within one frame period to improve the MPRT performance. The light source control circuit 14 may be built in the timing controller 11.

The light source control signal LCS includes a timing of turning on and off the light sources. The lighting timing of the light sources is determined after the liquid crystal is saturated on the display surface of the liquid crystal display panel 10 corresponding to the light sources. The timing of lighting of the light sources may be lengthened in proportion to the duty ratio of the PWM signal after the liquid crystal is segregated.

The light source driving circuit 15 sequentially drives the light sources in synchronization with data scanning of the liquid crystal display panel 10 in response to the light source control signal LCS. The light source driving circuit 15 may adjust the driving currents of the light sources according to the duty ratio of the PWM signal under the control of the light source control circuit 14.

5 to 7 show data writing, response of liquid crystal, and lighting timing of light sources for MPRT improvement.

Referring to FIG. 5, the present invention performs time-division driving of one frame into a first subframe SF1 and a second subframe SF2 by controlling the driving circuits using a frame frequency multiplied twice the input frame frequency. . One frame of original data is displayed during the first subframe SF1, and one frame of copy data (same as the original data) is displayed on the liquid crystal display panel during the second subframe SF2. The response speed of the liquid crystal LC is inversely proportional to the capacitor component present in the liquid crystal display panel. In addition, since the capacitor component is inversely proportional to the frame frequency, multiplying the frame frequency twice as much as the input results in a faster response speed of the liquid crystal LC. As shown in FIG. 6, when the frequency driving the respective subframes SF1 and SF2 is increased to 240 Hz, the same data is repeatedly supplied, and the light sources are sequentially driven in units of three scanning blocks BLK1 to BLK3, and thus, scanning of data is required. The time taken is reduced to 1s / 240. In addition, the liquid crystals LC corresponding to each of the scanning blocks BLK1 to BLK3 are segmented immediately after the data is written, but before the first subframe SF1 has elapsed, and each of the second subframes SF2. This saturation state is maintained until The light sources of each of the scanning blocks BLK1 to BLK3 remain off during the transition period TP of the liquid crystal, and are sequentially turned on at a 50% duty ratio within the liquid crystal separation period SP. Therefore, as the response speed of the liquid crystal LC increases, the overlap lengths of the turn-off periods and the turn-on periods of the neighboring scanning blocks BLK1 to BLK3 are reduced to 1/2 or less as compared with the related art. That is, according to the present invention, even if the light sources are sequentially turned on at a duty ratio of 50% as in the prior art, the turn-on time of the second scanning block BLK2 is earlier than the turn-off time of the first scanning block BLK1, Since the turn-on time of the first scanning block BLK3 is earlier than the turn-off time of the second scanning block BLK2, the length of the turn-on period of the neighboring lower scanning block overlapping the turn-off period of the neighboring upper scanning block is Significantly reduced compared to the conventional. As the length of overlap between the turn-off period and the turn-on period of neighboring scanning blocks decreases, optical interference is less affected.

On the other hand, the turn-on period of the scanning blocks BLK1 to BLK3 may be further reduced within the separation period SP of the liquid crystal as shown in FIG. 7 so that the overlap length between the turn-off period and the turn-on period of the neighboring scanning blocks is further reduced. The duty ratio can be adjusted to less than 50%. To this end, in the first scanning block BLK1, the turn-on time of the light sources is adjusted to be delayed compared to the turn-on time when the duty ratio is 50%, and the turn-off time when the turn-off time of the light sources is 50% duty ratio. It can be adjusted to be fixed. In the second scanning block BLK2, the turn-on time of the light sources is adjusted to be delayed compared to the turn-on time when the duty ratio is 50%, and the turn-off time of the light sources is turned off when the duty ratio is 50%. It can be adjusted to be faster. In the third scanning block BLK3, the turn-on time of the light sources is adjusted to be fixed at the turn-on time when the duty ratio is 50%, and the turn-off time of the light sources is compared with the turn-off time when the duty ratio is 50%. It can be adjusted to be fast. According to FIG. 7, the length of the turn-on period of the neighboring lower scanning block overlapping the turn-off period of the neighboring upper scanning block is further reduced.

FIG. 8 shows levels of driving currents that are set differently according to duty ratios of PWM signals to compensate for luminance degradation during backlight scanning driving.

Referring to FIG. 8, the level of the driving current is adjusted to have an inverse relationship with the duty ratio of the PWM signal. For example, the level of the driving current is twice the reference current level A (2A) corresponding to the PWM signal having the duty ratio of 50%, and the reference current level (in response to the PWM signal having the duty ratio of 33%). 3 times (3A) of A), corresponding to a PWM signal having a duty ratio of 25%, 4 times (4A) of a reference current level (A), and a reference current corresponding to a PWM signal having a duty ratio of 20% It can be adjusted to 5 times 5A of level A. Here, the reference current level A is a current level corresponding to a duty ratio of 100% and is stored in advance in a specific register in the light source control circuit.

9 shows the configuration of the light source control circuit 14 of FIG.

Referring to FIG. 9, the light source control circuit 14 includes an input image analyzer 141, a data modulator 142, a duty adjuster 143, and a current controller 144.

The input image analyzer 141 calculates a histogram of the data RGB of the input image, that is, a cumulative distribution function, and calculates a frame representative value such as an average value and a mode value of the cumulative distribution function. The input image analyzer 141 determines a gain value G according to the frame representative value, and supplies the gain value G to the data modulator 142 and the duty controller 143. The gain value G may be determined to be higher as the frame representative value is higher, and may be determined as a lower value as the frame representative value is lower.

The data modulator 142 modulates the data RGB based on the gain value from the input image analyzer 141 to adjust the dynamic range of the data R'G'B 'input to the liquid crystal display panel 10. Zoom in. The higher the gain value from the input image analyzer 141, the larger the up-modulation width of the data, and the lower the gain value, the greater the down-modulation width of the data. The data modulation equation of the data modulator 142 may be implemented as a look-up table.

The duty controller 143 adjusts the duty ratio of the PWM signal according to the gain value G from the input image analyzer 141. The duty ratio of the PWM signal is determined in proportion to the gain value G within a range of 50% or less.

The current controller 144 outputs a current control signal CA which is inversely proportional to the duty ratio of the PWM signal input from the duty controller 143. The current control signal CA may be generated as an analog signal or a digital signal.

As described above, the liquid crystal display according to the present invention controls the operation of the driving circuits at a frequency faster than the input frame frequency, divides one frame into first and second subframes, and repeatedly displays the same data, thereby writing data. The liquid crystals are all segmented at each point of the liquid crystal display panel immediately after the first subframe has elapsed. The light sources are sequentially turned on at a duty ratio of 50% or less within the liquid crystal period. Accordingly, the liquid crystal display according to the present invention can reduce the influence of optical interference by reducing the overlap length of the turn-off period and the turn-on period of neighboring scanning blocks when driving the scanning backlight.

Furthermore, the liquid crystal display according to the present invention increases the light source driving current as the lighting time of the light sources is reduced in one frame, thereby preventing the luminance from being lowered during the driving of the scanning backlight.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 and 2 illustrate a conventional scanning backlight driving technique.

3 is a diagram showing large optical interference between scanning blocks in a conventional scanning backlight driving technique.

4 is a view showing a liquid crystal display according to an embodiment of the present invention.

5 shows data write timing for MPRT improvement.

FIG. 6 shows an example of the response of the liquid crystal and the flashing timing of the light sources to reduce optical interference between scanning blocks; FIG.

7 shows another example of the response of the liquid crystal and the timing of the flashing of the light sources to reduce optical interference between the scanning blocks.

8 is a view showing levels of a drive current signal set differently according to the duty ratio of a PWM signal.

9 is a diagram illustrating a configuration of a light source control circuit of FIG. 4.

<Description of Symbols for Main Parts of Drawings>

10 liquid crystal display panel 11 timing controller

12: data driving circuit 13: gate driving circuit

14 light source control circuit 15 light source driving circuit

16: backlight unit

Claims (7)

A liquid crystal display panel; A data driver circuit driving data lines of the liquid crystal display panel; A gate driving circuit driving gate lines of the liquid crystal display panel; One frame period is divided into first and second sub frame periods, and the same frame data is repeatedly supplied to the data driving circuit for the first and second sub frame periods, and the driving circuits are operated at a frame frequency higher than an input frame frequency. A timing controller for controlling an operation timing; Light sources generating light to be irradiated onto the liquid crystal display panel; And And a light source driving circuit for sequentially lighting the light sources in units of a scanning block at a duty ratio of 50% or less within a period in which the liquid crystal of the liquid crystal display panel is segregated. The method of claim 1, And the timing controller controls the operation of the driving circuits at a frame frequency multiplied by twice the input frame frequency. The method of claim 1, And a light source control circuit for generating a PWM signal for controlling the lighting of the light sources and a current control signal for controlling a driving current applied to the light sources. The method of claim 3, wherein The scanning block comprises first to third scanning blocks; And the light source control circuit sets the duty ratio of the PWM signal to 50%. The method of claim 3, wherein The scanning block comprises first to third scanning blocks; And the light source control circuit adjusts the duty ratio of the PWM signal to less than 50%. The method of claim 5, The light source control circuit, In the first scanning block, delaying the turn-on time of the light sources with respect to the turn-on time when the duty ratio is 50%, and fixing the turn-off time of the light sources to the turn-off time when the duty ratio is 50%; In the second scanning block, the turn-on time of the light sources is delayed compared to the turn-on time when the duty ratio is 50%, and the turn-off time of the light sources is faster than the turn-off time when the duty ratio is 50%. ; In the third scanning block, the turn-on time of the light sources is fixed to the turn-on time when the duty ratio is 50%, and the turn-off time of the light sources is faster than the turn-off time when the duty ratio is 50%. A liquid crystal display device. The method according to claim 4 or 5, And the level of the driving current is adjusted in inverse proportion to the duty ratio of the PWM signal.

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