KR20110047883A - Method for manufacturing semiconductor device with vertical gate - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device with a vertical gate is provided to prevent an active pillar from falling due to the tensile stress of a spin-on insulation layer by forming a liner silicon film before making an isolation film. CONSTITUTION: In a method for manufacturing a semiconductor device with a vertical gate, a substrate(21) is etched to form a plurality of active pillars(24). A vertical gate(27) surrounds the side of the active pillar. A liner silicon film is formed over a side including a vertical gate. A spin-on insulation layer(29) for separating vertical gates is formed on the liner silicon film. An anneal is performed to harden the spin-on insulation layer.

Description

Method of manufacturing semiconductor device with vertical gate {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH VERTICAL GATE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a vertical gate.

As the design rules of semiconductor devices become smaller and smaller, there are many difficulties in manufacturing semiconductor devices of 40 nm or less. In order to overcome this problem, researches on the formation of vertical gates rather than horizontal gates have been conducted.

1A and 1B illustrate a method of manufacturing a semiconductor device having a vertical gate according to the prior art.

Referring to FIG. 1A, the substrate 11 is etched using the pad oxide film 12 and the hard mask film 13 to form a plurality of active pillars 14.

Subsequently, a buried bit line 15 is formed through ion implantation of impurities in the substrate 11 between the active pillars 14.

Subsequently, a gate insulating film 16 is formed on the entire surface.

Subsequently, after the gate conductive film is formed on the entire surface along the profile of the structure including the gate insulating layer 16, the gate conductive layer is etched back to form a vertical gate 17 that surrounds the sidewall of the active pillar 14.

Subsequently, a spin on dielectric (SOD) is gap-filled as the separator 18 for separation between the vertical gates 17.

As shown in FIG. 1B, a trench 19 is formed that separates buried bit lines 15A and 15B.

However, the prior art is a pillar leaning caused by using a spin-on insulating film (SOD) excellent in the gap fill ability (flow) excellent in the flow characteristics in forming a separator between the vertical gate (17). This is a big problem.

The spin-on insulating film (SOD) is essentially accompanied by an annealing process for hardening. During this annealing process, volume shrinkage occurs to have a tensile stress. During the trench 19 etching process for separating the subsequent buried bit lines 15A and 15B, tensile stress is applied to the bulky side depending on the extent of the spin-on insulating film remaining after etching around the active pillars 14. According to the load, the active pillar 14 may fall, and when the trench 19 is etched, the active pillar 14 may be attacked.

The present invention has been proposed to solve the problems according to the prior art, to provide a semiconductor device manufacturing method that can prevent the fall of the active pillar due to the tensile stress of the spin-on insulating film used as the vertical gate-to-gate separator. The purpose is.

The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a plurality of active pillars by etching the substrate; Forming a vertical gate surrounding a sidewall of the active pillar; Forming a liner silicon film on the entire surface including the vertical gate; Forming a spin-on insulating film on the liner silicon film to separate the vertical gates; And an annealing step for curing the spin-on insulating film.

In addition, the semiconductor device manufacturing method of the present invention comprises the steps of forming a plurality of active pillars by etching the substrate; Forming a metal gate surrounding a sidewall of the active pillar; Forming a capping film on the entire surface including the metal gate; Forming a liner silicon film on the capping film; Forming a spin-on insulating film on the liner silicon film to separate the metal gates; And an annealing step for curing the spin-on insulating film.

According to the present invention, the liner silicon film is formed in advance before the formation of the separator, and even though the trench etching process for separating the subsequent buried bitline is performed, the tensile stress caused by the spin-on insulating film used as the separator is canceled to prevent the collapse of the active pillar. It can be effective.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

As shown in FIG. 2A, the active pillars 24 are formed on the substrate 21.

The active pillar 24 is a pillar structure arranged in a dot matrix form and is an active region in which a channel of a transistor is formed. The active pillar 24 has a rod-type structure having a neck free structure without a neck pillar, and having a neck structure allows a stable structure resistant to collapse.

The active pillars 24 are formed through an etching process using a pad oxide layer 22 and a hard mask layer 23. The substrate 21 includes a silicon substrate. Since the substrate 21 is a silicon substrate, the etching process for forming the active pillars 24 may be performed by using a Cl ₂ or HBr gas alone or by a dry etching method using a mixed gas of Cl ₂ and HBr gas. The hard mask film 23 includes a nitride film such as a silicon nitride film.

Subsequently, impurities are implanted into the substrate 21 between the active pillars 24 to form buried bit lines BBL 25. Here, the buried bit line 25 may be formed by ion implanting N-type impurities such as phosphorus (Ph) and arsenic (As), and proceed with the concentration of the impurities to be 1 × 10 ¹⁵ atoms / cm ³ or more. .

The buried bit line 25 may be formed in a process after forming an annular vertical gate that surrounds the active pillars 24, but it is easy to secure an area to form a buried bit line of sufficiently low resistance, It is desirable to create the buried bitline 25 immediately after the formation of the active pillar 24 which is sufficiently processable.

Subsequently, a gate insulating film 26 is formed. In this case, the gate insulating layer 26 may be formed by deposition, thermal oxidation, or radical oxidation. The thickness of the gate insulating film 26 is 30-80 kPa.

Subsequently, the gate conductive layer is formed on the entire surface of the structure including the gate insulating layer 26 and then etched back. As a result, a vertical gate 27 is formed to surround sidewalls of the active pillars 24, the pad oxide layer 22, and the hard mask layer 23. The gate conductive film used as the vertical gate 27 may include a metallic layer such as a metal film or a metal nitride film, or may include a polysilicon film. For example, the metallic film used as the gate conductive film includes a tungsten film W, a titanium nitride film TiN, or a tantalum nitride film TaN.

As shown in FIG. 2B, a liner silicon layer Si liner 28 is formed on the entire surface including the vertical gate 27. The liner silicon film 28 is intended to relieve the tensile stress caused by the subsequent separator.

The liner silicon film 28 is oxidized during the subsequent wet annealing process to have a compressive stress, thereby alleviating the tensile stress caused by the separator.

The liner silicon layer 28 may be deposited using a furnace type low pressure chemical vapor deposition (LPCVD) or a single type (sub-atmosphere chemical vapor deposition). Then, the deposited using a SiH ₄ gas as a raw material at a temperature of 490~600 ℃. Accordingly, the liner silicon film 28 has an amorphous silicon structure.

As shown in FIG. 2C, a separator 29 is formed on the liner silicon film 28 to separate the neighboring vertical gates 27. The separator 29 may be formed on the front surface so as to gap-fill the space between the active pillars 24 surrounded by the vertical gate 27, and may be subsequently planarized by using chemical mechanical polishing (CMP).

The separator 29 may be formed using spin on coating to void-free gapfill between the vertical gates 27. That is, the separator 29 includes a spin-on insulating film SOD. The spin-on insulating layer SOD is coated with polysilazane PSZ and then wet annealed. The wet annealing proceeds at a high temperature capable of sufficiently oxidizing the liner silicon film 28. For example, it advances at the high temperature of at least 700 degreeC or more (700-1000 degreeC), and all the liner silicon film 28 is oxidized and is converted into the liner silicon oxide film 28A. The liner silicon film has a compressive stress as the volume expands as it is oxidized. As a result, the tensile stress caused by the spin-on insulating film used as the separator 29 is canceled by the compressive stress of the liner silicon oxide film 28A.

In addition, when the high-temperature wet annealing proceeds as described above, the treatment and further annealing can be omitted, thereby simplifying the process. In other words, after forming the spin-on insulating film without the liner silicon film, it is necessary to perform 300 ° C. wet annealing, two treatments using hot distilled water (Hot DI), and additional annealing. When the wet annealing is carried out at a high temperature (700 to 1000 ° C.), the effects of the treatment and further annealing can be obtained at once.

As shown in FIG. 2D, the separation process of the buried bit line 25 is performed. That is, the buried bit lines 25A and 25B are etched by a predetermined depth by etching the separator 29, the liner silicon oxide film 28A, the gate insulating film 26, and the substrate 21 through a BBL (Buried BitLine) mask process (not shown). To form a trench 30 that separates it. The trench 30 has a depth of 1000 to 3000 mm 3.

3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

As shown in FIG. 3A, the active pillar 34 is formed on the substrate 31.

The active pillar 34 is a pillar structure arranged in a dot matrix form and is an active region in which a channel of a transistor is formed. The active pillar 34 has a rod-type structure having a neck free structure without a neck pillar. When the active pillar 34 has a neck structure, a stable structure resistant to collapse can be obtained.

The active pillar 34 is formed through an etching process using a pad oxide layer 32 and a hard mask layer 33. The substrate 31 includes a silicon substrate. Since the substrate 31 is a silicon substrate, the etching process for forming the active pillar 34 may be performed by using a Cl ₂ or HBr gas alone, or a dry etching method using a mixed gas of Cl ₂ and HBr gas. The hard mask film 33 includes a nitride film such as a silicon nitride film.

Subsequently, impurities are implanted into the substrate 31 between the active pillars 34 to form buried bit lines BBL 35. Here, the buried bit line 35 can be formed by ion implanting N-type impurities such as phosphorus (Ph) and arsenic (As), and proceed with the concentration of impurities to be 1 × 10 ¹⁵ atoms / cm ³ or more. .

The buried bit line 35 may be formed in a process after forming an annular vertical gate, but an active pillar which is easy to secure an area and is sufficiently capable of a process such as silicide to form a buried bit line having a sufficiently low resistance ( 24) It is preferable to create the buried bit line 35 immediately after formation.

Subsequently, a gate insulating film 36 is formed. In this case, the gate insulating layer 36 may be formed by deposition, thermal oxidation, or radical oxidation. The thickness of the gate insulating film 36 is 30 to 80 kPa.

Subsequently, the gate conductive layer is formed on the entire surface of the structure including the gate insulating layer 36 and then etched back. As a result, a vertical gate 37 surrounding sidewalls of the active pillar 34, the pad oxide layer 32, and the hard mask layer 33 is formed. The gate conductive film used as the vertical gate 37 may include a metal layer such as a metal film or a metal nitride film, or may include a polysilicon film. Hereinafter, the gate conductive film is referred to as a metallic film, and the metallic film includes a tungsten film W, a titanium nitride film TiN, or a tantalum nitride film TaN.

As shown in FIG. 3B, a liner silicon film Si liner 39 is formed on the entire surface including the vertical gate 37. The liner silicon film 39 is for relieving the tensile stress caused by the subsequent separator.

The liner silicon film 39 is oxidized during the subsequent wet annealing process to have a compressive stress, thereby alleviating the tensile stress by the separator.

When the vertical gate 37 is a metallic film, the capping film 38 may be formed in advance before the liner silicon film 39 is formed. In this case, the capping film 38 includes a nitride film. The capping layer 38 prevents the vertical gate 37 from oxidizing in a subsequent process. Here, the subsequent process includes an annealing process for curing the spin-on insulating film used as the separator.

As shown in FIG. 3C, a separator 40 for separation between adjacent vertical gates 37 is formed on the liner silicon layer 39. The separator 29 may be formed on the front surface to gap-fill the space between the active pillars 34 on which the vertical gate 37 is formed, and then the planarization process may be performed by using chemical mechanical polishing (CMP).

The separator 40 may be formed using spin on coating to void-fill gaps between the active pillars. That is, the separator 40 includes a spin-on insulating film SOD. The spin-on insulating film SOD is subjected to wet annealing after coating polysilazane (PSZ). The wet annealing proceeds at a high temperature capable of sufficiently oxidizing the liner silicon film 39. For example, the process proceeds at a high temperature of 700 ° C. or higher, whereby all of the liner silicon film is oxidized and converted into the liner silicon oxide film 39A. The liner silicon film has a compressive stress as the volume expands as it is oxidized. As a result, the tensile stress caused by the spin-on insulating film is canceled out by the compressive stress of the liner silicon oxide film 39A.

As shown in FIG. 3D, the separation process of the buried bit line 35 is performed. That is, the buried bit is etched by a predetermined depth by etching the separator 40, the liner silicon oxide film 39A, the capping film 38, the gate insulating film 36, and the substrate 31 through a BBL (Buried BitLine) mask process (not shown). A trench 41 is formed that separates the lines 35A and 35B. The trench 41 has a depth of 1000 to 3000 mm 3.

According to the embodiments described above, the present invention introduces a liner silicon film to cancel the tensile stress caused by the spin-on insulating film used as a separator. As such, when the liner silicon film is introduced, the active pillar does not fall even when the trench etching process for separating the subsequent buried bit line is performed.

In another embodiment, a linear oxide such as LPTEOS (Low Pressure Tetra Ethyl Ortho Silicate) may be directly deposited to offset the tensile stress caused by the spin-on insulating film. However, the liner oxide film has a limitation in preventing the fall of the active pillar.

FIG. 4A is a photograph when LPTEOS is used as a liner film and SOD is used as a separation film, and FIG. 4B is a photograph when a silicon film is used as a liner film and SOD is used as a separation film.

Referring to FIGS. 4A and 4B, when LPTEOS is used as the liner film, the active pillars are collapsed. However, when the silicon film is used as the liner layer, the active pillars are not collapsed.

Particularly, in the case of the combination of LPTEOS and SOD, SOD has a tensile stress of 96 MPa based on a plate after wet annealing at 350 ° C. and a high tensile stress of 360 MPa through 700 ° C. N ₂ annealing. The present invention is to apply a liner silicon film as a method that can mitigate such tensile stress.

In addition, when using a combination of LPTEOS and SOD, the process is very complicated because multiple treatments and annealing processes for SOD are added. However, in the case of a combination of liner silicon and SOD, such a process can be omitted to simplify the process. It is possible to obtain additional effects.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A and 1B illustrate a method of manufacturing a semiconductor device having a vertical gate according to the prior art.

2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

4A is a photograph when LPTEOS is used as a liner membrane and SOD is used as a separator.

4B is a photograph when the silicon film is used as the liner film and the SOD is used as the separation film.

* Explanation of symbols for the main parts of the drawings

31 substrate 32 pad oxide film

33: hard mask film 34: active pillar

35A, 35B: buried bit line 36: gate insulating film

37: vertical gate 38: capping film

39: liner silicon film 39A: liner silicon oxide film

40: separator 41: trench

Claims (11)

Etching the substrate to form a plurality of active pillars; Forming a vertical gate surrounding a sidewall of the active pillar; Forming a liner silicon film on the entire surface including the vertical gate; Forming a spin-on insulating film on the liner silicon film to separate the vertical gates; And Annealing step for curing the spin-on insulating film A semiconductor device manufacturing method comprising a. The method of claim 1, The liner silicon film, A semiconductor device manufacturing method formed using SiH ₄ . The method of claim 1, The annealing step, A method of manufacturing a semiconductor device using a high temperature wet annealing method in which the liner silicon film is oxidized. The method of claim 3, The annealing step, A method for manufacturing a semiconductor device that proceeds at a temperature of at least 700 ° C or higher. The method of claim 1, And the liner silicon film is formed using LPCVD or SACVD using SiH ₄ gas as a raw material at a temperature of 490 to 600 캜. Etching the substrate to form a plurality of active pillars; Forming a metal gate surrounding a sidewall of the active pillar; Forming a capping film on the entire surface including the metal gate; Forming a liner silicon film on the capping film; Forming a spin-on insulating film on the liner silicon film to separate the metal gates; And Annealing step for curing the spin-on insulating film A semiconductor device manufacturing method comprising a. The method of claim 6, The silicon liner film, A semiconductor device manufacturing method formed using SiH ₄ . The method of claim 6, The annealing step, A method of manufacturing a semiconductor device employing a high temperature wet annealing method in which the silicon liner film is oxidized. The method of claim 8, The annealing step, A method for manufacturing a semiconductor device that proceeds at a temperature of at least 700 ° C or higher. The method of claim 6, And the liner film is formed using LPCVD or SACVD using SiH ₄ gas at a temperature of 490 to 600 캜. The method of claim 6, And the capping film comprises a nitride film.

Images