KR20110002243A - Method of program operating for nonvolatile memory device - Google Patents

Method of program operating for nonvolatile memory device Download PDF

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Publication number
KR20110002243A
KR20110002243A KR1020090059739A KR20090059739A KR20110002243A KR 20110002243 A KR20110002243 A KR 20110002243A KR 1020090059739 A KR1020090059739 A KR 1020090059739A KR 20090059739 A KR20090059739 A KR 20090059739A KR 20110002243 A KR20110002243 A KR 20110002243A
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South Korea
Prior art keywords
pass voltage
voltage
program
pass
line
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KR1020090059739A
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Korean (ko)
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김도영
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주식회사 하이닉스반도체
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Priority to KR1020090059739A priority Critical patent/KR20110002243A/en
Publication of KR20110002243A publication Critical patent/KR20110002243A/en

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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/08Address circuits; Decoders; Word-line control circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series

Abstract

The present invention relates to a method of programming a nonvolatile memory device capable of improving a pass disturb phenomenon of a program cell.
The present invention provides a method of applying a first pass voltage to non-selected word lines other than a selected one of a plurality of word lines between a source select line and a drain select line, and applying the first pass voltage during a first period. And after applying, applying the first pass voltage to the second pass voltage for the second period. Here, a program voltage is applied to the selected word line during the first and second periods.
Pass disturb, pass voltage

Description

Method of program operating for nonvolatile memory device
The present invention relates to a method of operating a nonvolatile memory device, and more particularly, to a method of programming a nonvolatile memory device.
NAND flash memory devices among nonvolatile memory devices are easy to increase the degree of integration, and thus are widely used in applications requiring high capacity data storage.
The memory cell array of NAND flash memory devices includes a plurality of string structures. Each string structure includes a source select transistor, a drain select transistor, and a plurality of memory cells connected in series between the source select transistor and the drain select transistor. The drain select transistor selectively connects the string and the bit line. The source select transistor also selectively connects the common source line connected to the string and ground. Here, memory cells of a string structure arranged in parallel with each other are electrically connected through word lines. The source select transistors of the string structure arranged in parallel with each other are connected through the source select line, and the drain select transistors are connected through the drain select line. Accordingly, a plurality of word lines are disposed between the source select line and the drain select line.
The above-described program of the NAND flash memory device is implemented by applying a program voltage to sequentially selected word lines from word lines adjacent to the source select line to word lines adjacent to the drain select line. In this case, since memory cells of a string structure adjacent to each other are connected through a word line, memory cells connected to a selected word line may be a program target (hereinafter, referred to as a "program cell") and a program target according to data to be stored. It may be divided into non-cells (hereinafter, referred to as "program inhibited cells"). Therefore, even though the program voltage is applied to the selected word line, the program cell can be programmed, but the channel inhibiting channel is used to prevent the program cell from being programmed.
More specifically, in order to program only the program cell, applying a voltage of 0V to the source select line prevents the string structure from being connected to the ground path. In addition, a voltage of 0 V is applied to the bit line connected to the string structure including the program cell, and a power supply voltage is applied to the bit line connected to the string structure including the program inhibiting cell. Then, a power supply voltage is applied to the drain select line. Accordingly, a voltage equal to the difference between the power supply voltage applied to the bit line and the threshold voltage of the drain select transistor is precharged in the channel region of the string structure including the program inhibiting cell. Thereafter, a program voltage is applied to the selected word line, and a pass voltage is applied to the unselected word lines. As a result, the channel select phenomenon occurs in the channel region of the string structure including the program inhibiting cell, and the drain select transistor is turned off. Therefore, since the FN tunneling does not occur in the program inhibiting cell, the threshold voltage of the program inhibiting cell does not increase.
In this case, in order to prevent the threshold voltage of the program inhibiting cell from rising, it is preferable to apply a high pass voltage to prevent program disturb. Meanwhile, the pass voltage is applied until the program voltage is applied to the word line to which the program cell is connected. Accordingly, as the pass voltage increases, a pass disturb phenomenon occurs in which the program cell is programmed to an unwanted threshold voltage by the pass voltage.
It is preferable to apply the pass voltage within an appropriate range in consideration of the correlation between the pass disturb phenomenon, the program disturb phenomenon, and the pass voltage as described above. However, even if the pass voltage is selected and applied within an appropriate range, there is a limit in improving the pass disturb phenomenon.
FIG. 1 is a diagram for explaining a cause that affects a pass disturb phenomenon when a specific pass voltage is applied. For reference, FIG. 1 illustrates a threshold voltage change due to a pass disturb phenomenon when a specific pass voltage is applied in consideration of the correlation between the pass disturb phenomenon, the program disturb phenomenon, and the pass voltage.
Referring to FIG. 1, a pass disturb is applied by the effective field oxide height (EFH) of the device isolation layer (ie, the height of the device isolation layer protruding from the surface of the semiconductor substrate) and the pass voltage applied to a specific memory cell until the program is completed. Loss is related to stress.
More specifically, when the EFH of the device isolation layer decreases, the change of the threshold voltage due to the pass disturb phenomenon tends to increase. On the other hand, as the EFH decreases, the number of pulses (hereinafter, referred to as "NOP") of the pass voltage applied to the specific memory cell tends to increase until the program of the specific memory cell is completed. As the NOP increases, the stress applied to the program cell due to the pass voltage increases, so that the change in the threshold voltage due to the pass disturb phenomenon becomes more severe.
Therefore, if the EFH of the device isolation layer is formed lower than the target range according to the high integration of the device, and if the stress applied to the program cell is increased due to the pass voltage, the failure due to the pass disturb occurs. This further increases the problem.
The present invention provides a method of programming a nonvolatile memory device capable of improving a pass disturb phenomenon of a program cell.
A method of programming a nonvolatile memory device having a plurality of word lines formed between a source select line and a drain select line, according to an embodiment of the present invention. Applying a first pass voltage, and applying the first pass voltage during a first period, and then lowering the first pass voltage to a second pass voltage to apply the second pass voltage for a second period. And a program voltage is applied to the selected word line during the second period.
The second pass voltage is set to be 1V to 3V lower than the first pass voltage.
In the second exemplary embodiment of the present invention, in the method of programming a nonvolatile memory device in which a plurality of word lines are formed between a source select line and a drain select line, a first pass may be performed on a plurality of groups of unselected word lines including a first group. Applying a voltage; And maintaining a first pass voltage applied to the unselected word lines of the first group, and lowering and applying the first pass voltage applied to the unselected word lines of the plurality of groups to a second pass voltage. The first and second pass voltages are applied while the program voltage is applied to the selected word line.
The first group includes word lines disposed between the source select line and the selected word line among the plurality of word lines.
The second pass voltage is set to be 1V to 3V lower than the first pass voltage.
The method may further include applying a voltage for shorting a channel to an unselected word line adjacent to a group to which the second pass voltage is applied when the voltage is lowered to the second pass voltage.
The voltage for shorting the channels is greater than 0V and less than 3V.
An unselected word line to which a voltage for shorting the channel is applied is adjacent to the outermost word line toward the source select line of the group to which the second pass voltage is applied.
Lowering and applying the second pass voltage is sequentially performed from a group adjacent to the drain select line to a group adjacent to the source select line among the plurality of groups.
And lowering the first pass voltage to a third pass voltage lower than the second pass voltage to an unselected word line except for the group to which the second pass voltage is applied.
The third pass voltage is applied to an unselected word line of a group to which the third pass voltage is applied when the second pass voltage is applied.
When a second pass voltage lower than the first pass voltage is applied to the plurality of unselected word lines, a low pass voltage is sequentially applied from a group adjacent to the drain select line to a group adjacent to the source select line. .
The present invention can improve the pass disturb phenomenon of the program cell by reducing the stress applied by the pass voltage.
In addition, the present invention improves the path disturb phenomenon by sequentially lowering the pass voltage while applying the existing channel boosting phenomenon, so that the present invention can be immediately applied to the existing nonvolatile memory device without applying an additional process.
In addition, when the present invention is applied to a case where the height of the device isolation layer is locally low due to the high integration of the device, the effect of improving the pass disturb phenomenon may be further increased. Accordingly, the present invention can improve the stability of the highly integrated device by improving the cell characteristic deterioration caused by the high integration.
In addition, the present invention can prevent the loss of time required to complete the program by lowering the pass voltage within the time range that the existing pass voltage is applied.
On the other hand, the present invention can improve the boosting efficiency by sequentially lowering the pass voltage for each group from the group adjacent to the drain select line. Accordingly, the present invention can maintain the overall boosting potential of the cell string including the program inhibited cell.
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.
2 is a view for explaining a nonvolatile memory device according to the present invention. 2 is a diagram illustrating a NAND flash memory device among the nonvolatile memory devices.
Referring to FIG. 2, the memory cell array 210 of the nonvolatile memory device according to the present invention includes a plurality of string structures 220. Each string structure 220 includes a plurality of memory cells MC connected in series between a source select transistor SST and a drain select transistor DST. Memory cells MC of the string structure 220 arranged side by side are connected through word lines WL. The source select transistors SST of the string structure 220 arranged side by side are connected through the source select line SSL. The drain select transistors DST of the string structure 220 arranged side by side are connected through the drain select line DSL.
The drain select transistor DST described above selectively connects the string structure 220 and the bit line BL. In addition, the source select transistor SST selectively connects the string structure 220 and the common source line CSL connected to ground. The string structures 220 connected to the bit lines BL are connected to the common source line CSL in parallel to form a memory block BLock.
3A and 3B are timing diagrams for describing a method of programming a nonvolatile memory device according to a first embodiment of the present invention.
2 and 3A, the bit line BL is set up at the beginning of a program operation. During the bit line BL setup operation, a power supply voltage or a ground voltage of 0V is applied to the bit line BL. More specifically, 0 V is applied to the bit line BLpgm of the program mode connected to the program cell MCpgm. On the other hand, a power supply voltage is applied to the bit line BLinh of the program inhibit mode connected to the program inhibit cell MCinh. Meanwhile, the string structure 220 is blocked from being connected to the ground path by applying a voltage of 0V to the source select line SSL. Then, a power supply voltage Vcc is applied to the drain select line DSL. Accordingly, the channel region of the string structure 220 including the program inhibiting cell MCinh may have a voltage equal to the difference between the power supply voltage applied to the bit line BLh of the program inhibiting mode and the threshold voltage of the drain select transistor DST. Precharged.
A word line voltage is applied to each word line WL at the time t0 when the bit line BL setup is completed. At this time, the voltage applied to the drain select line DSL can be reduced to a level higher than the ground voltage and lower than the power supply voltage Vcc in order to more reliably turn off the drain select transistor connected to the program inhibiting cell MCinh. have. Referring to the voltage applied to the word line WL in detail, first, a pass voltage Vpass is applied to all the word lines WL. The pass voltage Vpass is preferably applied within an appropriate range in consideration of the correlation between the pass disturb phenomenon, the program disturb phenomenon, and the pass voltage. More specifically, the pass voltage Vpass is preferably selected within the range of 7.0V to 9.5V.
After the time point t1 at which the pass voltage Vpass is applied to all word lines WL, the program voltage Vpgm is applied to the selected word line WLsel, and the remaining word lines except for the selected word line WLsel. The pass voltage Vpass is maintained and applied to WLunsel (hereinafter, referred to as "unselected word line"). When the program voltage Vpgm is applied to the selected word line WLsel and the pass voltage Vpass is applied to the unselected word line WLunsel, the string structure 220 including the program inhibit cell MCinh. The channel boost phenomenon occurs in the channel region of the drain select transistor DST connected to the string structure 220 is turned off. Therefore, since the FN tunneling does not occur in the program inhibit cell MCinh, the threshold voltage of the program inhibit cell MCinh does not increase.
As described above, even if the pass voltage Vpass is selected and applied within an appropriate range, there is a limit in improving the pass disturb phenomenon. In order to overcome this limitation, it is preferable to perform the program operation in a manner as shown in FIG. 3B.
2 and 3B, the bit line BL is set up at the beginning of a program operation. The bit line BL setup operation is the same as described above with reference to FIG. 3A.
A word line voltage is applied to each word line WL at the time t0 when the bit line BL setup is completed. At this time, the voltage applied to the drain select line DSL can be reduced to a level higher than the ground voltage and lower than the power supply voltage Vcc in order to more reliably turn off the drain select transistor connected to the program inhibiting cell MCinh. have. Referring to the voltage applied to the word line WL in detail, first, the first pass voltage Vpass1 is applied to all the word lines WL. The first pass voltage Vpass1 may be applied within an appropriate range in consideration of a correlation between a pass disturb phenomenon, a program disturb phenomenon, and a pass voltage. More specifically, the first pass voltage Vpass1 is preferably selected within the range of 7.0V to 9.5V. For example, 9V may be applied to the first pass voltage Vpass1.
After the time point t1 at which the pass voltage Vpass is applied to all word lines WL, the program voltage Vpgm is applied to the selected word line WLsel. In addition, while the program voltage Vpgm is applied to the selected word line WLsel, the first pass voltage Vpass1 is maintained and applied to the unselected word line WLunsel, which is lower than the first pass voltage Vpass1 and is grounded. A higher second pass voltage Vpass2 is applied. That is, the first pass voltage Vpass1 is lowered to the second pass voltage Vpass2. As such, when the program voltage Vpgm and the first pass voltage Vpass1 are applied, a channel boosting phenomenon occurs in the channel region of the string structure 220 including the program inhibiting cell MCinh, and is applied to the string structure 220. The connected drain select transistor DST is turned off. Therefore, since the FN tunneling does not occur in the program inhibit cell MCinh, the threshold voltage of the program inhibit cell MCinh does not increase.
Meanwhile, when the pass voltage applied to the unselected word line WLunsel is lowered from the first pass voltage Vpass1 to the second pass voltage Vpass2, the memory cell connected to the unselected word line WLunsel by the pass voltage ( Reduce stress on the MCs.
The stress exerted on the memory cell MC connected to an arbitrary unselected word line WLunsel by the pass voltage includes the unit pulse width of the pass voltage pulse, the amplitude of the pass voltage pulse, and an arbitrary unselected word line. It is proportional to the number of pass voltages applied to the memory cells MC connected to WLunsel. On the other hand, the program operation sequentially applies a program voltage from word line WL0 adjacent to the source select line SSL to n word line WLn adjacent to the drain select line DSL (n is a natural number). This is done by. Accordingly, the pass voltage is applied to any unselected word line WLunsel until the program of the memory cell connected to the previous short word line of the unselected word line WLunsel is completed. For example, when any unselected word line WLunsel is a word line 31, a pass voltage is applied to the word line 31 until a program of a memory cell connected to the word line 30 is completed. Assume that memory cells store two bits of data, a program operation is divided into a first program operation and a second program operation, and each program operation is performed using an increasing step plus program (ISPP) method.
The first program operation is to raise the threshold voltage of the memory cell from the erase level to the first level, and the second program operation to raise the threshold voltage of the memory cell from the erase level to the second level after the first program operation, The operation is for raising from the first level to the third level. In the ISPP method, a program is repeatedly executed in a predetermined loop only for an unprogrammed cell, and the program voltage Vpgm is increased by a constant step voltage each time the program is repeated. Since the pass voltage is applied whenever the program voltage Vpgm is applied to another word line to word line 31, the program operation divided into the first program and the second program as described above is performed using the ISPP method. The number of pass voltage pulses (hereinafter referred to as "NOP") applied to word line 31 is as follows.
NOP applied to word line 31 = (number of ISPP program pulses applied to the first program operation + number of ISPP program pulses applied to the second program operation + number of additional program pulses applied to the second program operation) x 31 loops
On the other hand, the stress applied to the memory cell by the pass voltage is proportional to (the duration of the pass voltage pulse) x (the magnitude of the pass voltage) x (NOP).
In view of the foregoing, the stress applied to the memory cell by the pass voltage in each of FIGS. 3A and 3B is reduced. When the method of FIG. 3B is used rather than the method of FIG. 3A, the stress applied to the memory cell by the pass voltage is reduced. Can be. This is because the average magnitude of the pass voltages in the limited time range where the program voltage Vpgm is maintained and applied is lower in FIG. 3B than in FIG. 3A. That is, in FIG. 3A, the pass voltage is maintained at a specific pass voltage Vpass. In contrast, in FIG. 3B, the pass voltage is lowered from the first pass voltage Vpass1 to the second pass voltage Vpass2. As a result, when the method of FIG. 3B is used rather than the method of FIG. 3A, stress due to a pass voltage can be reduced. Here, the second pass voltage Vpass2 is preferably set to 1V to 3V lower than the first pass voltage Vpass1.
After applying the second pass voltage Vpass2 for a predetermined time, the channel voltage of the program inhibiting cell MCinh is completed by lowering the pass voltage applied to the unselected word line WLunsel to 0V.
As described above, according to the first embodiment of the present invention, the first pass voltage Vpass1 is applied to the unselected word line WLunsel by dividing the time for which the program voltage Vpgm is maintained and applied into the first and second sections. The second pass voltage Vpass2 is applied to the unselected word line WLunsel during the subsequent second period. Accordingly, in the first embodiment of the present invention, the stress applied to the memory cells connected to the unselected word line WLunsel by the pass voltage when the program voltage Vpgm is applied can be reduced. In addition, according to the first embodiment of the present invention, even if any one of the memory cells connected to the unselected word line WLunsel is selected as the program cell, the pass disturb phenomenon may be improved.
On the other hand, in the first embodiment of the present invention it is possible to prevent the loss of time required to complete the program by lowering the pass voltage within the time range to which the existing pass voltage is applied. More specifically, in the first embodiment of the present invention, the loss of time required to complete the program can be prevented by lowering the pass voltage within a limited time range to which the program voltage Vpgm is applied.
4 is a timing diagram illustrating a program method of a nonvolatile memory device according to a second embodiment of the present invention.
2 and 4, in the second embodiment of the present invention, the word line WL is divided into a plurality of groups to control the word line voltage applied to the word line WL for each group. In this case, the unselected word lines WLunsel disposed between the selected word line WLsel and the source select line SSL are included in the first group G1. The unselected word lines WLunsel are divided into a plurality of groups (eg, G1, G2, G3, and G4) in addition to the first group G1. Hereinafter, a program method according to a second embodiment of the present invention will be described in more detail.
First, the bit line BL is set up at the beginning of the program operation. The bit line BL setup operation is the same as described above with reference to FIG. 3A.
A word line voltage is applied to each word line WL at the time t0 when the bit line BL setup is completed. At this time, the voltage applied to the drain select line DSL can be reduced to a level higher than the ground voltage and lower than the power supply voltage Vcc in order to more reliably turn off the drain select transistor connected to the program inhibiting cell MCinh. have.
In the second embodiment of the present invention, a voltage applied to the word line WL will be described in detail. First, the first pass voltage Vpass1 is applied to all the word lines WL. The first pass voltage Vpass1 may be applied within an appropriate range in consideration of a correlation between a pass disturb phenomenon, a program disturb phenomenon, and a pass voltage. More specifically, the first pass voltage Vpass1 is preferably selected within the range of 7.0V to 9.5V. For example, 9V may be applied to the first pass voltage Vpass1.
After the time point t1 at which the first pass voltage Vpass1 is applied to all word lines WL, the program voltage Vpgm is applied to the selected word line WLsel.
The first pass voltage Vpass1 is maintained and applied to the unselected word lines WLunsel of the first group G1 while the program voltage Vpgm is applied to the selected word line WLsel. The first pass voltage Vpass1 is applied to the unselected word lines WLunsel of the plurality of groups G2, G3, and G4 while the program voltage Vpgm is applied to the selected word line WLsel. The pass voltage Vpass1 is lowered to the second pass voltage Vpass2 and applied. Here, the second pass voltage Vpass2 is lower than the first pass voltage Vpass1 and higher than the ground voltage. More specifically, the second pass voltage Vpass2 is preferably set to 1V to 3V lower than the first pass voltage Vpass1.
When the program voltage Vpgm is applied to the selected word line WLsel and the first pass voltage Vpass1 is applied to the unselected word line WLunsel, the string structure including the program inhibit cell MCinh ( As the channel boosting phenomenon occurs in the channel region of 220, the drain select transistor DST connected to the string structure 220 is turned off. Therefore, since the FN tunneling does not occur in the program inhibit cell MCinh, the threshold voltage of the program inhibit cell MCinh does not increase.
In the second embodiment of the present invention, the first pass voltage Vpass1 is maintained while being applied to the first group unselected word line WLunsel including the program inhibiting cell MCinh while the program voltage Vpgm is applied. do. Accordingly, since a relatively high first pass voltage Vpass1 is maintained and applied to some word lines while the program voltage Vpgm is applied, channel boosting efficiency of the program inhibiting cell MCinh may be increased.
Meanwhile, in the second embodiment of the present invention, since the first pass voltage Vpass1 applied to the plurality of groups G2, G3, and G4 is lowered to the second pass voltage Vpass2, it is not selected as described in the first embodiment. The stress applied to the memory cells connected to the word line WLunsel may be reduced. Accordingly, according to the second embodiment of the present invention, even if any one of the memory cells included in the plurality of groups G2, G3, and G4 is selected as a program cell, a pass disturb phenomenon may be improved.
When the second pass voltage Vpass2 is applied to the unselected word lines WLunsel of the plurality of groups G2, G3, and G4, the application time points are sequentially applied to the first to third time points t21, t22, and t23. Can be set. More specifically, the second pass voltage Vpass2 may be sequentially applied from the group adjacent to the drain select line DSL to the group adjacent to the source select line SS among the plurality of groups G2, G3, and G4. For example, assume that the second group G2 is nearest to the drain select line DSL, and the fourth group G4 is located farthest from the drain select line DSL. In this case, the second pass voltage Vpass2 is applied to the second group G2 at the first time point t21, and at the second time point t22 that is later than the first time point t21 in the third group G3. Preferably, the second pass voltage Vpass2 is applied, and the second pass voltage Vpass2 is applied to the fourth group G4 at a third time point t23 that is later than the second time point t22.
As described above, when the second pass voltage Vpass2 is sequentially applied from the group adjacent to the drain select line DSL, the pass voltage is lowered from the group farthest from the selected word line WLsel. Accordingly, since the relatively high first pass voltage Vpass1 may be applied for a longer time, the boosting efficiency of the program inhibiting cell MCinh may be further improved.
In addition, when the second pass voltage Vpass2 lower than the first pass voltage Vpass1 is applied to the unselected word lines WLunsel of the plurality of groups G2, G3, and G4, the group adjacent to the drain select line DSL. Low pass voltages may be sequentially applied from the group G2 to the group G4 adjacent to the source select line SSL. In this case, while a relatively high pass voltage can be applied for a long time while the program voltage is applied, stress applied to memory cells connected to the unselected word line WLunsel can be reduced.
Meanwhile, the unselected word lines WLunsel of the plurality of groups G2, G3, and G4 are groups WLunsel2 to which the second pass voltage Vpass2 is applied and groups WLunsel1 to which the third pass voltage Vpass3 is applied. Can be distinguished. The third pass voltage Vpass3 may be higher than the ground voltage 0V but lower than the second pass voltage Vpass2.
The third pass voltage Vpass3 described above is applied when the second pass voltage Vpass2 is applied. The third pass voltage Vpass3 may be a voltage for turning off the memory cell MC to short the channel. In this case, the third pass voltage Vpass3 is preferably applied to the unselected word lines WLunsel of the plurality of groups G2, G3, and G4 located at the boundary between the groups G1, G2, G3, and G4. That is, when the third pass voltage Vpass3 is a voltage that turns off the memory cell MC, the third pass voltage Vpass3 is a source of the group WLunsel2 to which the second pass voltage Vpass2 is applied. It is preferably applied to the unselected word line WLunsel1 adjacent to the outermost word line on the select line SSL side.
Specifically, the first unselected word line WLunsel1 positioned at the boundary between the third and fourth groups G3 and G4 among the unselected word lines WLunsel included in the fourth group G4 at the first time point t21. ) May apply a third pass voltage Vpass3. In this case, the second pass voltage Vpass2 applied at the first time point t21 may be the remaining second except for the first unselected word line WLunsel1 among the unselected word lines WLunsel included in the fourth group G4. 2 is applied to the unselected word line WLunsel2. Also, at the second time point t22, the first unselected word line WLunsel1 positioned at the boundary between the second and third groups G2 and G3 among the unselected word lines WLunsel included in the third group G3 is located at the second time point t22. The third pass voltage Vpass3 may be applied. At this time, the second pass voltage Vpass2 applied at the second time point t22 is the remaining second except for the first unselected word line WLunsel1 among the unselected word lines WLunsel included in the third group G3. 2 is applied to the unselected word line WLunsel2. At the third time point t23, the first unselected word line WLunsel1 positioned at the boundary between the first and second groups G1 and G2 among the unselected word lines WLunsel included in the second group G2 is disposed at the third time point t23. The third pass voltage Vpass3 may be applied. At this time, the second pass voltage Vpass2 applied at the third time point t23 is the remaining second except for the first unselected word line WLunsel1 among the unselected word lines WLunsel included in the second group G2. 2 is applied to the unselected word line WLunsel2.
The third pass voltage Vpass3 is applied at each of the first to third time points t21, t22, and t23, or is applied at the second and third time points t22 and t23, or a third time point t23. Can be applied from The third pass voltage Vpass3 is preferably set higher than the ground voltage 0V and less than or equal to 3V to short the channel. The third pass voltage Vpass3 is a group of any one of the second to fourth groups G2, G3, and G4 other than the first group G1 when a boosting phenomenon occurs in the channel of the program inhibiting cell MCinh. Channels of the memory cells included in the device may be electrically separated. Accordingly, only the channel electrically connected to the channel of the program inhibiting cell MCinh through the first pass voltage Vpass1 and the program voltage Vpgm may be boosted, thereby increasing the channel voltage boosting efficiency of the program inhibiting cell MCinh. .
On the other hand, the lower the third pass voltage Vpass3 is applied, the higher the probability that a hot carrier injection (HCI) phenomenon occurs. Accordingly, in order to prevent the HCI phenomenon, the third pass voltage Vpass3 may be set higher than 0 V to turn off the memory cell connected to the first unselected word line WLunsel1, but to be as large as possible within the allowable range. It is preferable to be set. In order to turn off the memory cell connected to the first unselected word line WLunsel1, Vg, which is a voltage applied to the first unselected word line WLunsel1, and a memory connected to the first unselected word line WLunsel1. The difference between the cell's threshold voltage Vt must be less than the source voltage Vs or the drain voltage Vd of the memory cell connected to the first unselected word line WLunsel1 (ie, Vg-Vt < Vs and Vd).
After applying the second and third pass voltages Vpass2 and Vpass3 for a predetermined time, the channel boosting of the program inhibiting cell MCinh is completed by lowering the pass voltage applied to the unselected word line WLunsel to 0V.
In the second embodiment of the present invention, the first pass voltage Vpass1 is maintained and applied to the first group G1 while the program voltage Vpgm is maintained and applied, and the unselected words of the plurality of groups G2 to G4 are applied. After applying the first pass voltage Vpass1 to the line WLunsel, the second pass voltage Vpass2 or the third pass voltage Vpass3 is applied. Accordingly, in the second embodiment of the present invention, stress applied to the memory cells connected to the unselected word line WLunsel by the pass voltage when the program voltage Vpgm is applied can be reduced. In addition, according to the second exemplary embodiment of the present invention, even if any one of the memory cells connected to the unselected word line WLunsel is selected as a program cell, a pass disturb phenomenon may be improved.
Meanwhile, in the second exemplary embodiment of the present invention, as in the first exemplary embodiment of the present invention, the loss of the time required to complete the program can be prevented by lowering the pass voltage within a time range in which the existing pass voltage is applied. .
In addition, in the second embodiment of the present invention, the boosting efficiency may be improved by sequentially lowering the pass voltage from an unselected word line group adjacent to the drain select line among the unselected word lines between the drain select line and the selected word line. Accordingly, in the second embodiment of the present invention, the overall boosting potential of the string structure including the program inhibiting cell can be maintained.
5A to 5C and 6 are diagrams for describing an example of a method of programming a nonvolatile memory device according to a second embodiment of the present invention in more detail. 5A through 5C and 6 illustrate a case where 32 word lines including word lines WL0 to 31 word lines WL31 are formed between the source select line SSL and the drain select line DSL. An example is shown.
Referring to FIGS. 5A to 5C and FIG. 6A, when the selected word line is any one of the word lines WL0 to WL7, the word lines may be the first as described above with reference to FIG. 4. To the fourth group G1, G2, G3, and G4. In this case, the voltage applied at the first time point t21 is as shown in FIGS. 5A and 6A, and the voltage applied at the second time point t22 is shown in FIGS. 5B and 6A. The voltage applied at the third time point t23 is as shown in FIGS. 5C and 6A. 5A to 5C and FIG. 6A, voltages applied to the first to fourth groups G1, G2, G3, and G4 at the first to third time points t21, t22, and t23 are shown in FIG. As described above in 4.
Meanwhile, referring to FIG. 6B, when the selected word line is any one of the word lines WL0 to WL10, the word lines may be included in the first to third groups G1, G2, and G3. It can be divided into At this time, when the second and third pass voltages Vpass2 and Vpass3 are applied according to the principle described above with reference to FIG. 4, the time points t2a and t2b at which the second and third pass voltages Vpass2 and Vpass3 are applied are two places. to be.
In addition, referring to FIG. 6C, when the selected word line is any one of word lines WL0 to WL15, the word lines may be divided into first and second groups G1 and G2. have. In this case, when the second and third pass voltages Vpass2 and Vpass3 are applied according to the principle described above with reference to FIG. 4, the time point t2 at which the second and third pass voltages Vpass2 and Vpass3 are applied is one place.
As described above, dividing word lines into groups may vary according to positions of selected word lines. Meanwhile, the number of word lines included in one group may be variously set to 2 to 20. At this time, the smaller the number of groups, the simpler the method for applying the pass voltage to the word line, so that the pass voltage can be easily applied. As the number of groups increases, the stress applied to the memory cell by the pass voltage can be reduced more effectively, thereby reducing the overall pass disturb phenomenon. Therefore, the word lines are grouped in various ranges according to the elements of various design rules so that the optimum characteristics can be considered in consideration of the two conditions.
The above-described present invention can be applied not only when 32 word lines are formed between the source select line and the drain select line, but also without limitation on the number of word lines formed between the source select line and the drain select line such as 32 to 1000.
Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.
1 shows a correlation between a path disturb and a height of an isolation layer.
2 is a view for explaining a nonvolatile memory device according to the present invention;
3A and 3B are timing diagrams for describing a method of programming a nonvolatile memory device according to a first embodiment of the present invention.
4 is a timing diagram illustrating a program method of a nonvolatile memory device according to a second exemplary embodiment of the present invention.
5A to 5C and 6 are diagrams for describing an example of a method of programming a nonvolatile memory device according to a second embodiment of the present invention in more detail.
<Explanation of symbols for the main parts of the drawings>
210: memory cell array 220: string structure
MCpgm: Program Cell MCinh: Program Prohibited Cell
DSL: Drain Select Line SSL: Source Select Line
WL: word line WLsel: selected word line
WLunsel: Unselected Word Lines

Claims (12)

  1. A method of programming a nonvolatile memory device in which a plurality of word lines are formed between a source select line and a drain select line,
    Applying a first pass voltage to the remaining unselected word lines except for the selected one of the word lines; And
    After applying the first pass voltage during the first period, lowering the first pass voltage to the second pass voltage and applying the second pass voltage during the second period;
    And a program voltage is applied to the selected word line during the first and second periods.
  2. The method of claim 1,
    And the second pass voltage is set to 1V to 3V lower than the first pass voltage.
  3. A method of programming a nonvolatile memory device in which a plurality of word lines are formed between a source select line and a drain select line,
    Applying a first pass voltage to a plurality of groups of unselected word lines including a first group; And
    Maintaining a first pass voltage applied to the unselected word lines of the first group, and lowering and applying the first pass voltage applied to the unselected word lines of the plurality of groups to a second pass voltage; ,
    And the first and second pass voltages are applied while a program voltage is applied to a selected word line.
  4. The method of claim 3, wherein
    And the first group includes word lines disposed between the source select line and the selected word line among the plurality of word lines.
  5. The method of claim 3, wherein
    And the second pass voltage is set to 1V to 3V lower than the first pass voltage.
  6. The method of claim 3, wherein
    And applying a voltage for shorting a channel to an unselected word line adjacent to the group to which the second pass voltage is applied when the voltage is lowered to the second pass voltage.
  7. The method of claim 6,
    And a voltage for shorting the channel is greater than 0V and less than 3V.
  8. The method of claim 6,
    And a non-selected word line to which the voltage for shorting the channel is applied is adjacent to the outermost word line toward the source select line of the group to which the second pass voltage is applied.
  9. The method of claim 3, wherein
    The step of applying the lowered voltage to the second pass voltage
    And programming a group adjacent to the drain select line among the plurality of groups to a group adjacent to the source select line.
  10. The method of claim 3, wherein
    And lowering the first pass voltage to a third pass voltage lower than the second pass voltage to an unselected word line except for the group to which the second pass voltage is applied. Program method.
  11. The method of claim 10,
    And the third pass voltage is applied to an unselected word line of a group to which the third pass voltage is applied when the second pass voltage is applied.
  12. The method of claim 3, wherein
    When a second pass voltage lower than the first pass voltage is applied to the plurality of unselected word lines, a low pass voltage is sequentially applied from a group adjacent to the drain select line to a group adjacent to the source select line. Program method of volatile memory device.
KR1020090059739A 2009-07-01 2009-07-01 Method of program operating for nonvolatile memory device KR20110002243A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140113014A (en) * 2013-03-15 2014-09-24 삼성전자주식회사 Non-Volatile Memory Device and Method of Program thereof
US9053796B2 (en) 2013-10-24 2015-06-09 SK Hynix Inc. Semiconductor device and methods of manufacturing and operating the same
US9966144B2 (en) 2016-06-30 2018-05-08 SK Hynix Inc. Method of programming semiconductor memory device
US10269570B2 (en) 2017-01-05 2019-04-23 SK Hynix Inc. Memory device and method relating to different pass voltages for unselected pages

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140113014A (en) * 2013-03-15 2014-09-24 삼성전자주식회사 Non-Volatile Memory Device and Method of Program thereof
US9053796B2 (en) 2013-10-24 2015-06-09 SK Hynix Inc. Semiconductor device and methods of manufacturing and operating the same
US9966144B2 (en) 2016-06-30 2018-05-08 SK Hynix Inc. Method of programming semiconductor memory device
US10290355B2 (en) 2016-06-30 2019-05-14 SK Hynix Inc. Method of programming semiconductor memory device
US10269570B2 (en) 2017-01-05 2019-04-23 SK Hynix Inc. Memory device and method relating to different pass voltages for unselected pages
US10937655B2 (en) 2017-01-05 2021-03-02 SK Hynix Inc. Memory device with various pass voltages

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