KR20100078808A - Resistive memory device - Google Patents

Resistive memory device Download PDF

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Publication number
KR20100078808A
KR20100078808A KR1020080137169A KR20080137169A KR20100078808A KR 20100078808 A KR20100078808 A KR 20100078808A KR 1020080137169 A KR1020080137169 A KR 1020080137169A KR 20080137169 A KR20080137169 A KR 20080137169A KR 20100078808 A KR20100078808 A KR 20100078808A
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KR
South Korea
Prior art keywords
electrode
method
layer
memory device
resistive memory
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KR1020080137169A
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Korean (ko)
Inventor
강보수
김기환
김창정
안승언
이명재
이창범
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삼성전자주식회사
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Priority to KR1020080137169A priority Critical patent/KR20100078808A/en
Publication of KR20100078808A publication Critical patent/KR20100078808A/en

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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/24Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, e.g. resistance switching non-volatile memory structures
    • H01L27/2409Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, e.g. resistance switching non-volatile memory structures comprising two-terminal selection components, e.g. diodes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/12Details
    • H01L45/122Device geometry
    • H01L45/1233Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/14Selection of switching materials
    • H01L45/145Oxides or nitrides
    • H01L45/146Binary metal oxides, e.g. TaOx

Abstract

A resistive memory element is disclosed. The resistive memory device disclosed has an intermediate electrode including a barrier layer between the resistance change layer and the switching device. The barrier layer may be formed of a material that prevents material diffusion between the resistance change layer and the switching device.

Description

Resistive Memory Device

The present disclosure relates to a resistive memory device.

A resistive memory device is a nonvolatile memory device using a resistance change characteristic of a material, for example, a transition metal oxide, in which a resistance varies greatly at a specific voltage. That is, when a voltage above a set voltage is applied to the resistance change material, the resistance of the resistance change material is lowered. This is called an ON state. When a voltage equal to or greater than a reset voltage is applied to the resistance change material, the resistance of the resistance change material is increased. This is called an OFF state. Among the resistive memory devices, a multi-layer cross point memory device has an advantage of high integration.

In general, a resistive memory device includes a storage node including a resistance change layer and a switching device electrically connected to the storage node. The switching element serves to control signal access to the storage node connected thereto. However, in the conventional resistive memory device, the switching device may be damaged during the programming operation. This may reduce the reliability of the device, it may be difficult to improve the integration.

An aspect of the present invention provides a resistive memory device using a resistive change layer as an information storage element.

One embodiment of the invention the at least one first electrode; At least one second electrode spaced apart from the first electrode; And a first stacked structure provided between the first and second electrodes, wherein the first stacked structure includes a first resistance changing layer, a first switching element, and a barrier layer interposed therebetween. Provided is a resistive memory device including a middle electrode.

The barrier layer may include at least one of a conductive metal nitride and a conductive metal oxide.

The barrier layer may include one of Ti nitride, Ta nitride, Ru oxide, Ti oxide, Al oxide, and a mixture thereof.

The first intermediate electrode may further include a metal layer between at least one of the barrier layer and the first resistance change layer and between the barrier layer and the first switching device.

The first switching device may be one of a diode, a threshold switching device, and a varistor.

The first switching device may be an oxide diode.

The first resistance change layer, the first intermediate electrode, the first switching element, and the second electrode may be sequentially provided on the first electrode.

The first switching element, the first intermediate electrode, the first resistance change layer, and the second electrode may be sequentially provided on the first electrode.

The plurality of first electrodes may have a wiring form and be arranged in parallel with each other, and the plurality of second electrodes may have a wiring form and be arranged in parallel with each other so as to intersect the first electrodes. The first stacked structure may be provided at an intersection point of a second electrode.

The resistive memory device of the present embodiment may include at least one third electrode spaced apart from the second electrode; And a second stacked structure provided between the second electrode and the third electrode, wherein the second stacked structure is interposed between the second resistance change layer, the second switching element, and the barriers. It may include a second intermediate electrode having a layer.

The barrier layer of the second intermediate electrode may be the same as the barrier layer of the first intermediate electrode.

The configuration of the second intermediate electrode may be the same as that of the first intermediate electrode.

The second switching device may be one of a diode, a threshold switching device, and a varistor.

The second switching device may be an oxide diode.

When the first and second switching elements are diodes, the rectifying directions of the first and second switching elements may be the same or opposite to each other.

The second resistance change layer, the second intermediate electrode, the second switching element, and the third electrode may be sequentially provided on the second electrode.

The second switching element, the second intermediate electrode, the second resistance change layer, and the third electrode may be sequentially provided on the second electrode.

The plurality of second electrodes may have a wiring form and be arranged in parallel with each other, and the plurality of third electrodes may have a wiring form and be arranged in parallel with each other so as to intersect the second electrodes. And the second stacked structure at an intersection point of the third electrode.

The resistive memory device may be a multilayer cross-point memory device having a 1S (switch) -1R (resistor) cell structure.

In the resistive memory device according to the embodiment of the present invention, deterioration of characteristics of the switching device during the programming operation may be prevented or suppressed. Therefore, an error can be prevented in reproducing information, and the reliability of the device can be improved. In addition, the structure of the resistive memory device according to the embodiment of the present invention may be advantageous for improving the degree of integration.

Hereinafter, a resistive memory device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. In this process, the thicknesses of the layers or regions illustrated in the drawings are somewhat exaggerated for clarity. Like numbers refer to like elements throughout.

1 shows a resistive memory device according to an embodiment of the present invention.

Referring to FIG. 1, the first electrode E1 is provided on the substrate SUB1. The substrate SUB1 may be any one of various substrates including a glass substrate, a hard plastic substrate, a flexible plastic substrate, a silicon substrate, and the like. The first electrode E1 may have a wiring shape extending in a predetermined direction, for example, the X-axis direction. A second electrode E2 spaced apart from the first electrode E1 may be provided above the first electrode E1. The second electrode E2 may have a wiring form crossing the first electrode E1. For example, the second electrode E2 may extend in the Y-axis direction to vertically cross the first electrode E1. However, the extending directions of the first and second electrodes E1 and E2 may be changed, and the shapes of the first and second electrodes E1 and E2 may be variously modified. Meanwhile, the first and second electrodes E1 and E2 may be formed of a general electrode material used in the semiconductor device field, and may be formed in a single layer or a multilayer structure. For example, the first and second electrodes E1 and E2 may include one of Pt, Au, Pd, Ir, Ag, Ni, Al, Mo, Cu, and a mixture thereof. The materials and structures of the first and second electrodes E1 and E2 may be the same or different.

The stacked structure S1 may be provided between the first and second electrodes E1 and E2. When the first and second electrodes E1 and E2 have an interconnection shape, the stacked structure S1 may be provided at the intersection of the first and second electrodes E1 and E2. The stacked structure S1 may include a resistance change layer R1, a switching device D1, and an intermediate electrode M1 between the R1 and D1.

The resistance change layer R1 may be formed of a material having a variable resistance characteristic, for example, a transition metal oxide (TMO). More specifically, the resistance change layer (R1) is Ni oxide, Cu oxide, Ti oxide, Co oxide, Hf oxide, Zr oxide, Zn oxide, W oxide, Nb oxide, TiNi oxide, LiNi oxide, Al oxide, InZn oxide , V oxide, SrZr oxide, SrTi oxide, Cr oxide, Fe oxide, Ta oxide, and a mixture thereof. The switching device D1 may be formed of a diode, a threshold switching device, a varistor, or the like. When the switching element D1 is formed in a diode structure, the diode is a pn diode, a back-to-back pn diode, a schottky diode, a back-to-back It may be a Schottky diode, a tunnel diode, a varactor diode, or a zener diode. When the switching device D1 has a pn diode structure, the switching device D1 may have a bilayer structure of a p-type semiconductor layer and an n-type semiconductor layer. The p-type semiconductor layer and the n-type semiconductor layer may be oxide layers. For example, the switching element D1 has a structure in which a p-type oxide layer such as a CuO layer and an n-type oxide layer such as an InZnO layer are sequentially stacked, or a p-type oxide layer such as NiO and an n-type oxide layer such as TiO 2 are sequentially It may be a stacked structure. In the case of the CuO layer, due to the naturally occurring Cu deficiency, O 2 that is not bonded with Cu may act as a donor to form a p-type semiconductor layer. For the InZnO layer, and naturally acts as a Zn gap (interstitial) and O public (vacancy), have not combined with the presence in addition to the grid, or O Zn 2 + is an acceptor (acceptor) by the generated may be n-type semiconductor . Although the switching device D1 may be manufactured using amorphous oxide layers that are easily formed at room temperature, the switching device D1 may also be manufactured using an oxide layer of a crystalline phase. In the case of a silicon diode, since it must be formed in a high temperature process of about 800 ° C., there is a limitation in selecting a substrate, and various problems may occur due to the high temperature process. Therefore, when configuring the switching device (D1) with an oxide layer easily formed at room temperature, various advantages can be provided. However, the present invention does not exclude silicon as a material of the switching device D1. In some cases, the switching element D1 may be made of silicon or various other materials.

The intermediate electrode M1 electrically connects the resistance change layer R1 and the switching element D1. Without the intermediate electrode M1, the switching element D1 acts like a resistor, which may cause a problem in device operation. have. The intermediate electrode M1 may include a barrier layer b1. In addition, the intermediate electrode M1 may further include a lower metal layer a1 between the barrier layer b1 and the resistance change layer R1, and an upper metal layer c1 between the barrier layer b1 and the switching device D1. have. The lower and upper metal layers a1 and c1 may have higher electrical conductivity than the barrier layer b1. In some cases, at least one of the lower and upper metal layers a1 and c1 may not be provided. The barrier layer b1 may prevent material diffusion (or penetration) between the resistance change layer R1 and the switching device D1 to prevent deterioration of characteristics of the switching device D1. More specifically, when programming the resistance change layer R1 by applying a predetermined voltage between the first and second electrodes E1 and E2, if there is no barrier layer b1, the resistance change layer R1 A predetermined material, for example, oxygen ions, can be easily diffused (or penetrated) from the switching element D1 to the deterioration characteristics of the switching element D1. Such deterioration of the switching element D1 can be prevented or suppressed by the barrier layer b1. The barrier layer b1 may include at least one of a conductive metal nitride and a conductive metal oxide. For example, the barrier layer b1 may include one of Ti nitride, Ta nitride, Ru oxide, Ti oxide, Al oxide, and a mixture thereof. The barrier layer b1 formed of such a material can effectively block oxygen ions and the like, and has a relatively high electrical conductivity. The barrier layer b1 may be formed to a thickness of about 10 nm or less, but may also be formed to a thickness of 10 nm or more. The lower and upper metal layers a1 and c1 may be formed of the same material as the first and second electrodes E1 and E2, for example, Pt, Au, Pd, Ir, Ag, Ni, Al, Mo, Cu, and mixtures thereof. It may include one of the. However, in some cases, materials of the lower and upper metal layers a1 and c1 and materials of the first and second electrodes E1 and E2 may be different.

Although not shown in FIG. 1, an interlayer insulating layer covering the first electrode E1 may be provided on the substrate SUB1 around the stacked structure S1. The interlayer insulating layer may have a height similar to that of the stacked structure S1, and the second electrode E2 may be provided on the interlayer insulating layer and the stacked structure S1.

The structure of FIG. 1 can be variously modified. For example, the structure of the intermediate electrode M1 of FIG. 1 may vary. Examples are shown in FIGS. 2 and 3.

The intermediate electrode M1 ′ of FIG. 2 has a structure in which the lower metal layer a1 is removed from the intermediate electrode M1 of FIG. 1, and the intermediate electrode M1 ″ of FIG. 3 has an upper portion in the intermediate electrode M1 of FIG. 1. The barrier layer b1 is positioned in the middle of the intermediate electrode M1 as shown in FIG. 1, or the intermediate electrodes M1 'and M1 "as shown in FIGS. 2 and 3. It may be located at the end of the). Although not illustrated here, the intermediate electrodes M1, M1 ′, and M1 ″ may include a plurality of barrier layers b1 spaced apart from each other.

In addition, in FIGS. 1 to 3, the positions of the resistance change layer R1 and the switching element D1 may be interchanged, and the positions of the p-type semiconductor layer and the n-type semiconductor layer of the switching element D1 may also be interchanged. have. In addition, a contact electrode layer may be further provided between the switching device D1 and the second electrode 200.

4 shows the voltage (V)-current (A) characteristics of the resistive memory device according to the comparative example. The resistive memory device according to the comparative example has a structure without the barrier layer b1 in FIG. 2. That is, the resistive memory device according to the comparative example has an intermediate electrode made of a single metal layer. In this comparative example, a Ni oxide layer was used as a resistance change layer, a Pt layer was used as an intermediate electrode, a diode in which a CuO layer and an InZnO layer were stacked as a switching element, and a Pt electrode as the first and second electrodes. Was used.

In FIG. 4, the first and second graphs G1 and G2 positioned on the positive voltage side show characteristics of the resistance change layer in the OFF and ON states, respectively. On the other hand, the third and fourth graphs G3 and G4 on the negative voltage side show reverse characteristics of the diode before and after programming the resistance change layer, respectively.

Referring to FIG. 4, the fourth graph G4 is located at a considerably higher position than the third graph G3. This means that after programming the resistance change layer, the reverse leakage current of the switching element (diode) is greatly increased. This is because the rectification characteristics of the switching element (diode) is deteriorated. If the rectification characteristic of the switching element (diode) is deteriorated in this manner, the sensing margin becomes small during the information reproducing (reading) operation of the resistive memory device, and the possibility of the reproducing (reading) current flowing in an undesired direction increases. . Therefore, a reproduction error may occur and the reliability of the device may be degraded. In addition, since the sensing margin is small, it is difficult to have a large number of memory cells in one electrode line. This is because the longer the electrode line, the greater the electric resistance of itself, and thus the more difficult the sensing. Therefore, when the resistive memory device according to the comparative example is to be manufactured in an array structure, the degree of integration may not be easily improved.

FIG. 5 shows the voltage (V) -current (A) characteristics of the resistive memory device having the structure of FIG. 1. In this case, a Ni oxide layer was used as the resistance change layer R1, and a Pt layer / TiN layer / Pt layer (here, the TiN layer is a barrier layer b1) was used as the intermediate electrode M1. As the device D1, a diode in which a CuO layer and an InZnO layer were stacked was used, and Pt electrodes were used as the first and second electrodes E1 and E2. In other words, the configuration except for using the barrier layer (b1) is the same as the comparative example used to obtain the result of FIG.

In FIG. 5, the first and second graphs G1 ′ and G2 ′ positioned on the positive voltage side show characteristics of the resistance change layer R1 in the OFF and ON states, respectively. The third and fourth graphs G3 'and G4' on the negative voltage side show reverse characteristics of the switching element (diode) D1 before and after programming the resistance change layer R1, respectively.

Referring to FIG. 5, it can be seen that the positions of the third and fourth graphs G3 ′ and G4 ′ are almost identical to each other. From this, it can be seen that when the barrier layer b1 is used, deterioration of characteristics of the switching element D1 can be prevented. That is, even after programming the resistance change layer R1, the reverse leakage current of the switching element D1 does not increase and is maintained at a low level. Therefore, the resistive memory device according to the embodiment of the present invention may have a relatively large sensing margin. Further, in the resistive memory device according to the embodiment of the present invention, it is possible to suppress or prevent the reproduction (read) current from flowing in an unwanted direction. Therefore, the occurrence of reproduction error can be suppressed and the reliability of the device can be improved. In addition, since a large number of memory cells may be provided in one electrode line, easy sensing may be possible, and thus it may be advantageous to improve the degree of integration of the device. According to the exemplary embodiment of the present invention, since the centers of the resistance change layer R1, the intermediate electrode M1, and the switching element D1 may exist on the same vertical line, the unit cell has a minimum cell size of 4F 2 ( F: feature size).

1 to 3 may be a unit cell structure of a resistive memory device according to an exemplary embodiment of the present invention. The resistive memory device according to the exemplary embodiment of the present invention may have an array structure including the structure of FIGS. 1 to 3 as a unit cell structure. Examples are shown in FIGS. 6 and 8. 6 and 8 may be a multilayer cross-point resistive memory device having a 1S (switch) -1R (resistor) cell structure, for example, a 1D (diode) -1R (resistor) cell structure.

6 shows a resistive memory device having an array structure according to an embodiment of the present invention.

Referring to FIG. 6, a plurality of first electrodes E1 formed in parallel with each other in a first direction and a plurality of second electrodes E2 formed in a direction crossing the first electrodes E1 may be provided. The first stacked structure S1 may be provided at the intersection of the electrode E1 and the second electrode E2. The first stacked structure S1 may include a first resistance change layer R1, a first intermediate electrode M1, and a first switching element D1 that are sequentially stacked on the first electrode E1. Positions of the first resistance change layer R1 and the first switching element D1 may be changed. The first electrode E1, the first resistance change layer R1, the first intermediate electrode M1, the first switching element D1, and the second electrode E2 are the first electrode E1 of FIG. 1, respectively. It corresponds to the resistance change layer R1, the intermediate electrode M1, the switching element D1, and the second electrode E2.

The third electrodes E3 may be further spaced apart from the upper surface of the second electrode E2 by a predetermined interval. The third electrode E3 may have a wiring shape and may be formed at equal intervals, and may cross the second electrode E2. The material of the third electrode E3 may be the same as the first and second electrodes E1 and E2. The second stacked structure S2 may be provided at the intersection of the second electrode E2 and the third electrode E3. The second stacked structure S2 and the first stacked structure S1 may have the same stacked structure or a vertically symmetrical structure in a circuit. The latter case is shown in FIG. 6. That is, if the first stacked structure S1 includes a structure in which the first intermediate electrode M1 and the first switching device D1 are sequentially stacked on the first resistance change layer R1, the second stacked structure ( S2) may have a structure in which the second intermediate electrode M2 and the second resistance change layer R2 are sequentially stacked on the second switching element D2. The second intermediate electrode M2 may include a barrier layer b2, and may further include a lower metal layer a2 and an upper metal layer c2 on a lower surface and an upper surface of the barrier layer b2. The lower metal layer a2, the barrier layer b2 and the upper metal layer c2 of the second intermediate electrode M2 are respectively the lower metal layer a1, the barrier layer b1 and the upper metal layer (1) of the first intermediate electrode M1. similar to c1). The second resistance change layer R2 may be the same material layer as the first resistance change layer R1, and the second switching element D2 may have various configurations similar to the first switching element D1. When the first and second switching elements D2 are diodes, the second switching elements D2 may have a vertically symmetrical structure or the same stacked structure as the first switching element D1. That is, the first stacked structure S1, the second electrode E2, and the second stacked structure S2 may have a structure as illustrated in FIG. 7A or 7B. In FIG. 7A, the rectifying directions of the first and second switching devices D1 and D2 are opposite to each other. In FIG. 7B, the rectifying directions of the first and second switching devices D1 and D2 are the same. 7A and 7B, rectifying directions of the first and second switching devices D1 and D2 may vary. In addition, in the first stacked structure S1 of FIGS. 7A and 7B, the positions of the first resistance changing layer R1 and the first switching device D1 may be interchanged, and the second resistor in the second stacked structure S2 may be changed. The positions of the change layer R2 and the second switching device D2 may also be changed.

In addition, in the structure of FIG. 7A, since the first and second switching elements D1 and D2 are vertically symmetrical with respect to the second electrode E2, the second electrode E2 is used as a common bit line. Thus, information can be recorded simultaneously in the first and second resistance change layers R1 and R2. On the other hand, in the structure of FIG. 7B, since the rectifying directions of the first and second switching elements D1 and D2 are the same, information is provided to either one of the first and second resistance change layers R1 and R2 in one programming operation. Can record

Although not shown, the resistive memory device of FIG. 6 may further include a stacked structure having the same structure as the stacked structure of the first stacked structure S1 and the second electrode E2 on the third electrode E3. Can be.

Alternatively, in the resistive memory device according to the embodiment of the present invention, the first stacked structure S1, the second electrode E2, the second stacked structure S2, and the third electrode E3 may be disposed on the third electrode E3. At least one set or more of the laminated structure having the same structure as the laminated structure of may be further included.

Alternatively, in the resistive memory device according to the exemplary embodiment of the present invention, the first stacked structure S1, the second electrode E2, the second stacked structure S2, and the third electrode E3 may be disposed on the third electrode E3. The first stacked structure S1 and the second electrode E2 may further include at least one or more sets of stacked structures having the same structure as the stacked structure in which the first stacked structure S1 and the second electrode E2 are sequentially stacked.

In FIG. 6, the first and second stacked structures S1 and S2 are illustrated in a circular columnar shape, but they may have various deformation shapes such as square pillars or wider widths downward. For example, the first and second stacked structures S1 and S2 are asymmetrically extended outside the intersection of the first and second electrodes E1 and E2 and the intersection of the second and third electrodes E2 and E3. It may have a shape. An example of the first laminated structure S1 ′ having the asymmetrical shape is shown in FIG. 8.

8 is a plan view of a resistive memory device according to another exemplary embodiment of the present invention.

Referring to FIG. 8, the first stacked structure S1 ′ contacts the first portion p1 and the first portion p1 provided at the intersection of the first and second electrodes E1 and E2 and is outside the intersection. It may include a second portion (p2) extended to. That is, the first stacked structure S1 ′ has an asymmetrical shape that extends outside the intersection of the first and second electrodes E1 and E2. The first stacked structure S1 ′ may have a stacked structure similar to the first stacked structure S1 of FIG. 6, wherein the shape of the first switching element and the first resistance change layer of the first stacked structure S1 ′ may be defined. The shapes may be different from each other. For example, the first switching element may be formed to have an area corresponding to the first portion p1 and the second portion p2, and the first resistance change layer may be formed to have an area corresponding to the first portion p1. Can be. However, the first resistance change layer may be provided on the entire lower surface of the first intermediate electrode. In this case, only the first resistance change layer region existing at the intersection of the first electrode E1 and the first intermediate electrode may be an effective resistance change region, and the remaining region deviating from the intersection point may be an effective region. Can be. A contact electrode layer covering the entire top surface of the first switching device may be further provided between the first switching device and the second electrode E2. As shown in FIG. 8, when the first switching device is large, its forward current may be increased and switching characteristics may be improved. The second stacked structure S2 of FIG. 6 may also be modified to have a planar structure similar to the first stacked structure S1 ′ of FIG. 8.

9 is a cross-sectional view illustrating a resistive memory device according to still another embodiment of the present invention.

Referring to FIG. 9, a first electrode E10 is provided on the substrate SUB10 and a first hole H1 exposing a portion of the upper surface of the first electrode E10 on the first electrode E10. The first insulating layer 100 may be provided. The first hole H1 may be formed by an oblique etching process, and thus, the width of the first hole H1 may be narrower as the first electrode H10 is closer to the first electrode E10. The width of the first hole H1 does not change depending on the height and may be constant. The first stacked structure S10 may be provided on the first electrode E10 exposed by the first hole H1. The first stacked structure S10 may include a first resistance change layer R10, a first intermediate electrode M10, and a first switching element D10 sequentially stacked. The layers constituting the first stacked structure S10 may have a curved shape along the shape of the first hole H1. The first intermediate electrode M10 may include a lower metal layer a10, a barrier layer b10, and an upper metal layer b10. A first interlayer insulating layer 150 having a similar height may be provided around the first stacked structure S10. The second electrode E20 in contact with the first switching device D10 may be provided on the first stacked structure S10. The first electrode E10 and the second electrode E20 are in the form of wires, and may be provided to cross each other, preferably perpendicular to each other. Materials and configurations of the first electrode E10, the second electrode E20, the first resistance change layer R10, the first intermediate electrode M10, and the first switching element D10 are shown in FIG. It may be the same as the material and configuration of the E1, the second electrode E2, the first resistance change layer R1, the first intermediate electrode M1, and the first switching element D1.

The second switching device D20 and the second intermediate electrode M20 may be sequentially provided on the second electrode E20. The second intermediate electrode M20 may include a lower metal layer a20, a barrier layer b20, and an upper metal layer b20. A second hole H2 exposing the top surface of the second intermediate electrode M20 while covering the second switching element D20 and the second intermediate electrode M20 on the first interlayer insulating layer 150. The second insulating layer 200 may be provided. The second hole H2 may have a shape similar to the first hole H1. A second interlayer insulating layer 250 having a similar height may be provided around the second insulating layer 200, and contacts the second intermediate electrode M20 exposed by the second hole H2. The second resistance change layer R20 may be provided. The second switching element D20, the second intermediate electrode M20, and the second resistance change layer R20 sequentially provided on the second electrode E20 may constitute the second stacked structure S20. The third electrode E30 in contact with the second resistance change layer R20 may be provided on the second interlayer insulating layer 250. The third electrode E30 has a wiring form and may cross the second electrode E20. Materials and configurations of the second switching element D20, the second intermediate electrode M20, the second resistance change layer R20, and the third electrode E30 are respectively represented by the second switching element D2 and the second switching element D2 of FIG. The material and structure of the intermediate electrode M2, the second resistance change layer R2, and the third electrode E3 may be the same.

In FIG. 9, the first and second stacked structures S10 and S20 have a columnar structure similar to the first and second stacked structures S1 and S2 of FIG. 6, or the first stacked structure S1 of FIG. 8. It may have an asymmetric structure similar to '). In addition, a memory array having part or all of FIG. 9 in a unit cell structure may be configured.

6 and 9, the intermediate electrodes M1, M2, M10, and M20 may be modified to have a structure of the intermediate electrode M1 ′ of FIG. 2 or the intermediate electrode M1 ″ of FIG. 3.

In addition, the resistive memory device according to the exemplary embodiments described above may be used as a rewritable memory or an OTP (one-time programmable) memory. In more detail, when the resistance change layers R1, R2, R10, and R20 include a first element that is reversibly converted from a high resistance state to a low resistance state or from a low resistance state to a high resistance state. The resistive memory device according to the embodiment of the present invention may be a rewritable memory. Examples of the first element include a material layer having a variable resistance characteristic, a filament fuse, and the like. On the other hand, when the resistance change layers R1, R2, R10, and R20 include a second element that is irreversibly converted from a high resistance state to a low resistance state, the memory cell once programmed can be returned to its original state. Since there is no resistance, the resistive memory device according to the embodiment of the present invention may be an OTP (one-time programmable) memory. An example of the second element is an antifuse, and the antifuse may be formed of a dielectric material such as silicon oxide or silicon nitride.

While many details are set forth in the foregoing description, they should be construed as illustrative of embodiments rather than to limit the scope of the invention. For example, one of ordinary skill in the art to which the present invention pertains will be able to more diversify the components of the resistive memory device in the embodiments of the present invention, and may variously modify the structure. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be determined by the technical spirit described in the claims.

1 to 3 are cross-sectional views illustrating a resistive memory device according to example embodiments.

4 is a graph showing voltage (V)-current (A) characteristics of a resistive memory device according to a comparative example compared with the present invention.

5 is a graph showing voltage (V) -current (A) characteristics of the resistive memory device according to an exemplary embodiment of the present invention.

6 is a perspective view illustrating a resistive memory device having an array structure according to an exemplary embodiment of the present invention.

7A and 7B are circuit diagrams of a resistive memory device according to example embodiments.

8 is a plan view of a resistive memory device according to another exemplary embodiment of the present invention.

9 is a cross-sectional view of a resistive memory device according to another exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

a1, a2, a10, a20: lower metal layer b1, b2, b10, b20: barrier layer

c1, c2, c10, c20: upper metal layer D1, D2, D10, D20: switching element

E1 to E3, E10 to E30: electrodes H1, H2: holes

M1, M2, M10, M20: intermediate electrode R1, R2, R10, R20: resistance change layer

S1, S2, S10, S20: laminated structure SUB1, SUB10: substrate

100, 150, 200, 250: insulation layer

Claims (19)

  1. At least one first electrode;
    At least one second electrode spaced apart from the first electrode; And
    And a first stacked structure provided between the first and second electrodes.
    The first stacked structure includes a first resistive change layer, a first switching element and a first intermediate electrode interposed therebetween and having a barrier layer.
  2. The method of claim 1,
    The barrier layer includes at least one of a conductive metal nitride and a conductive metal oxide.
  3. The method of claim 2,
    The barrier layer may include one of Ti nitride, Ta nitride, Ru oxide, Ti oxide, Al oxide, and a mixture thereof.
  4. The method of claim 1,
    The first intermediate electrode may further include a metal layer provided between at least one of the barrier layer and the first resistance change layer and between the barrier layer and the first switching device.
  5. The method of claim 1,
    The first switching device is one of a diode, a threshold switching device and a varistor.
  6. The method of claim 5,
    The first switching device is an oxide memory device.
  7. The method of claim 1,
    The resistive memory device including the first resistance change layer, the first intermediate electrode, the first switching device, and the second electrode in order on the first electrode.
  8. The method of claim 1,
    And a first switching element, the first intermediate electrode, the first resistance change layer, and the second electrode on the first electrode.
  9. The method of claim 1,
    A plurality of the first electrode has a wiring form and arranged in parallel with each other,
    A plurality of the second electrodes are arranged in parallel with each other in a wiring form so as to intersect the first electrodes,
    The resistive memory device having the first stacked structure at an intersection point of the first and second electrodes.
  10. The method according to claim 1 or 9,
    At least one third electrode spaced apart from the second electrode; And
    And a second stacked structure provided between the second electrode and the third electrode.
    The second stacked structure includes a second resistive change layer, a second switching element and a second intermediate electrode interposed therebetween having a barrier layer.
  11. The method of claim 10,
    The barrier layer of the second intermediate electrode is the same as the barrier layer of the first intermediate electrode.
  12. The method of claim 10,
    The resistive memory device having the same structure as that of the first intermediate electrode.
  13. The method of claim 10,
    The second switching device is one of a diode, a threshold switching device and a varistor.
  14. The method of claim 13,
    The second switching device is an oxide memory device.
  15. The method of claim 10,
    The first and second switching device is a diode,
    Resistive memory devices of the first and second switching devices are the same or opposite to each other.
  16. The method of claim 10,
    And a second resistance change layer, the second intermediate electrode, the second switching element, and the third electrode on the second electrode.
  17. The method of claim 10,
    And a second switching element, the second intermediate electrode, the second resistance change layer, and the third electrode on the second electrode.
  18. The method of claim 10,
    A plurality of the second electrode has a wiring form and arranged in parallel with each other,
    A plurality of the third electrodes are arranged in parallel with each other in a wiring form so as to intersect the second electrodes,
    The resistive memory device having the second stacked structure at the intersection of the second and third electrodes.
  19. The method of claim 18,
    The resistive memory device is a resistive memory device that is a multilayer cross-point memory device having a 1S (switch) -1R (resistor) cell structure.
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