KR20100071447A

KR20100071447A - Method for manufacturing of image sensor

Info

Publication number: KR20100071447A
Application number: KR1020080130164A
Authority: KR
Inventors: 정충경
Original assignee: 주식회사 동부하이텍
Priority date: 2008-12-19
Filing date: 2008-12-19
Publication date: 2010-06-29

Abstract

A method of manufacturing an image sensor according to an embodiment includes forming an interlayer insulating layer including wiring on a semiconductor substrate; Forming an image sensing unit on which the first doped layer and the second doped layer are stacked on the interlayer insulating layer; Forming a via hole through the image sensing unit and the interlayer insulating layer to expose the wiring; Performing a first cleaning process and a second cleaning process on the semiconductor substrate on which the via holes are formed; And forming a first barrier pattern, a second barrier pattern, and a contact plug in the via hole.

Description

Method for Manufacturing of Image Sensor

Embodiments relate to a method of manufacturing an image sensor.

An image sensor is a semiconductor device that converts an optical image into an electrical signal, and is classified into a charge coupled device (CCD) image sensor and a CMOS image sensor (CIS). .

The CMOS image sensor is a structure in which a photo diode area for receiving a light signal and converting it into an electric signal and a transistor area for processing the electric signal are horizontally disposed.

Such a horizontal image sensor is limited in that the photodiode region and the transistor region are horizontally disposed on the semiconductor substrate to extend the light sensing portion (commonly referred to as "Fill Factor") under a limited area.

As an alternative to overcome this problem, the circuitry is formed on a silicon substrate by depositing a photodiode with amorphous silicon or by using wafer-to-wafer bonding. Attempts have been made to form photodiodes on the lead-out circuit (hereinafter referred to as "three-dimensional image sensor"). The photodiode and the circuit area are connected through a metal line.

In this case, the photodiodes may be separated by unit pixels, and in the etching process of separating the photodiodes by unit pixels, the profile of the via hole surface formed in the photodiode is not uniform, which serves as a defect source of the image sensor. .

The embodiment provides a method of manufacturing an image sensor capable of minimizing the generation of dark current by preventing damage to the image sensing unit.

In addition, the embodiment is to provide a method of manufacturing an image sensor in which charge sharing may not occur while increasing the fill factor.

In addition, the embodiment of the present invention manufactures an image sensor capable of minimizing dark current sources and preventing saturation and degradation of sensitivity by creating a smooth movement path of photo charge between the photodiode and the lead-out circuit. To provide a method.

In the method of manufacturing the image sensor according to the embodiment, by uniformizing the profile of the sidewall of the via hole, the damage of the image sensing unit can be minimized to minimize the generation of dark current.

In addition, according to the embodiment, the device may be designed such that there is a potential difference between the source and the drain across the transfer transistor Tx, thereby enabling full dumping of the photo charge.

In addition, according to the embodiment, the charge connection region is formed between the photodiode and the lead-out circuit to create a smooth movement path of the photo charge, thereby minimizing the dark current source, and reducing saturation and sensitivity. You can prevent it.

A method of manufacturing an image sensor according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where described as being formed "on / over" of each layer, the on / over may be directly or through another layer ( indirectly) includes everything formed.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size.

The embodiment is not limited to the CMOS image sensor, and may be applied to all image sensors requiring a photodiode such as a CCD image sensor.

Hereinafter, a method of manufacturing an image sensor according to an embodiment will be described with reference to FIGS. 1 to 9.

Referring to FIG. 1, a wiring 150 and an interlayer insulating layer 160 are formed on a semiconductor substrate 100 including a readout circuit 120.

The semiconductor substrate 100 may be a single crystal or polycrystalline silicon substrate, and may be a substrate doped with p-type impurities or n-type impurities. An isolation region 110 is formed on the semiconductor substrate 100 to define an active region, and a readout circuit 120 including a transistor is formed in the active region. For example, the readout circuit 120 may include a transfer transistor (Tx) 121, a reset transistor (Rx) 123, a drive transistor (Dx) 125, and a select transistor (Sx) 127. can do. Thereafter, an ion implantation region 130 including a floating diffusion region (FD) 131 and source / drain regions 133, 135, and 137 for each transistor may be formed. Meanwhile, the readout circuit 120 may be applied to a 3Tr or 5Tr structure.

The forming of the lead-out circuit 120 on the semiconductor substrate 100 may include forming an electrical junction region 140 on the semiconductor substrate 100 and the wiring 150 on the electrical junction region 140. The method may include forming a first conductivity type connection region 147 connected to the first conductive connection region 147.

For example, the electrical junction region 140 may be a PN junction 140, but is not limited thereto. For example, the electrical junction region 140 may include a first conductive ion implantation layer 143 and a first conductive ion implantation layer (143) formed on the second conductive well 141 or the second conductive epitaxial layer. 143 may include a second conductivity type ion implantation layer 145. For example, the PN junction 140 may be a P0 145 / N- 143 / P-141 junction as shown in FIG. 1, but is not limited thereto. In addition, the semiconductor substrate 100 may be conductive in a second conductivity type, but is not limited thereto.

According to the embodiment, the device can be designed such that there is a voltage difference between the source / drain across the transfer transistor Tx, thereby enabling full dumping of the photo charge. Accordingly, as the photo charge generated in the photodiode is dumped into the floating diffusion region, the output image sensitivity may be increased.

That is, by forming an electrical junction region 140 in the semiconductor substrate 100 on which the readout circuit 120 is formed, there is a voltage difference between the source / drain across the transfer transistor (Tx) 121 so as to completely dump the photocharge. This can be made possible.

Hereinafter, the dumping structure of the photocharge of the embodiment will be described in detail with reference to FIGS. 1 and 2.

Unlike the floating diffusion (FD) 131 node, which is an N + function in the embodiment, the P / N / P section 140, which is an electrical junction region 140, does not transmit all of the applied voltage and pinches at a constant voltage. It is off (Pinch-off). This voltage is called a pinning voltage and the pinning voltage depends on the P0 145 and N- (143) doping concentrations.

Specifically, the electrons generated by the photodiode 205 are moved to the PNP caption 140 and are transferred to the FD 131 node when the transfer transistor (Tx) 121 is turned on and converted into voltage.

Since the maximum voltage value of the P0 / N- / P- caption 140 becomes pinning voltage and the maximum voltage value of the node FD 131 becomes Vdd-Rx Vth, as shown in FIG. 2, the potential difference between both ends of the Tx 131 is shown. Due to this, electrons generated from the photodiode on the chip may be completely dumped to the FD 131 node without charge sharing.

That is, in the embodiment, the reason why the P0 / N- / Pwell junction is formed instead of the N + / Pwell junction in the silicon sub, which is the semiconductor substrate 100, is P0 / N- / Pwell during the 4-Tr APS Reset operation. In the junction, + voltage is applied to N- (143) and ground voltage is applied to P0 (145) and Pwell (141). Therefore, P0 / N- / Pwell double junction is more than Pinch-Off as in BJT structure. Will occur. This is called pinning voltage. Therefore, a voltage difference is generated in the source / drain at both ends of the Tx 121, and thus the photocharge is completely dumped from the N-well to the FD through the Tx at the Tx On / Off operation to prevent the charge sharing phenomenon.

Therefore, unlike the case where the photodiode is simply connected with N + junction in the technology of a general image sensor, according to the embodiment, problems such as degradation of saturation and degradation of sensitivity can be avoided.

Next, according to the embodiment, the first conductive connection region 147 is formed between the photodiode and the lead-out circuit 120 to minimize the dark current source by creating a smooth movement path of the photo charge. Deterioration of saturation and degradation of sensitivity can be prevented.

To this end, the embodiment may form an N + doped region as the first conductivity type connection region 147 for ohmic contact on the surface of the P0 / N− / P− junction 140. The N + region 147 may be formed to contact the N− 143 through the P0 145.

Meanwhile, in order to minimize the first conductive connection region 147 from becoming a leakage source, the width of the first conductive connection region 147 may be minimized.

To this end, the embodiment may proceed with a plug implant after etching the second metal contact 151a, but is not limited thereto. For example, the first conductive connection region 147 may be formed by forming an ion implantation pattern (not shown) and using the ion implantation mask as an ion implantation mask.

That is, the reason for N + doping locally only in the contact forming part as in the embodiment is to facilitate the formation of ohmic contact while minimizing the dark signal. As in the prior art, when N + Doping the entire Tx Source part, the dark signal may increase due to the substrate surface dangling bond.

3 shows another structure for the readout circuit. As shown in FIG. 3, a first conductive connection region 148 may be formed on one side of the electrical junction region 140.

Referring to FIG. 3, an N + connection region 148 for ohmic contact may be formed in the P0 / N− / P− junction 140, wherein the process of forming the N + connection region 148 and the M1C contact 151a is performed. It can be a Leakage Source. This is because the electric field EF may be generated on the Si surface of the substrate because the reverse bias is applied to the P0 / N− / P− junction 140. Crystal defects that occur during the contact formation process inside these electric fields become a source of liquidity.

In addition, when the N + connection region 148 is formed on the surface of the P0 / N- / P- junction 140, an E-Field by the N + / P0 junction 148/145 is added, which is also a leakage source. Can be

That is, the first contact plug 151a is formed in an active region formed of the N + connection region 148 without being doped with the P0 layer, and a layout for connecting the first contact plug 151a with the N-junction 143 is presented.

Then, the E-Field of the surface of the semiconductor substrate 100 does not occur, which may contribute to the reduction of dark current of the 3-D integrated CIS.

Referring back to FIG. 1, an interlayer insulating layer 160 and a wiring 150 may be formed on the semiconductor substrate 100. The wire 150 may include a second metal contact 151a, a first metal M1 151, a second metal M2 152, and a third metal M3 153, but is not limited thereto. It doesn't happen. In an embodiment, after forming the third metal 153, an insulating film may be deposited to prevent the third metal 153 from being exposed, and then an interlayer insulating layer 160 may be formed by performing a planarization process. Therefore, the surface of the interlayer insulating layer 160 having a uniform surface profile may be exposed on the semiconductor substrate 100.

Referring to FIG. 4, an image sensing unit 200 is formed on the interlayer insulating layer 160. The image sensing unit 200 may include a first doped layer (N−) 210 and a second doped layer (P +) 220 to have a photodiode structure of a PN junction. In addition, the image sensing unit 200 may have an ohmic contact layer (N +) 230 formed under the first doped layer 210.

For reference, the third metal 153 and the interlayer insulating layer 160 of the wiring 150 illustrated in FIG. 4 represent portions of the wiring 150 and the interlayer insulating layer 160 illustrated in FIG. 1. For convenience, some of the readout circuit 120 and the wiring 150 are omitted.

For example, the image sensing unit 200 ion-implants N-type impurities (N−) and P-type impurities (P +) in order into the p-type carrier substrate (not shown) having a crystalline structure, and thus the first doped layer 210. ) And the second doped layer 220 may be formed in a stacked structure. In addition, an ohmic contact layer 230 may be formed by ion implanting a high concentration of N-type impurities (N +) under the first doped layer 210. The ohmic contact layer 230 may lower the contact resistance between the image sensing unit 200 and the wiring 150.

In an embodiment, the first doped layer 210 may be formed to have a wider area than the second doped layer 220. The depletion region can then be expanded to increase the production of photoelectrons.

Next, the ohmic contact layer 230 of the carrier substrate (not shown) is positioned on the interlayer insulating layer 160, and a bonding process is performed to bond the semiconductor substrate 100 and the carrier substrate. Thereafter, the carrier substrate on which the hydrogen layer is formed is exposed by the cleaving process so that the image sensing unit 200 bonded on the interlayer insulating layer 160 is exposed to expose the surface of the second doped layer 220. . For example, the height of the image detection unit 200 may be about 1.0 ~ 1.5㎛.

That is, since the semiconductor substrate 100 and the image sensing unit 200 on which the readout circuit 120 is formed are formed by wafer-to-wafer bonding, defects may be prevented.

In addition, the image sensing unit 200 may be formed above the readout circuit 120 to increase the fill factor. In addition, since the image sensing unit 200 is bonded on the interlayer insulating layer 160 having a uniform surface profile, the bonding force may be physically improved.

Meanwhile, in the embodiment, the image sensing unit is formed to have a PN junction, but the image sensing unit may be formed to have a PIN junction.

Referring to FIG. 5, a via hole 240 penetrating the image sensing unit 200 and the interlayer insulating layer 160 is formed. The via hole 240 may expose a surface of the third metal 153 inside the interlayer insulating layer 160 as a deep via hole.

Although not shown, the via hole 240 may form a hard mask (not shown) and a photoresist pattern (not shown) on the image sensing unit 200, and then the image sensing unit 200 and the interlayer insulating layer ( 160 may be formed by selectively etching. In this case, the opening of the hard mask and the photoresist pattern may expose the surface of the image sensing unit 200 corresponding to the third metal 153. Thereafter, the photoresist pattern may be removed by an ashing process, and the hard mask may remain on the image sensing unit 200. In the embodiment, the hard mask is removed.

The via hole 240 may be formed by an etching process. In this case, the sidewall of the via hole 240 may be damaged in a crystal direction to increase the dark current of the image sensor.

Therefore, in the embodiment, after the via hole 240 is formed, the first cleaning process and the second cleaning process are performed to make the profile of the sidewall of the via hole 240 uniform.

First, the first cleaning process is performed using Tetra Methly Ammonium Hydroxide (TMAH) and HNO ₃ chemicals.

The first cleaning process using the TMAH chemical is a concentration of 10% to 60%, the process is carried out for 20 seconds to 30 minutes, the first cleaning process using the HNO ₃ chemical will be performed for 5 seconds to 60 seconds. Can be.

During the etching process for forming the via hole 240 in the image sensing unit 200, the p-type carrier substrate having a crystalline structure formed by epitaxial growth converts the substrate surface, thereby forming another direction ( direction occurs to increase the roughness.

In particular, since the inside of the via hole 240 is a photodiode formed region, it is difficult to perform plasma treatment.

In this case, when the p-type carrier substrate having the crystal structure in which the image sensing unit 200 is formed has a direction of [100], the [111] direction of the via hole 240 is an etching process for forming the via hole 240. It is formed on the side wall.

Accordingly, the TMAH chemical may be used to selectively remove silicon (Si) in different [111] directions.

In this case, when the TMAH chemical is used, the silicon surface in the [111] direction formed on the sidewalls of the via hole 240 has an etch rate higher than that of the silicon surface in the [100] direction, thereby selectively etching the silicon surface in the [111] direction. ) Becomes possible.

In the etching process for forming the via hole 240 in the image sensing unit 200, polysilicon is formed instead of epitaxial Si, which is removed using the HNO ₃ chemical. can do.

The TMAH and HNO ₃ chemicals can be used by spraying the chemical while rotating at 200 ~ 800 rpm in a spin method at a temperature of 25 ~ 40 ℃, the method using the TMAH and HNO ₃ chemical is not limited to this After proceeding with a method such as QDR (Quick Dump Drain), it may be dried by a method such as N ₂ dry (dry).

In addition, the second cleaning process is performed using a chemical containing hydrogen fluoride (HF).

The second cleaning process using the chemical including the HF is used to remove polymer residues generated during the photo process for forming the via hole 240, and diluted hydrogen fluoride (DHF) and buffered (BHF). chemicals such as hydrogen fluoride), H ₂ SO ₄ and H ₂ O ₂ .

Referring to FIG. 6, first and second barrier layers 260 and a metal layer 270 are formed on the image sensing unit 200 in which the via holes 240 are formed. For example, the first barrier layer 250 may be a Ti layer, and the second barrier layer 260 may be a TiN layer. In addition, the metal layer 270 may be formed of a metal such as tungsten (W), copper (Cu), or aluminum (Al). In an embodiment, the metal layer 270 may be tungsten.

The first and second barrier layers 250 and 260 may prevent oxidation of the third metal 153 exposed by the via hole 240 and protect the interlayer insulating layer 160. 200 may be formed in a thin film form along the steps of the via hole 240.

The metal layer 270 may be formed by depositing a metal material such that the via holes 240 in which the first and second barrier layers 250 and 260 are formed are gap-filled.

Referring to FIG. 7, the metal layer 270 is etched by the first etching process to form a contact plug 275 in the via hole 240. The first etching process may selectively remove only tungsten as an etch back process for the metal layer 270.

For example, the contact plug 275 may be formed by an etching process using SFx gas (1 <x <6) and Ar gas as an etching gas. In this case, since the SFx gas does not etch the Ti layer and the TiN layer and forms only a deformation of the surface, the SFx gas may be a defect source due to plasma damage, thereby removing the first and second barrier layers 250 and 260. Process is required.

The contact plug 275 formed by the first etching process may have a height corresponding to the height of the first doped layer 210. That is, the contact plug 275 may expose the second barrier layer 260 inside the via hole 240 corresponding to the second doped layer 220.

The contact plug 275 may correspond to an upper region of the first doped layer 210 in contact with the second doped layer 220 and the second doped layer 220 based on the sidewall of the via hole 240. The second barrier layer 260 may be exposed. For example, the contact plug 275 may be formed to have a first height H based on the third metal 153.

Referring to FIG. 8, a second etching process is performed on the second barrier layer 260 to form a second barrier pattern 255, and a third etching process is performed on the first barrier layer 250. The first barrier pattern 265 is formed.

The first barrier pattern 265, the second barrier pattern 255, and the contact plug 275 may be formed to have the same first height H, and sidewalls of the via hole 240 may be exposed.

That is, the first and second barrier patterns 255 and the contact plugs 275 may be electrically connected only to the first doped layer 210 and the third metal 153 in the via hole 240 so that the image detector Photoelectric charges generated at 200 may be transferred to the readout circuit 120. In addition, since the first and second barrier patterns 255 and the contact plugs 275 are electrically connected only to the first doped layer 210 in the via hole 240, the first doped layer 210 and the first The two doped layers 220 may be electrically separated to prevent the device from malfunctioning.

Although not shown, an upper electrode, a color filter, and a micro lens may be additionally formed on the image detector 200.

In the method of manufacturing the image sensor according to the above-described embodiment, the profile of the sidewall of the via hole may be uniform, thereby minimizing damage to the image sensing unit and minimizing generation of dark current.

The above-described embodiments are not limited to the above-described embodiments and drawings, and it is common in the technical field to which the present embodiments belong that various changes, modifications, and changes can be made without departing from the technical spirit of the present embodiments. It will be apparent to those who have

1 to 8 are side cross-sectional views illustrating a manufacturing process of an image sensor according to an embodiment.

Claims

Forming an interlayer insulating layer including wiring on the semiconductor substrate;

Forming an image sensing unit on which the first doped layer and the second doped layer are stacked on the interlayer insulating layer;

Forming a via hole through the image sensing unit and the interlayer insulating layer to expose the wiring;

Performing a first cleaning process and a second cleaning process on the semiconductor substrate on which the via holes are formed; And

And forming a first barrier pattern, a second barrier pattern, and a contact plug in the via hole.

The method of claim 1,

Forming a first barrier pattern, a second barrier pattern, and a contact plug in the via hole may include:

Forming a first barrier layer and a second barrier layer on sidewalls and bottom surfaces of the via holes;

Forming a contact plug in the via hole to expose a second barrier layer corresponding to the second doped layer in the via hole and to have a first height that is the height of the first doped layer;

Performing a first etching process on the exposed second barrier layer to form a second barrier pattern having the same height as the contact plug; And

And forming a first barrier pattern by performing a second etching process on the first barrier layer to expose the second doped layer in the via hole.

The method of claim 1,

Forming the contact plug,

Forming a metal layer to gap-fill an inside of the via hole in which the first and second barrier layers are formed; And

And selectively removing the metal layer by performing an etch back process on the metal layer to have a first height corresponding to the height of the first doped layer.

The method of claim 1,

The first cleaning process is a method of manufacturing an image sensor comprising using a TMAH (Tetra Methly Ammonium Hydroxide) and HNO ₃ chemical.

The method of claim 4, wherein

The first cleaning process using the TMAH chemical is a manufacturing method of the image sensor comprising the process proceeds for 20 seconds to 30 minutes.

The method of claim 4, wherein

The TMAH chemical method of manufacturing an image sensor comprising using at a concentration of 10 ~ 60%.

The method of claim 4, wherein

The first cleaning process using the HNO ₃ chemical method of manufacturing an image sensor comprising a 5 seconds to 60 seconds.

The method of claim 1,

The second cleaning process is a method of manufacturing an image sensor comprising the progress using a chemical containing hydrogen fluoride (HF).

The method of claim 8,

The chemical containing HF is a method of manufacturing an image sensor including diluted hydrogen fluoride (DHF), buffered hydrogen fluoride (BHF), H ₂ SO ₄ and H ₂ O ₂ .

The method of claim 1,

And the contact plug is formed of tungsten, the first barrier layer is formed of a Ti layer, and the second barrier layer is formed of TiN.