KR20100054066A - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
KR20100054066A
KR20100054066A KR1020080123595A KR20080123595A KR20100054066A KR 20100054066 A KR20100054066 A KR 20100054066A KR 1020080123595 A KR1020080123595 A KR 1020080123595A KR 20080123595 A KR20080123595 A KR 20080123595A KR 20100054066 A KR20100054066 A KR 20100054066A
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KR
South Korea
Prior art keywords
method
information storage
switching elements
formed
elements
Prior art date
Application number
KR1020080123595A
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Korean (ko)
Inventor
이상윤
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이상윤
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Priority to KR20080112975 priority Critical
Priority to KR1020080112975 priority
Application filed by 이상윤 filed Critical 이상윤
Priority claimed from US12/618,542 external-priority patent/US7867822B2/en
Priority claimed from US12/637,559 external-priority patent/US20100133695A1/en
Priority claimed from US12/731,087 external-priority patent/US20100190334A1/en
Publication of KR20100054066A publication Critical patent/KR20100054066A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10805Dynamic random access memory structures with one-transistor one-capacitor memory cells
    • H01L27/10808Dynamic random access memory structures with one-transistor one-capacitor memory cells the storage electrode stacked over transistor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10805Dynamic random access memory structures with one-transistor one-capacitor memory cells
    • H01L27/10823Dynamic random access memory structures with one-transistor one-capacitor memory cells the transistor having a trench structure in the substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/10873Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the transistor
    • H01L27/10876Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the transistor the transistor having a trench structure in the substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor

Abstract

PURPOSE: A semiconductor memory device is provided to improve the integration degree of the semiconductor memory device by forming information storage devices in upper part and lower part of switch elements. CONSTITUTION: Switching elements are separated from a semiconductor substrate and have a vertical channel. Information storage device are arranged in upper part and lower part of the switching elements. Each information storage device comprises a storage node electrode(282) of a cylinder type, a plate electrode(284) on the storage node electrode, and a dielectric layer. The storage node electrode is connected to the switching elements.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a three-dimensional structure that can improve the degree of integration.

In order to highly integrate a semiconductor device, the size of a pattern formed on a chip and the distance between the formed patterns are gradually reduced. However, when the size of the pattern is reduced as described above, a problem such as an increase in leakage current occurs. Therefore, there is a limit to increasing the degree of integration by reducing the size of the pattern. Therefore, recently, in order to highly integrate a semiconductor device, three-dimensional semiconductor devices having semiconductor unit elements such as MOS transistors stacked on a substrate have been developed.

Accordingly, an object of the present invention is to provide a semiconductor memory device having a three-dimensional structure that can improve the degree of integration.

Technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

The semiconductor device according to the embodiment of the present invention for solving the above problems is formed spaced apart from the semiconductor substrate, and includes a switching element having a vertical channel and information storage elements disposed on the upper and lower portions of the switching elements, respectively The information storage elements of the storage device include a cylindrical storage node electrode and a plate electrode on the storage node electrode, a storage node electrode and a dielectric film between the plate electrode, and the storage node electrode is connected to the switching elements.

The semiconductor device according to another embodiment of the present invention for solving the above problems is formed spaced apart from the semiconductor substrate, and includes a switching element having a vertical channel and information storage elements disposed on and under the switching elements, respectively The information storage elements of the device include first and second electrodes and a ferroelectric film or a phase change film between the first and second electrodes, and a first electrode is connected to the switching elements.

The semiconductor device according to another embodiment of the present invention for solving the above problems is formed spaced apart from the semiconductor substrate, and electrically connected to the switching elements and switching elements having a horizontal channel, the upper and lower portions of the switching elements Formed information storage elements.

Specific details of other embodiments are included in the detailed description and the drawings.

According to the semiconductor device of the present invention, since the information storage elements can be formed above and / or below the switching element, the degree of integration of the semiconductor memory element can be improved.

In addition, by forming the information storage devices on the logic device, the degree of integration of the semiconductor memory device may be further improved.

In addition, the data storage devices may be electrically connected to the switching devices having the vertical channel, thereby providing various advantages such as to further improve the degree of integration of the semiconductor memory device.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the dimensions of the substrates, layers (films), regions, recesses, pads, patterns or structures are shown to be larger than actual for clarity of the invention. In the present invention, each layer (film), region, pad, recess, pattern or structure is formed on the substrate, each layer (film), region, pad or patterns "on", "top" or "bottom". When referred to as meaning that each layer (film), region, pad, recess, pattern or structure is formed directly over or below the substrate, each layer (film), region, pad or patterns, or Other layers (films), other regions, different pads, different patterns or other structures may additionally be formed on the substrate.

1 to 6 are cross-sectional views of a DRAM device according to the present invention.

A semiconductor memory device according to a first embodiment of the present invention will be described in detail with reference to FIG. 1.

Referring to FIG. 1, a logic region 20 and a memory cell region 10 are sequentially disposed on a semiconductor substrate 100. That is, the memory cell region 10 is positioned on the logic region 20. The logic region 20 on the semiconductor substrate 100 includes logic elements, and the memory cell region 10 spaced apart from the top surface of the semiconductor substrate 100 includes switching elements and information storage elements. Meanwhile, in embodiments of the present invention, the logic region may be located above the memory cell region.

In more detail, the semiconductor substrate 100 may be bulk silicon, bulk silicon-germanium, or a semiconductor substrate having a silicon or silicon-germanium epi layer formed thereon. In addition, the semiconductor substrate 100 may include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, and thin film transistor (TFT) technology. Doped and undoped semiconductors, silicon epitaxial layers supported by the underlying semiconductor, and other semiconductor structures well known to those skilled in the art.

Device isolation regions 102 defining an active region are formed in the semiconductor substrate 100, and NMOS and PMOS transistors 110 and 112, a resistor (not shown), and a diode are formed on the active region of the semiconductor substrate 100. And wires 164 and 174 may be formed to form logic elements. Logic elements control the switching elements of the memory cell region 10 to write or read data to the information storage elements.

The gate electrode pattern 110 is formed on the active region of the semiconductor substrate 100, and the source / drain regions 112 doped with impurities are formed in both active regions of the gate electrode pattern 110. The gate electrode pattern 110 may have a structure in which the gate insulating layer pattern and the gate conductive layer pattern are sequentially stacked, and insulating spacers may be formed on both sidewalls. In addition, although not shown in the figure, logic elements may be formed over the gate electrode patterns 110 in the logic region 20 over a plurality of layers. The logic elements formed in the logic region 20 may be buried by the interlayer insulating layer 120.

On top of the logic elements switching elements and information storage elements are formed. That is, the switching elements may be spaced apart from the top surface of the semiconductor substrate 100, and the information storage elements may be formed on and under the switching elements. More specifically, the switching elements may be NMOS or PMOS transistors, and in the first embodiment of the present invention, the transistors may have a vertical channel. Further, in the first embodiment of the present invention, the information storage elements may be capacitors, and the capacitors may be formed above and below the switching elements.

In more detail, capacitors are formed on the interlayer insulating layer 120 covering the logic elements. In this case, the capacitors may be a cylinder type structure or a stack type structure. In the first embodiment of the present invention, a cylindrical structure will be described as an example.

That is, first electrodes 132 of capacitors may be formed on the interlayer insulating layer 120. The first electrode 132 may be a plate electrode to which a ground voltage is applied. The first electrodes 132 are electrically connected to each other and may have a pillar shape. A dielectric film (not shown) of a capacitor is conformally formed on the surfaces of the pillar-shaped first electrodes 132. On the dielectric layer (not shown), a second electrode 134 conformally covering the pillar is formed. That is, the second electrode 134 is a storage node electrode and surrounds an upper surface and a sidewall of the first electrode 132 and is electrically separated from each other. In other words, each of the second electrodes 134 may have a cylindrical shape opened downward.

The first electrode 132 and the second electrode 134 of the capacitor may be formed of polysilicon or a metal material, and the dielectric layer (not shown) may be a tantalum oxide layer (Ta 2 O 5 ) or an aluminum oxide layer (Al 2 O 3 ). It can be formed of a single film or a laminated film of a tantalum oxide film / titanium oxide film, an aluminum oxide film / titanium oxide film, or the like.

The capacitors 132 and 134 are covered by the interlayer insulating layers 140 and 150, and in the interlayer insulating layers 140 and 150, contact plugs 162 contacting the upper surfaces of the second electrodes 134, and Contact plugs 164 connected to the logic elements. The second electrodes 134 of the capacitor are connected one-to-one with the switching elements through the contact plugs 162, 172, and 182.

The switching elements include a plurality of pillar-shaped semiconductor layer patterns 202, 204, and 206, and a gate electrode 220 surrounding a center of a sidewall of the semiconductor layer patterns 202, 204, and 206. A gate insulating film (not shown) is formed between the sidewalls of the patterns 202, 204, and 206 and the gate electrode 220. The pillar-shaped semiconductor layer patterns 202, 204, and 206 are alternately stacked with the first conductive semiconductor patterns 202 and 206 and the second conductive semiconductor pattern 204. Then, the first conductivity type semiconductor patterns 202 and 206 are disposed on the lowermost layer and the uppermost layer.

In embodiments of the present invention, the switching elements are NMOS or PMOS transistors, where the first conductivity type is n type and the second conductivity type is p type when the NMOS transistor. In the case of a PMOS transistor, the first conductivity type is p-type and the second conductivity type is n-type.

Further, in embodiments of the present invention, the semiconductor patterns 202, 204, and 206 may be formed of a polycrystalline semiconductor, a single crystal semiconductor, a semiconductor partially containing metal, or a mixture thereof. Here, the single crystal semiconductor having better properties than the polycrystalline semiconductor may be formed through the bonding of the single crystal semiconductor substrate. The three-dimensional semiconductor through the semiconductor substrate bonding is well described in the patent application 10-2008-100892 and the like filed by the inventor.

In addition, the first conductive semiconductor layer patterns 202 and 206 positioned at the lowermost layer and the uppermost layer correspond to the source / drain regions of the transistors, and the second conductivity between the first conductive semiconductor layer patterns 202 and 206. The type semiconductor layer pattern 204 corresponds to a channel region.

The gate electrode 220 around the columnar semiconductor patterns 202, 204, and 206 may be formed in the form of a spacer on sidewalls of the columnar semiconductor layer patterns 202, 204, and 206 and adjacent semiconductor layer patterns. It may be in contact with gate electrodes formed around 202, 204, 206. That is, the columnar semiconductor patterns 202, 204, and 206 are disposed on the interlayer insulating layer 180 to be spaced apart from each other by a predetermined interval so that the gate electrodes 220 formed on the sidewalls may contact each other. Accordingly, one gate electrode line 220 may be formed to surround sidewalls of the plurality of columnar semiconductor patterns. The gate electrode 220 may be electrically connected to the logic elements through the contact plug 164.

Meanwhile, the semiconductor layer patterns 202, 204, and 206 stacked in a pillar shape may be formed by bonding a semiconductor substrate including impurity layers. Accordingly, the bonding layer 190 is formed on the bottom surface of each of the pillar-shaped semiconductor patterns 202, 204, and 206. In this case, the bonding layer 190 may be formed of a conductive adhesive material. Accordingly, the contact plug 182 electrically connected to the second electrode 134 or the wiring 172 (that is, the bit line) of the capacitor may be electrically connected to the bonding layer 190.

In other words, the second electrode 134 of the capacitor may be electrically connected to the bottom surface of the plurality of pillar-shaped semiconductor patterns 202, 204, and 206, or the bit line 172 may be electrically connected to each other. The bit lines 172 and the second electrodes 13 are alternately disposed under the arranged columnar semiconductor patterns 202, 204, and 206. In addition, the bit lines 172 may be electrically connected to the logic element through the contact plug 164.

Contact plugs 242 and wires 252 are sequentially formed on the top surfaces of the columnar semiconductor patterns 202, 204, and 206, respectively. The second electrodes 282 of the capacitor are formed on the columnar semiconductor patterns 202, 204, and 206 electrically connected to the bit lines 172, respectively. In other words, the capacitors 132 and 134 and the bit line 252 face each other with the columnar semiconductor patterns 202, 204 and 206 interposed therebetween.

Capacitors 282 and 284 located above the switching elements include a cylindrical storage node electrode (ie, a second electrode 282) which is open upward. In addition, a dielectric film (not shown) is formed on a surface of each of the second electrodes 282, and a plate electrode (ie, a first electrode 284) filling the inside of the second electrodes 282 on the dielectric film (not shown). Is formed.

As described above, in the first embodiment of the present invention, the bottom surfaces of the columnar semiconductor patterns 202, 204, and 206 may be electrically connected to the second electrode 134 of the capacitor, and the top surface may be connected to the bit line 252. Can be electrically connected. On the contrary, the bottom surfaces of the columnar semiconductor patterns 202, 204, and 206 may be electrically connected to the bit line 172, and the top surface thereof may be connected to the second electrode 282 of the capacitor.

On the other hand, a wiring 294 may be formed on the uppermost layer of the memory cell region 10 that is commonly connected to the wiring of the memory cell region 10 and the wirings of the logic region 20. . These wires 294 may also be used as conductive pads.

A semiconductor memory device according to a second embodiment of the present invention will be described in detail with reference to FIG. 2. For the second embodiment, detailed description of technical features overlapping with the first embodiment of the present invention will be omitted, and differences from the first embodiment will be described in detail.

Referring to FIG. 2, in the semiconductor memory device according to the second exemplary embodiment, the memory cell region 10 and the logic region 20 are horizontally disposed. Accordingly, the information storage element, the switch element, and the information storage element are sequentially formed on the semiconductor substrate 100 in the memory cell region 10. That is, switching elements spaced apart from the surface of the semiconductor substrate 100 are formed on the semiconductor substrate 100 in the memory cell region 10. Information storage elements are formed above and below the switching elements. The structures of the switching elements and the information storage elements are substantially the same as in the first embodiment of the present invention.

In addition, logic elements such as NMOS or PMOS transistors 110 and 112 may be formed on the semiconductor substrate 100 in the logic region 20. In addition, logic elements, wirings 254 and 174 and contact plugs 164, 244 and 292 connected to the gate electrode 220 and the bit lines 172 and 252 of the memory cell region 10 may be formed. Can be. In addition, a wiring 294 may be commonly connected to the wiring of the memory cell region 10 and the wirings of the logic region 20.

As described above, in the semiconductor memory devices according to the first and second embodiments, the switching elements and the information storage elements may have the structures shown in FIGS. 3 to 6. 3 to 6 show cross sections of a memory cell region in the semiconductor memory devices according to the first and second embodiments.

Referring to FIG. 3, the switching elements are vertical channel transistors and include pillar-shaped semiconductor patterns 202, 203, 204, 205, and 206, gate electrodes 220, and bit lines 252. The information storage elements are electrically connected to the top and bottom surfaces of the columnar semiconductor patterns 202, 203, 204, 205, and 206, respectively.

In more detail, the columnar semiconductor patterns 202, 203, 204, 205, and 206 may include the first conductive semiconductor patterns 202, 204, and 206 and the second conductive semiconductor patterns 203 and 205. The layers are alternately stacked, and the first conductive semiconductor patterns 202, 204, and 206 are disposed on the uppermost layer and the lowermost layer. In this case, the second conductivity type semiconductor patterns 203 and 205 include at least two or more. That is, the columnar semiconductor patterns 202, 203, 204, 205, and 206 may be stacked with semiconductor patterns in an n / p / n / p / n type or p / n / p / n / p type structure. Here, the first conductive semiconductor patterns 202, 204, and 206 correspond to the source / drain regions of the transistor, and the second conductive semiconductor patterns 203 and 205 correspond to the channel regions of the transistor. Accordingly, the gate electrodes 220 are formed around the second conductive semiconductor patterns 203 and 205 corresponding to the channel region through the gate insulating layer. The bit line 252 is formed around the first conductive semiconductor pattern 202, 204, and 206 positioned at the center of the pillar-shaped semiconductor patterns 202, 203, 204, 205, and 206. That is, the volatile memory device shown in FIG. 3 has a structure in which two memory cells share a bit line 252.

Referring to FIG. 4, the switching element is formed on the bonded semiconductor substrate 200 spaced apart from the semiconductor substrate 100 of FIG. 1. The junction semiconductor substrate 200 has an active region defined by device isolation regions 201, and transistors are formed on the active region. The device isolation regions 201 may be formed through the junction semiconductor substrate 200. The transistors include gate patterns 220 formed on the junction semiconductor substrate 200 and source / drain regions 222 formed in active regions on both sides of the gate patterns 220. In this case, the source / drain regions 222 may be formed by implanting impurities in a predetermined depth in the junction semiconductor substrate 200 or by implanting impurities to the bottom of the junction semiconductor substrate 200.

In addition, on the junction semiconductor substrate 200, transistors adjacent to each other may share a drain region 222 between the gate patterns 210, and the drain region 222 may be connected to the bit line 252 through the contact plug 242. ) Is electrically connected. In addition, a capacitor is electrically connected to the source region 222 of each transistor. In this case, the capacitor formed under the transistors may have a contact plug 215 electrically connected to the bottom surface of the drain region 222 through the junction semiconductor substrate 200.

Here, an insulating film 213 may be formed around the contact plug 215 penetrating the junction semiconductor substrate 200 to electrically insulate the junction layer 190 made of a conductive material and the junction semiconductor substrate 200. Can be. The insulating layer 213 may surround a portion of the sidewall of the contact plug 215 having a pillar shape. That is, the insulating film 213 does not penetrate the junction semiconductor substrate 200 like the contact plug 215.

In other words, the insulating layer 213 does not extend to the drain region 222 formed in the junction semiconductor substrate 200. Accordingly, the contact plug 215 and the drain region 222 may be electrically connected to each other while preventing sidewalls of the contact plug 215 from being electrically connected to the bonding layer 190 and the bonding semiconductor substrate 200.

Referring to FIG. 5, a switching element is formed on the bonded semiconductor substrate 200 spaced apart from the semiconductor substrate (100 of FIG. 1). Accordingly, in the junction semiconductor substrate 200, an active region is defined by device isolation regions 201, and transistors are formed in the active region. The transistors include gate patterns 220 formed on the junction semiconductor substrate 200 and source / drain regions 222 formed in active regions on both sides of the gate patterns 220. Transistors are separated from source / drain regions 222 adjacent by device isolation region 201. Accordingly, bit lines 252 are connected to drain regions 222 of the transistors, respectively. In addition, a capacitor is electrically connected to the source region 222 of each transistor. In this case, the capacitor formed under the transistors may have a contact plug 215 electrically connected to the bottom surface of the source region 222 through the junction semiconductor substrate 200. Here, an insulating film 213 may be formed around the contact plug 215 to electrically insulate the bonding layer 190 made of a conductive material. In addition, the insulating layer 213 surrounding the contact plug 215 does not extend to the source region 222.

Referring to FIG. 6, transistors are formed on the junction semiconductor substrate 200, and adjacent source / drain regions 222 are separated by the device isolation region 201. Accordingly, bit lines 252 are connected to drain regions 222 of the transistors, respectively. In addition, a capacitor is electrically connected to the source region 222 of each transistor. In this case, the capacitor formed under the transistors may be electrically connected to the drain region 222 through the contact plug 244 and the wiring 254 passing through the junction semiconductor substrate 200. In addition, an insulating layer 242 may be formed around the contact plug 244 to electrically insulate the bonding layer 190 made of a conductive material.

Meanwhile, although capacitors are formed on the upper and lower portions of the transistors in FIGS. 4 to 6, the capacitors may be formed only on the upper portions of the transistors or may be formed only on the lower portions of the transistors.

7 and 8 are cross-sectional views of a PRAM device according to the present invention.

7 and 8, in the semiconductor memory devices according to the first and second embodiments of the present invention, as a data storage element, a phase change material such as GeSbTe generates local heat by an electrical pulse. A device for storing information by using the characteristic of changing to a crystalline and an amorphous state by using is used. That is, the phase change films 144 and 274 are formed between the first electrodes 142 and 276 and the second electrodes 146 and 272. Accordingly, the semiconductor memory device may store on-off digital data using the phase change of the phase change layers 144 and 274, and may read the digital data using the phase change films 144 and 274.

Such information storage elements are connected one-to-one with switching elements having vertical channels. In addition, the information storage elements and the switching elements may be electrically connected to logic elements located below or on one side.

9 and 10 are cross-sectional views of the FRAM device according to the present invention.

9 and 10, in the semiconductor memory devices according to the first and second embodiments of the present invention, as information storage elements, even if the electric field is removed using high residual polarization of the ferroelectric material, the data is not erased. An element for storing the memory is used. That is, ferroelectric films 145 and 275 are formed between the first electrodes 143 and 277 and the second electrodes 147 and 273.

Such information storage elements are connected one-to-one with switching elements having vertical channels. In addition, the information storage elements and the switching elements may be electrically connected to logic elements located below or on one side.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is shown by the following claims rather than the above description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 to 6 are cross-sectional views of a DRAM device according to the present invention.

7 and 8 are cross-sectional views of a PRAM device according to the present invention.

9 and 10 are cross-sectional views of the FRAM device according to the present invention.

Claims (33)

  1. Switching elements formed apart from the semiconductor substrate and having vertical channels; And
    Information storage elements disposed above and below the switching elements,
    Each of the information storage elements includes a cylindrical storage node electrode and a plate electrode on the storage node electrode, and a dielectric layer between the storage node electrode and the plate electrode, wherein the storage node electrode is connected to the switching elements. Semiconductor memory device.
  2. Switching elements formed apart from the semiconductor substrate and having vertical channels; And
    Information storage elements disposed above and below the switching elements,
    Each of the information storage elements may include first and second electrodes and a ferroelectric film or a phase change film between the first and second electrodes, and the first electrode may be connected to the switching elements. .
  3. The method according to claim 1 or 2,
    The switching elements,
    Semiconductor layer patterns stacked in a pillar shape and doped with impurities;
    A gate electrode surrounding sidewall center portions of the semiconductor layer patterns; And
    And a gate insulating layer formed between sidewalls of the semiconductor layer patterns and the gate electrode.
  4. The method of claim 3, wherein
    And the semiconductor layer patterns are formed of a single crystal semiconductor.
  5. The method of claim 3, wherein
    The semiconductor layer patterns may include a first conductive semiconductor layer pattern and a second conductive semiconductor layer pattern, and the first conductive semiconductor layer patterns may be disposed on an uppermost layer and a lowermost layer.
  6. The method of claim 5,
    The impurity layer patterns are n-type / p-type / n-type or p-type / n-type / p-type impurity layer patterns.
  7. The method of claim 5,
    The switching device further comprises a metal layer in contact with the bottom surface of the switching device.
  8. The method of claim 5,
    The information storage elements are connected one-to-one with the semiconductor layer patterns,
    The information storage elements disposed on the switching elements are electrically connected to the upper surfaces of the semiconductor patterns,
    And the information storage elements disposed under the switching devices are electrically connected to lower surfaces of the semiconductor patterns.
  9. The method of claim 8,
    And bit lines electrically connected to the semiconductor layer pattern, the bit lines facing the information storage elements with the semiconductor layer pattern therebetween.
  10. The method of claim 8,
    And the information storage element connected to an upper surface of the semiconductor layer pattern and the information storage element connected to a lower surface of the semiconductor layer pattern alternately horizontally.
  11. The method of claim 5,
    And a plurality of bit lines including a plurality of the second conductivity type semiconductor layer patterns, and surrounding sidewalls of the first conductivity type semiconductor layer pattern among the semiconductor layer patterns.
  12. The method of claim 11,
    And the information storage elements are electrically connected to upper and lower surfaces of the semiconductor layer patterns.
  13. Switching elements formed apart from the semiconductor substrate and having horizontal channels; And
    And information storage elements electrically connected to the switching elements and formed on and under the switching elements.
  14. The method of claim 13,
    And the information storage element includes first and second electrodes and an information storage layer between the first and second electrodes.
  15. The method of claim 14,
    And the second electrodes of the information storage elements are connected to the switching elements.
  16. The method of claim 14,
    And the information storage layer is formed of a dielectric film, a ferroelectric film, or a phase change film.
  17. The method of claim 13,
    Further comprising another semiconductor substrate spaced from the semiconductor substrate,
    And the switching elements are formed on an upper surface of the other semiconductor substrate.
  18. The method of claim 17,
    And the other semiconductor substrate is formed of a single crystal semiconductor.
  19. The method of claim 17,
    And a metal bonding layer in contact with the bottom surface of the other semiconductor substrate.
  20. The method of claim 17,
    The switching elements,
    A gate insulating film and a gate electrode formed on the another semiconductor substrate; And
    And impurity regions formed in the gate insulating layer and the other semiconductor substrate on both sides of the gate electrode.
  21. The method of claim 20,
    The switching elements adjacent to each other share an impurity region formed between the gate electrodes,
    And a bit line electrically connected to the impurity regions shared by the switching elements.
  22. The method of claim 21,
    And the information storage elements are electrically connected to the impurity regions spaced from the impurity regions shared by the switching elements.
  23. The method of claim 20,
    The switching elements adjacent to each other include the impurity regions electrically separated from each other between the gate electrodes.
  24. The method of claim 23,
    And the information storage elements are electrically connected to the impurity region on one side of the gate electrode.
  25. The method of claim 23,
    And a bit line electrically connected to the impurity region on the other side of the gate electrode.
  26. The method of claim 20,
    One of the information storage elements adjacent to each other is disposed above the switching elements, and the other is disposed below the switching elements.
  27. The method of claim 26,
    And the information storage element disposed under the switching elements is electrically connected through a contact plug that extends into the other semiconductor substrate and contacts a lower surface of the impurity region.
  28. 28. The method of claim 27,
    And an insulating film formed between the another semiconductor substrate and the contact plug.
  29. The method of claim 26,
    And the information storage element disposed under the switching elements is electrically connected to an upper surface of the impurity region through contact plugs passing through the other semiconductor substrate and wirings on the switching element.
  30. 30. The method of claim 29,
    And an insulating film formed between the another semiconductor substrate and the contact plug.
  31. The method according to any one of claims 1, 2 and 13,
    And a logic device formed on the semiconductor substrate and controlling the switching devices.
  32. The method of claim 31, wherein
    And the logic elements are formed under the information storage elements.
  33. The method according to any one of claims 1, 2 and 13,
    And logic elements arranged in parallel with the switching elements and the information storage elements to control the switching elements.
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US12/618,542 US7867822B2 (en) 2003-06-24 2009-11-13 Semiconductor memory device
US12/637,559 US20100133695A1 (en) 2003-01-12 2009-12-14 Electronic circuit with embedded memory
US12/731,087 US20100190334A1 (en) 2003-06-24 2010-03-24 Three-dimensional semiconductor structure and method of manufacturing the same

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015195084A1 (en) * 2014-06-16 2015-12-23 Intel Corporation Embedded memory in interconnect stack on silicon die

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015195084A1 (en) * 2014-06-16 2015-12-23 Intel Corporation Embedded memory in interconnect stack on silicon die

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