KR20100053762A - Stacked wafer level package and method manufacturing the same - Google Patents

Abstract

PURPOSE: A stacked wafer level package and a method for manufacturing the same are provided to prevent the generation of misalignment during a stacking process by previously bonding solder balls on a conductive layer before a semiconductor chip mounting process, a rearranged wiring layer formation process and a stacking process are performed. CONSTITUTION: An external connection unit is arranged on the lower side of a rearranged wiring layer and is electrically connected to the rearranged wiring layer. A chip connection pad and an internal connection pad(130b) are arranged on the upper side of the rearranged wiring layer and are electrically connected to the rearranged wiring layer. A semiconductor chip is mounted on the rearranged wiring layer to be connected to the chip connection pad. Solder balls(140) are connected to the internal connection pad. A sealing material(170) exposes a part of the solder balls and seals the semiconductor chip. An electronic component is stacked on the sealing material and is electrically connected to the exposed solder balls.

Description

Stacked wafer level package and method for manufacturing same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated wafer level package and a method of manufacturing the same, wherein a solder ball for interconnection of an electronic component to be laminated is bonded in advance to a conductive layer for forming a rearranged wiring layer, and then a semiconductor chip mounting process and a rearranged wiring layer. The present invention relates to a laminated wafer level package and a method of manufacturing the same, which can improve a misalignment problem occurring in the lamination step by performing a forming step and a lamination step.

The trend in today's electronics industry is to make products that are lighter, smaller, faster, more versatile, more powerful and more reliable. One of the key technologies that enables this product design goal is the semiconductor package.

The semiconductor package is a technology for efficiently packaging devices used in electronic products, and is being developed in various forms as it is a technology that will determine the performance of semiconductor devices and the price, performance, and reliability of the final product.

Among the semiconductor packages, the stacked chip package may be manufactured by stacking semiconductor chips into a single package, thereby expanding the semiconductor package capacity or minimizing the mounting area based on the capacity of the semiconductor package.

The manufacturing method of these stacked chip packages includes both a wafer fabrication process of manufacturing individual semiconductor chips and a package assembly process of separating individual semiconductor chips from a wafer and then assembling the final product into a semiconductor package. .

As a conventional method of manufacturing a stacked chip package includes both a wafer manufacturing process and a package assembling process, reliability and degradation of process cost due to an increase in the throughput and complexity of the process are required. The increase in cost, and eventually, the production of high-priced products could bring down the disadvantages of price competitiveness.

Accordingly, a stacked wafer level package has been developed that includes a process of mounting a chip on a substrate and then forming a rearranged wiring layer, stacking a dielectric layer, and forming a via hole. That is, the laminated wafer-level package can reduce the manufacturing process, manufacturing time and manufacturing cost by performing both the semiconductor chip and the packaging on the wafer substrate.

However, the laminated wafer level package is formed in the chip and subsequent processes by a heat treatment process performed after chip mounting, according to a deformation of the wafer substrate such as a difference in coefficient of thermal expansion between the wafer substrate or the semiconductor chip or warpage of the wafer substrate. It may cause poor contact with the rearranged wiring layer. In addition, many defects may occur in subsequent processes performed after chip mounting, such as a layer stacking process and a via hole forming process.

In addition, in the process of further stacking another chip on the chip, deformation of the wafer substrate may cause misalignment of the chip to be stacked.

Therefore, a stack wafer level package technology that can shorten the conventional manufacturing process and manufacturing time has emerged, but there has been a problem that the yield is reduced and the cost is increased due to the misalignment occurring in the stacking process.

An object of the present invention is to laminate by soldering the solder ball for interconnection of the component to be laminated to the conductive layer for forming the rearranged wiring layer in advance, and then performing the semiconductor chip mounting step, the rearranged wiring layer forming step and the lamination step, The present invention provides a laminated wafer level package and a method of manufacturing the same that can improve the misalignment caused in the process.

In order to achieve the above technical problem, an aspect of the present invention provides a stacked wafer level package. The laminated wafer level package includes a rearrangement wiring layer; An external connection means disposed under the rearrangement wiring layer and electrically connected to the rearrangement wiring layer; A chip connection pad and an internal connection pad disposed on the rearrangement wiring layer and electrically connected to the rearrangement wiring layer; A semiconductor chip mounted on the rearrangement wiring layer to be connected to the chip connection pad; A solder ball connected to the internal connection pad; A sealing member exposing a portion of the solder ball and sealing the semiconductor chip; And an electronic component stacked on the sealing member and electrically connected to the exposed solder balls.

Here, the electronic component may have any one of a chip, a module, and a package.

The display device may further include a buffer unit covering at least a connection portion between the chip connection pad and the semiconductor chip.

The electronic device may further include a stacked buffer part filled between the electronic component and the sealing member.

In addition, the external connection means may be any one of a metal bump and a solder ball.

The semiconductor chip may be mounted using any one of soldering, a conductive paste, a non-conductive paste (NCP), and an anisotropic conductive film (ACF).

Another aspect of the present invention to achieve the above technical problem provides a method of manufacturing a laminated wafer level package. The manufacturing method includes preparing a substrate; Forming a conductive layer on the substrate; Forming a chip connection pad and an internal connection pad on the conductive layer; Forming a solder ball connected to the internal connection pad; Mounting a semiconductor chip on the conductive layer so as to be connected to the chip connection pad; Forming a sealing member for sealing the solder ball and the semiconductor chip; Separating the substrate from the conductive layer; Etching the conductive layer to form a rearranged wiring layer; Forming external connection means on the rearrangement wiring layer; Forming a contact hole exposing the solder ball to the sealing member; And stacking electronic components to be electrically connected to the solder balls exposed through the contact holes.

The connection between the semiconductor chip and the chip connection pad may use any one of soldering, a conductive paste, a non-conductive paste (NCP), and an anisotropic conductive film (ACF).

In addition, a buffer unit may be further formed to cover at least a connection portion between the chip connection pad and the semiconductor chip.

In addition, at least a stack buffer part surrounding a connection portion between the solder ball and the electronic component may be further formed.

In addition, the substrate further includes a sacrificial layer on an upper surface thereof, and the separation of the substrate from the conductive layer may be performed by removing the sacrificial layer.

In addition, the sacrificial layer may be formed of any one of metal, silicon oxide, silicon nitride, and UV photodegradable resin.

In addition, the sacrificial layer may be removed by wet etching or UV irradiation.

In addition, separation of the substrate from the conductive layer may be performed by removing the substrate by polishing or wet etching.

Another aspect of the present invention to achieve the above technical problem provides a method of manufacturing a laminated wafer level package. The manufacturing method includes preparing a substrate; Forming a conductive layer on the substrate; Forming a chip connection pad and an internal connection pad on the conductive layer; Forming a solder ball connected to the internal connection pad; Mounting a semiconductor chip to be connected to the chip connection pad; Forming a sealing member exposing the solder ball and sealing the semiconductor chip; Separating the substrate from the conductive layer; Etching the conductive layer to form a rearranged wiring layer; Forming external connection means on the rearrangement wiring layer; And stacking an electronic component electrically connected to the solder ball on the sealing member.

Here, the stack buffer unit may be formed to surround at least the connection portion between the solder ball and the electronic component.

In addition, the multilayer buffer unit may be formed on an entire surface between the electronic component and the sealing member.

In the laminated wafer level package of the present invention, a solder ball for interconnection of a component to be laminated is bonded to a conductive layer in advance, and is then generated during the lamination process by performing the semiconductor chip mounting step, rearranged wiring layer forming step, and lamination step. The occurrence of misalignment can be prevented, and the electrical contact reliability of the laminated electronic component can be improved.

In addition, the stacked wafer level package may reduce the process time and the process cost by performing both the stacking process and the packaging process of the chip on the wafer substrate.

In addition, the solder ball can be easily interconnected and the electronic components can be laminated, thereby simplifying the process.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings of a stacked wafer level package. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of the device may be exaggerated for convenience. Like numbers refer to like elements throughout.

1 is a cross-sectional view of a stacked wafer level package according to an embodiment of the invention.

Referring to FIG. 1, a stacked wafer level package according to an exemplary embodiment of the present invention may include a rearrangement wiring layer 111, an external connection means 190, a chip connection pad 130a, an internal connection pad 130b, and a semiconductor chip 160. ), The solder ball 140, the sealing member 170 and the electronic component 200.

The rearrangement wiring layer 111 rearranges the chip connection pad 130a and the internal connection pad 130b.

An insulating pattern 180 is disposed under the rearranged wiring layer 111. The insulating pattern 180 serves to protect the rearranged wiring layer 111 from the outside.

The insulating pattern 180 exposes a part of the rearranged wiring layer 111. An external connection unit 190 is bonded to the exposed rearranged wiring layer 111. That is, the external connection means 190 is electrically connected to the rearranged wiring layer 111. The laminated wafer level package may be electrically connected to an external signal device such as a printed circuit board by the external connection means 190. Examples of the external connection means 190 may be solder balls or metal bumps.

The chip connection pad 130a and the internal connection pad 130b may be disposed on the rearranged wiring layer 111. Here, the chip connection pad 130a and the internal connection pad 130b may be electrically connected to the rearranged wiring layer 111. Accordingly, the chip connection pad 130a and the internal connection pad 130b may be rearranged by the rearrangement wiring layer 111. The chip connection pad 130a and the internal connection pad 130b may be electrically separated from each other or may be connected to each other.

The semiconductor chip 160 may include a connection terminal 161 made of solder balls or metal bumps. The connection terminal 161 of the semiconductor chip 160 is electrically connected to the chip connection pad 130a. Thus, the semiconductor chip 160 may be mounted on the rearranged wiring layer 111. The mounting means 150 of the semiconductor chip 160 may be soldering, a conductive paste, a non-conductive paste (NCP), an anisotropic conductive film (ACF), or the like.

In addition, the stacked wafer level package according to the embodiment of the present invention, when the chip connection pad 130a and the semiconductor chip 160 are electrically connected by soldering, is not shown in the drawing, but at least the chip connection The apparatus may further include a buffer unit covering a connection portion between the pad 130a and the semiconductor chip 160. The buffer unit may be interposed between the semiconductor chip 160 and the insulating pattern 180 including the rearranged wiring layer 111. An example of a material for forming the buffer part may be an underfill material. The buffer part performs a buffer role and an electrical insulation function to absorb and relieve thermal stress, thereby improving electrical connection reliability between the semiconductor chip 160 and the chip connection pad 130a. In addition, the buffer unit may serve to adhere and fix the semiconductor chip 160 on the insulating pattern 180 including the rearranged wiring layer 110.

The solder ball 140 is directly bonded to the internal connection pad 130b. Here, the rearrangement wiring layer 111 and the electronic component 200 to be described later may be electrically connected to each other through the internal connection pad 130b.

The sealing member 170 seals the semiconductor chip 160 to protect the semiconductor chip 160 from an external environment. Here, the sealing member 170 exposes a part of the solder ball 140 for electrical connection between the solder ball 140 and the electronic component 200. In this case, the sealing member 170 may include a contact hole 171 for exposing the solder ball 140.

Electronic components 200 electrically connected to the solder balls 140 exposed by the contact holes 171 are stacked. Here, the solder ball 140 and the connection terminal 201 of the electronic component 200 may be electrically connected to each other by the connection member 195 filled in the contact hole 171, for example, a plating layer and a conductive paste. As a result, the electronic component 200 may receive an electrical signal from the outside through the solder ball 140.

Examples of the electronic component 200 may include additional semiconductor chips, modules, and packages. Here, the additional semiconductor chip may be the same type or different types as the semiconductor chip 160, but is not limited in the embodiment of the present invention. In addition, examples of the connection terminal 201 of the electronic component 200 may be solder balls, metal bumps, or the like.

In addition, although not shown in the drawing, at least a stack buffer part surrounding the connection portion between the solder ball 140 and the electronic component 200 may be further formed. That is, the stacked buffer part is interposed between the sealing member 170 and the electronic component 200. In this case, the laminated buffer part may reduce thermal stress of the solder ball 140 to improve electrical connection reliability. In addition, the multilayer buffer unit 310 may serve to fix the electronic component on the sealing member.

Therefore, in the embodiment of the present invention, as the interconnection between the electronic parts stacked through the solder balls electrically connected to the rearrangement layer is achieved, the electrical connection reliability between the stacked electronic parts can be ensured.

Hereinafter, referring to FIG. 2, the laminated wafer level package of the second embodiment will be described. In the second embodiment of the present invention, the same configuration as that of the stacked wafer level package according to the first embodiment described above except for the stacked buffer part is given the same reference numerals, and the first embodiment is given. Repeated descriptions will be omitted.

2 is a cross-sectional view of a stacked wafer level package according to a second embodiment of the present invention.

Referring to FIG. 2, a stacked wafer level package according to an exemplary embodiment of the present invention may include an insulating pattern disposed under the rearranged wiring layer 111 and the rearranged wiring layer 111 and exposing a portion of the rearranged wiring layer 111. 180, an external connection means 190 electrically connected to the exposed rearranged wiring layer 111, a chip connection pad 130a and an internal connection pad 130b electrically connected to the rearranged wiring layer 111. ), The semiconductor chip 160 electrically connected to the chip connection pad 130a and the solder ball 140 and the solder ball 140 electrically connected to the internal connection pad 130b. A sealing member 370 for exposing a portion of the 140 and sealing the semiconductor chip 160, and an electronic component stacked on the sealing member 370 and electrically connected to the exposed solder ball 140 ( 200).

The height of the sealing member 370 may be at least the same as or smaller than the solder ball 140, so that the solder ball 140 may be exposed from the sealing member 370. Here, the electronic component 200 may directly connect the connection terminal 201 and the solder ball 140 provided in the electronic component 200 to be electrically connected to the solder ball 140. Accordingly, the electronic component 200 may be electrically connected to the rearranged wiring layer 111 through the solder ball 140.

The electronic device 200 may further include a stack buffer 310 filled between the electronic component 200 and the sealing member 370. The multilayer buffer unit 310 may be formed of an underfill material. Here, the multilayer buffer unit 310 serves to improve electrical contact reliability between the electronic component 200 and the solder ball 140. Here, the stacked buffer unit 310 is illustrated as being filled in the entire surface between the electronic component 200 and the sealing member 370, but is not limited thereto. For example, the multilayer buffer unit 310 may be formed to surround only the connection portion between the solder ball 140 and the electronic component.

In the embodiment of the present invention, the stacking of the electronic component 200 is described as being directly bonded to the solder ball 140, but is not limited thereto. Anisotropic conductive film (ACF) and non-conductive paste (Non-Conductive) may be used. Paste; NCP).

Therefore, the stacked wafer level package according to the embodiment of the present invention has a height equal to or smaller than the height of the solder ball for connecting the electronic component on which the sealing member is laminated, thereby electrically connecting the solder ball and the electronic component through an easy process. You can connect.

In addition, the stacked wafer level package may include a stack buffer unit at a connection portion between the solder ball and the electronic component, thereby improving electrical reliability between the stacked electronic components.

3 to 18 are cross-sectional views illustrating a manufacturing process of a stacked wafer level package according to a third embodiment of the present invention.

Referring to FIG. 3, a substrate 100 is first provided to manufacture a stacked wafer level package.

The substrate 100 may be a wafer substrate used in a semiconductor process. Examples of the material of the substrate 100 may be silicon, ceramic, glass, and polymer.

The conductive layer 110 is formed on the substrate 100. In this case, the conductive layer 110 may be formed by laminating a metal foil. The embodiment of the present invention is not limited to the method of forming the conductive layer 110. Alternatively, the conductive layer 110 may be formed by depositing a metal. In addition, examples of the metal may be Cu, Au, W, Ni, Pb, Ti, and the like. The conductive layer 110 may be formed of a single film composed of a single species or a laminated film of two or more kinds.

Referring to FIG. 4, after the conductive layer 110 is formed, a first resist pattern 121 is formed on the conductive layer 110. In order to form the first resist pattern 121, a resist layer is first formed by coating a photosensitive resin on the conductive layer 110 or laminating a dry film resist (DFR). Thereafter, the first resist pattern 121 may be formed by performing an exposure and development process on the resist layer.

Referring to FIG. 5, the chip connection pad 130a and the internal connection pad (on the conductive layer 110 exposed by the first resist pattern 121 using the first resist pattern 121 as a mask) may be used. 130b).

The chip connection pad 130a and the internal connection pad 130b may be formed through a deposition process using a shadow mask. Alternatively, the chip connection pad 130a and the internal connection pad 130b may be formed by electroplating using the conductive layer 110 as a seed layer.

The chip connection pad 130a and the internal connection pad 130b may be made of metals such as Al and Cu. The chip connection pad 130a and the internal connection pad 130b may be formed of the same conductive material.

Referring to FIG. 6, the solder balls 140 are bonded to each other so as to be electrically connected to the internal connection pads 130b. The solder ball 140 may be formed through the reflow process after being disposed on the internal connection pad 130b by a method such as plating, ball placement, and stencil printing.

Thereafter, as shown in FIG. 7, the first resist pattern 121 is removed. Here, by the first resist pattern 121, the electrical defects caused by the solder ball 140 is bonded to another region can be prevented.

Referring to FIG. 8, after removing the first resist pattern 121, a mounting means 150, for example, an anisotropic conductive film, is disposed on the conductive layer 110 including the chip connection pad 130a. ACF) and a liquid non-conductive paste (NCP).

Referring to FIG. 9, as the semiconductor chip 160 is pressed onto the mounting means 150, the connection terminal 161 of the semiconductor chip 160 may be electrically connected to the chip connection pad 130a. Can be. Here, when the mounting means 150 is an anisotropic conductive film, the connection terminal 161 and the chip connection pad 130a of the semiconductor chip 160 may be electrically connected to each other by the anisotropic conductive film. In addition, when the mounting means 150 is a non-conductive paste, the mounting means 150 is not interposed between the connection terminal 161 of the semiconductor chip 160 and the chip connection pad 130a and contacts each other. It is disposed around the connection terminal 161 of the semiconductor chip 160 and the chip connection pad 130a, and serves to adhere and fix the semiconductor chip 160 on the conductive layer 110. . In this case, the non-conductive paste may serve as a buffer unit to improve electrical contact reliability between the semiconductor chip 160 and the conductive layer 110.

As another example of the mounting means 150 may be electrically connected to each other using soldering or conductive paste. Here, when the semiconductor chip 160 and the chip connection pad 130a are electrically connected by soldering, although not shown in the drawing, a connection portion between the semiconductor chip 160 and the chip connection pad 130a is formed. A covering buffer portion may be further formed. The buffer part may improve the fatigue life of the solder by providing an effect of releasing thermal stress applied to the solder due to a difference in thermal expansion coefficient between the semiconductor chip 160 and the substrate 100. Accordingly, electrical contact reliability between the semiconductor chip 160 and the chip connection pad 130a may be improved. In addition, the semiconductor chip 160 may be fixed on the conductive layer 110 by the buffer unit. The buffer unit may be formed by soldering and bonding the semiconductor chip 160 to the chip connection pad 130a and filling an underfill material between the conductive layer 110 and the semiconductor chip 160. For example, the underfill material may include an epoxy resin, a polyimide resin, a polyacrylate resin, a polyester resin, and a resin such as polybenzoxazole.

Referring to FIG. 10, after mounting the semiconductor chip 160, a sealing member 170 for sealing the semiconductor chip 160 is formed. Here, examples of the method of forming the sealing member 170 may be a transfer molding method, an injection molding method, a sprin printing method and a dispensing method. In addition, the sealing member 170 is formed of a resin, and may be, for example, an epoxy resin, a silicone resin, a fluororesin, an acrylic resin, or the like.

Referring to FIG. 11, after forming the sealing member 170, the substrate 100 is separated from the conductive layer 110. By separating the substrate 100, the substrate 100 may be polished or decomposed by a wet process.

As another method of separating the substrate 100, although not shown, a sacrificial layer is formed between the substrate 100 and the conductive layer 110, and then the sacrificial layer is wetted or irradiated with UV. By removing the substrate 100, the substrate 100 may be removed from the conductive layer 110. In this case, the sacrificial layer is formed on the substrate 100 before the conductive layer 110 is formed. Here, the sacrificial layer may be formed of any one of metal, silicon oxide, silicon nitride, and UV light decomposable resin.

Referring to FIG. 12, a second resist pattern 122 is formed below the exposed conductive layer 110 by removing the substrate 100. The second resist pattern 122 may form a resist layer by applying a photosensitive resin to the lower portion of the conductive layer 110 or laminating a dry film resist (DFR). Subsequently, the second resist pattern 122 may be formed by performing exposure and development processes on the resist layer.

Referring to FIG. 13, the conductive layer 110 is etched using the second resist pattern 122 as an etching mask to form the rearranged wiring layer 111. Thereafter, as shown in FIG. 14, the second resist pattern 122 is removed.

Therefore, after the solder ball 140 for interconnection with the electronic component 200 which will be described later is bonded in advance to the conductive layer 110 before the rearranged wiring layer 111 is formed, the rearranged wiring layer forming process and semiconductor chip mounting. By performing the process, the sealing member forming process, etc., it is possible to prevent the solder ball 140 from connecting poorly with the rearranged wiring layer 111.

Referring to FIG. 15, an insulating pattern 180 is formed on the rearranged wiring layer 111. The insulating pattern 180 exposes a part of the rearranged wiring layer 111. The insulating pattern 180 may be formed through an exposure and development process after forming an insulating layer.

Referring to FIG. 16, external connection means 190 is formed on the rearranged wiring layer 111 exposed by the insulating pattern 180. Here, examples of the external connection means 190 may be a solder ball, a metal bump, or the like.

Referring to FIG. 17, a contact hole 171 for exposing the solder ball 140 is formed in the sealing member 170. As an example of a method of forming the contact hole 171, a mechanical drill method, a laser drill method, an etching method, or the like may be used.

Referring to FIG. 18, an electronic component 200 electrically connected to the solder balls 140 exposed by the contact hole 171 is stacked. Here, examples of the electronic component 200 may be additional semiconductor chips, modules, packages, and the like. Here, the additional semiconductor chip may be the same kind as or different from the semiconductor chip, but is not limited to the exemplary embodiment of the present invention. Here, after filling the contact member 195, for example a plating layer or a conductive paste in the contact hole 171, by connecting the connection member 195 and the connecting means of the electronic component, the electronic component and the solder ball Can be electrically connected.

In addition, although not shown in the drawing, at least a stack buffer part surrounding the connection portion between the solder ball 140 and the electronic component 200 may be further formed. That is, the stacked buffer part is interposed between the sealing member 170 and the electronic component 200. In this case, the laminated buffer part may reduce thermal stress of the solder ball 140 to improve electrical connection reliability. In addition, the multilayer buffer unit may serve to fix the electronic component on the sealing member.

Therefore, in the method of manufacturing a stacked wafer level package according to an embodiment of the present invention, after soldering the solder balls for interconnection between the stacked parts to the conductive layer for forming the rearrangement wiring layer, the rearrangement wiring layer forming process By performing the semiconductor chip mounting process and the lamination process, the misalignment problem occurring in the lamination process can be improved.

Hereinafter, referring to FIGS. 19 and 20, a manufacturing method of the laminated wafer level package of the fourth embodiment will be described. In the fourth embodiment of the present invention, except that the buffer portion is formed, it is manufactured by the same method as the manufacturing process of the laminated wafer level package according to the third embodiment described above, and the same reference numerals will be given to the same configuration. . In addition, in the fourth embodiment, the description repeated with the third embodiment will be omitted.

19 and 20 are cross-sectional views illustrating a manufacturing process of a stacked wafer level package according to a fourth embodiment of the present invention.

Referring to FIG. 19, in order to manufacture a stacked wafer level package, a substrate 100 is first prepared. Thereafter, after forming the conductive layer 110 on the substrate 100, the chip connection pad 130a and the internal connection pad 130b are formed on the conductive layer 110. Thereafter, the solder ball 140 is formed to be connected to the internal connection pad 130b and the semiconductor chip 160 is mounted to be connected to the chip connection pad 130a. Thereafter, a sealing member 370 for sealing the solder ball 140 and the semiconductor chip 160 is formed.

Here, the sealing member 370 is formed to expose the solder ball 140. That is, the height of the sealing member 370 may be formed equal to or smaller than the height of the solder ball 140.

Thereafter, the substrate 100 is separated from the conductive layer 110, and then the rearranged wiring layer 111 is formed by etching the conductive layer 110. Subsequently, after the insulating pattern 180 exposing a part of the rearranged wiring layer 111 is formed, an external connection means 190 is formed in the exposed rearranged wiring layer 111.

Thereafter, the electronic component 200 electrically connected to the solder ball 140 is stacked on the sealing member 370. Here, the solder ball 140 is not exposed by a separate contact hole, but has the same height or the same height as the surface of the sealing member 370, so that the solder ball 140 without filling a separate connection member. ) May directly contact the connection terminal 201 of the electronic component 200.

A stack buffer part 310 may be further formed to cover a connection portion between the solder ball 140 and the electronic component 200. The stack buffer 310 may be formed by filling an underfill material between the sealing member 370 and the electronic component 200. The underfill material may include a resin such as an epoxy resin, a polyimide resin, a polyacrylate resin, a polyester resin, and a polybenzoxazole.

The multilayer buffer unit 310 may improve the fatigue life of the solder ball 140 by providing an effect of releasing thermal stress applied to the solder ball 140. Accordingly, electrical contact reliability between the solder ball 140 and the electronic component 200 may be improved. In addition, the electronic component 200 may be fixed on the sealing member 370 by the stack buffer 310.

In the embodiment of the present invention, the stacking of the electronic component 200 is described as being directly bonded to the solder ball 140, but is not limited thereto. Anisotropic conductive film (ACF) and non-conductive paste (Non-Conductive) may be used. Paste; NCP).

Therefore, when the sealing member is formed in the embodiment of the present invention, since the solder ball is formed to be exposed, the contact hole forming process for exposing the solder ball to the sealing member does not have to be performed separately, thereby simplifying the process. .

1 is a cross-sectional view of a stacked wafer level package according to an embodiment of the invention.

2 is a cross-sectional view of a stacked wafer level package according to a second embodiment of the present invention.

3 to 18 are cross-sectional views illustrating a manufacturing process of a stacked wafer level package according to a third embodiment of the present invention.

19 and 20 are cross-sectional views illustrating a manufacturing process of a stacked wafer level package according to a fourth embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: substrate 110: conductive layer

111: rearranged wiring layer 130a: chip connection pad

130b: internal connection pad 140: solder ball

150: mounting means 160: semiconductor chip

170, 370: sealing member 200: electronic components

310: stacked buffer portion

Claims (17)

Rearranged wiring layer; An external connection means disposed under the rearrangement wiring layer and electrically connected to the rearrangement wiring layer; A chip connection pad and an internal connection pad disposed on the rearrangement wiring layer and electrically connected to the rearrangement wiring layer; A semiconductor chip mounted on the rearrangement wiring layer to be connected to the chip connection pad; A solder ball connected to the internal connection pad; A sealing member exposing a portion of the solder ball and sealing the semiconductor chip; And An electronic component stacked on the sealing member and electrically connected to the exposed solder balls; Laminated wafer level package comprising a. The method of claim 1, The electronic component has a stacked wafer level package having any one of a semiconductor chip, a module, and a package. The method of claim 1, And a buffer unit covering at least a connection portion between the chip connection pad and the semiconductor chip. The method of claim 1, The stacked wafer level package further comprises a stacked buffer unit filled between the electronic component and the sealing member. The method of claim 1, The external connection means is a laminated wafer level package of any one of metal bumps and solder balls. The method of claim 1, The semiconductor chip may be mounted using any one of soldering, conductive paste, non-conductive paste (NCP), and anisotropic conductive film (ACF). Preparing a substrate; Forming a conductive layer on the substrate; Forming a chip connection pad and an internal connection pad on the conductive layer; Forming a solder ball connected to the internal connection pad; Mounting a semiconductor chip on the conductive layer so as to be connected to the chip connection pad; Forming a sealing member for sealing the solder ball and the semiconductor chip; Separating the substrate from the conductive layer; Etching the conductive layer to form a rearranged wiring layer; Forming external connection means on the rearrangement wiring layer; Forming a contact hole exposing the solder ball to the sealing member; And Stacking electronic components to be electrically connected to the solder balls exposed through the contact holes; Method of manufacturing a laminated wafer level package comprising a. The method of claim 7, wherein The method of manufacturing a stacked wafer level package using any one of soldering, a conductive paste, a non-conductive paste (NCP), and an anisotropic conductive film (ACF) is connected between the semiconductor chip and the chip connection pad. . The method of claim 7, wherein And a buffer portion covering at least a connection portion between the chip connection pad and the semiconductor chip. The method of claim 7, wherein A method of manufacturing a laminated wafer level package further comprising forming a stacked buffer portion surrounding at least a connection portion between the solder ball and the electronic component. The method of claim 7, wherein The substrate further includes a sacrificial layer on its upper surface, Separation of the substrate from the conductive layer is performed by removing the sacrificial layer. The method of claim 11, And the sacrificial layer is formed of any one of metal, silicon oxide, silicon nitride, and UV light decomposable resin. The method of claim 11, And the sacrificial layer is removed by wet etching or UV irradiation. The method of claim 7, wherein Separation of the substrate from the conductive layer is performed by removing the substrate by polishing or wet etching. Preparing a substrate; Forming a conductive layer on the substrate; Forming a chip connection pad and an internal connection pad on the conductive layer; Forming a solder ball connected to the internal connection pad; Mounting a semiconductor chip to be connected to the chip connection pad; Forming a sealing member exposing the solder ball and sealing the semiconductor chip; Separating the substrate from the conductive layer; Etching the conductive layer to form a rearranged wiring layer; Forming external connection means on the rearrangement wiring layer; And Stacking electronic components electrically connected to the solder balls on the sealing member; Method of manufacturing a laminated wafer level package comprising a. The method of claim 15, A method of manufacturing a laminated wafer level package further comprising forming a stacked buffer portion surrounding at least a connection portion between the solder ball and the electronic component. The method of claim 15, And the stacked buffer part is formed on an entire surface of the electronic component and the sealing member.

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