KR20100050010A

KR20100050010A - Powerup signal generating circuit

Info

Publication number: KR20100050010A
Application number: KR1020080109086A
Authority: KR
Inventors: 김재훈
Original assignee: 주식회사 하이닉스반도체
Priority date: 2008-11-04
Filing date: 2008-11-04
Publication date: 2010-05-13

Abstract

PURPOSE: A power-up signal generating circuit is provided to reduce power consumption by deactivating a power-up signal generating unit according to a termination signal generated at a high level. CONSTITUTION: A power-up signal generating unit(2) generates a first power-up signal by detecting an exterior voltage. A latch unit(3) generates a second power-up signal by maintaining the first power-up signal. A delay unit(4) generates a termination signal by delaying the first power-up signal in a prescribed section. The power up signal generating unit stops the generation of the first power-up signal when the termination signal is enabled.

Description

Power-up signal generation circuit {POWERUP SIGNAL GENERATING CIRCUIT}

The present invention relates to a semiconductor memory device, and more particularly to a power-up signal generation circuit that can reduce power consumption.

In general, the power-up signal generation circuit in the semiconductor device refers to a circuit that is responsible for initializing the semiconductor device. In order to operate the semiconductor device, an external voltage VDD is externally supplied. The voltage level of the external voltage VDD starts from 0 [V] and rises to a target voltage level with a constant slope. At this time, when all the circuits of the semiconductor device are directly applied with the external voltage VDD, a malfunction occurs due to the influence of the rising external voltage. Therefore, in order to prevent such chip malfunction, the semiconductor device includes a power-up signal generating circuit to enable a power-up signal so that each circuit after the external voltage VDD reaches a stable voltage level. To be supplied. The semiconductor device is initialized by powering up such an operation.

1 illustrates a configuration of a power up signal generation circuit according to the prior art.

As shown, the power-up signal generation circuit according to the prior art is composed of resistors R10 and R12, NMOS transistors N10 and N12, PMOS transistor P10 and inverters IV10 and IV12. The power-up signal generation circuit having such a configuration detects the external voltage VDD and generates a power-up signal PWRUP having a high level when the external voltage VDD is less than or equal to a predetermined level, and the external voltage VDD is preset. If it rises above the level, a power-up signal PWRUP that is low level is generated. That is, the power-up signal generation circuit is a power-up signal PWRUP having a high level in a period where power is supplied to the semiconductor memory device and the external voltage VDD rises to a predetermined level (hereinafter referred to as a 'power-up period'). After the power-up period ends, a power-up signal PWRUP that transitions to a low level is generated.

However, the conventional power-up signal generation circuit has a current path including resistance elements R10 and R12, NMOS transistors N10 and N12, and PMOS transistor P10 even after the power-up period ends. There is a problem that a lot of power loss occurs.

The present invention discloses a power-up signal generation circuit that can cut off a current path where power consumption occurs after the power-up period ends, thereby preventing unnecessary power consumption.

To this end, the present invention is a power-up signal generation unit for generating a first power-up signal by sensing an external voltage; A latch unit for latching the first power up signal to generate a second power up signal; And a delay unit generating a termination signal by delaying the first power-up signal by a predetermined interval, wherein the power-up signal generator stops the first power-up signal generating operation when the termination signal is enabled. Provide a generation circuit.

In the present invention, the power-up signal generation unit voltage division unit for dividing the external voltage in response to the end signal; A driving unit driving a first node by an output signal of the voltage distribution unit in response to the termination signal; And a buffer unit configured to buffer and output a signal of the first node in response to the end signal.

In the present invention, the voltage divider is connected between the external voltage and the second node, the switching element is turned on in response to the termination signal; A first resistance element connected between the second node and a third node; And a second resistance element connected between the third node and a ground voltage.

In the present invention, the second resistance element is preferably a MOS transistor turned on in response to the external voltage.

In the present invention, the driving unit is connected between the external voltage and the second node, the pull-up element for driving up the second node in response to the output signal of the voltage divider; A first resistance element connected between the second node and the first node; A pull-up element connected between the first node and a third node to pull down the first node in response to an output signal of the voltage divider; And a switch device connected between the third node and a ground voltage and turned on in response to the termination signal.

In the present invention, the buffer unit includes a first buffer for buffering the output signal of the driver; A first driving element driving an output node of the first buffer in response to the end signal; A second buffer for buffering the output signal of the first buffer; And a second driving device for driving the output node of the second buffer in response to the end signal.

In the present invention, the first driving device is a MOS transistor connected between the output node of the first buffer and the ground voltage, and pull-down driving the output node of the first buffer in response to the end signal.

In the present invention, the second driving device is a MOS transistor connected between the output node of the second buffer and the external voltage, and pull-up driving the output node of the second buffer in response to the end signal.

Hereinafter, the present invention will be described in more detail with reference to Examples. These embodiments are only for illustrating the present invention, and the scope of rights of the present invention is not limited by these embodiments.

2 is a block diagram showing the configuration of a power-up signal generation circuit according to an embodiment of the present invention.

As shown in Fig. 2, the power-up signal generation circuit according to the present embodiment includes a power-up signal generation section 2, a latch section 3, and a delay section 4.

As shown in FIG. 3, the power-up signal generator 2 includes a voltage divider 20, a driver 22, and a buffer 24. The voltage divider 20 is connected between the external voltage VDD and the node nd20 to operate as a switch element turned on in response to the termination signal OFF, and the node nd20 and the node ( The resistor R20 is connected between nd21 and the NMOS transistor N20 is connected between the node nd21 and the ground voltage VSS to operate as a resistor. The NMOS transistor N20 is turned on by the external voltage VDD to operate as a resistor having a turn-on resistance value.

The driver 22 is connected between the external voltage VDD and the node nd22 to pull up and drive the node nd22 in response to the signal of the node nd21, the node nd22 and the node ( NMOS transistor N22 connected between node nd23, node nd23 and node nd24 connected to node nd21 to pull-down node nd23 in response to a signal from node nd21, and a node; and an NMOS transistor N24 connected between the nd24 and the ground voltage VSS and turned on in response to an inversion signal of the termination signal OFF.

The buffer unit 24 includes an inverter IV21 for inverting and buffering the signal of the node nd23, an inverter IV22 for inverting and buffering the signal of the node nd25 and outputting the first power-up signal PWRUP1, and a node. An NMOS transistor N26 connected between an nd25 and a ground voltage VSS to pull down the node nd25 in response to an end signal OFF, and connected between an external voltage VDD and a node nd26. And a PMOS transistor P24 that pulls up the node nd26 in response to an inversion signal of the end signal OFF.

As shown in FIG. 4, the latch unit 3 includes inverters IV30, IV31, and IV32 to latch the first power-up signal PWRUP1 to generate a second power-up signal PWRUP2. Here, the second power-up signal PWRUP2 is a signal used for power-up of the semiconductor memory device. Like the first power-up signal PWRUP1, the second power-up signal PWRUP2 is high level in the power-up period and after the power-up period ends, A signal that transitions to a low level.

As shown in FIG. 5, the delay unit 4 includes inverters IV40-IV42, PMOS transistors P40 and P41 and NMOS transistors N40 and N41 that operate as charge holding devices.

Here, the end signal OFF is a signal initialized to a low level. Accordingly, the PMOS transistor P20 and the NMOS transistor N24 of the power-up signal generator 2 are turned on by the low level end signal OFF to activate the voltage divider 20 and the driver 22. In addition, the NMOS transistor N26 and the PMOS transistor P24 are turned off by the low-level end signal OFF, so that the inverters IV20 and IV21 buffer the signal of the node nd23 so that the first power-up signal ( PWRUP1).

The operation of the power-up signal generation circuit configured as described above is as follows.

When power is applied to the semiconductor memory device, the power-up signal generator 2 is activated by the end signal OFF initialized to the low level to generate the first power-up signal PWRUP1. That is, the power-up signal generator 2 generates the first power-up signal PWRUP1 having a high level in a power-up period in which the external voltage VDD does not rise to a predetermined level. This is because the node nd21 is at the low level due to the low level external voltage VDD in the power-up period, so that the PMOS transistor P22 of the driver 22 is turned on to drive the node nd23 up. When the first power-up signal PWRUP1 is at a high level, the end signal OFF output from the delay unit 4 maintains a low level.

Thereafter, when the external voltage VDD rises larger than the predetermined level, the first power-up signal PWRUP1 transitions to a low level. That is, since the node nd21 is at the high level due to the external voltage VDD having the increased level, the NMOS transistor N22 of the driving unit is turned on to pull down the node nd23 to lower the first power-up signal PWRUP1. Transition to level.

When the first power-up signal PWRUP1 transitions to the low level, the delay unit 4 generates a high level end signal OFF. The high level end signal OFF turns off the PMOS transistor P20 and the NMOS transistor N24 of the power-up signal generator 2 to deactivate the voltage divider 20 and the driver 22. In addition, the high level end signal OFF turns on the NMOS transistor N26 and the PMOS transistor P24 to deactivate the buffering operations of the inverters IV21 and IV22.

In this way, the power-up signal generation circuit 2 according to the present embodiment generates a power-up signal generation section 2 by an end signal OFF generated at a high level after the delay section of the delay section 4 elapses after the power-up section ends. By deactivating), power consumption can be reduced after the power-up period ends.

1 is a circuit diagram of a power up signal generation circuit according to the prior art.

FIG. 3 is a circuit diagram of a power-up signal generator included in the power-up signal generator shown in FIG. 2.

4 is a circuit diagram of a latch unit included in the power-up signal generation circuit shown in FIG. 2.

FIG. 5 is a circuit diagram of a delay unit included in the power-up signal generation circuit shown in FIG. 2.

2: power-up signal generator 20: voltage divider

22: drive unit 24: buffer unit

3: latch portion 4: delay portion

Claims

A power-up signal generator configured to detect an external voltage and generate a first power-up signal;

A latch unit for latching the first power up signal to generate a second power up signal; And

A delay unit configured to generate a termination signal by delaying the first power-up signal by a predetermined period;

And the power-up signal generator stops the first power-up signal generating operation when the end signal is enabled.

The method of claim 1, wherein the power-up signal generation unit

A voltage divider configured to divide and output the external voltage in response to the end signal;

A driving unit driving a first node by an output signal of the voltage distribution unit in response to the termination signal; And

And a buffer unit configured to buffer and output a signal of the first node in response to the end signal.

The method of claim 2, wherein the voltage divider is

A switch element connected between the external voltage and a second node and turned on in response to the termination signal;

A first resistance element connected between the second node and a third node; And

And a second resistor connected between the third node and a ground voltage.

4. The power up signal generation circuit according to claim 3, wherein the second resistor element is a MOS transistor turned on in response to the external voltage.

The method of claim 2, wherein the driving unit

A pull-up element connected between the external voltage and a second node to pull-up the second node in response to an output signal of the voltage divider;

A first resistance element connected between the second node and the first node;

A pull-up element connected between the first node and a third node to pull down the first node in response to an output signal of the voltage divider; And

And a switch element connected between the third node and a ground voltage and turned on in response to the termination signal.

The method of claim 2, wherein the buffer unit

A first buffer for buffering the output signal of the driver;

A first driving element driving an output node of the first buffer in response to the end signal;

A second buffer for buffering the output signal of the first buffer; And

And a second driving device for driving an output node of the second buffer in response to the end signal.

The power-up signal of claim 6, wherein the first driving device is a MOS transistor connected between an output node of the first buffer and a ground voltage to pull down the output node of the first buffer in response to the termination signal. Generating circuit.

The power up device of claim 6, wherein the second driving device is a MOS transistor connected between an output node of the second buffer and the external voltage to pull up the output node of the second buffer in response to the termination signal. Signal generation circuit.