KR20100049564A - 3d r/w cell with reduced reverse leakage and method of making thereof - Google Patents

3d r/w cell with reduced reverse leakage and method of making thereof Download PDF

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KR20100049564A
KR20100049564A KR1020107001752A KR20107001752A KR20100049564A KR 20100049564 A KR20100049564 A KR 20100049564A KR 1020107001752 A KR1020107001752 A KR 1020107001752A KR 20107001752 A KR20107001752 A KR 20107001752A KR 20100049564 A KR20100049564 A KR 20100049564A
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South Korea
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read
switching element
element
write switching
resistivity state
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KR1020107001752A
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Korean (ko)
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탄메이 쿠마르
크리스토퍼 제이. 페티
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쌘디스크 3디 엘엘씨
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Priority to US11/819,989 priority Critical patent/US7759666B2/en
Priority to US11/819,989 priority
Priority to US11/819,895 priority
Priority to US11/819,895 priority patent/US7800939B2/en
Application filed by 쌘디스크 3디 엘엘씨 filed Critical 쌘디스크 3디 엘엘씨
Publication of KR20100049564A publication Critical patent/KR20100049564A/en

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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/24Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, e.g. resistance switching non-volatile memory structures
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30Resistive cell, memory material aspects
    • G11C2213/33Material including silicon
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70Resistive array aspects
    • G11C2213/72Array wherein the access device being a diode

Abstract

The nonvolatile memory device includes a semiconductor diode steering element and a semiconductor read / write switching element.

Description

3D R / W CELL WITH REDUCED RELEASE AND METHODS OF MANUFACTURING THEREOF

Cross Reference of Related Patent Application

This application claims the benefit of US patent applications Ser. Nos. 11 / 819,895 and 11 / 819,989, which are incorporated herein by reference and filed June 29, 2007.

The present invention relates to a nonvolatile memory device and a method of manufacturing the device.

Nonvolatile memory arrays retain their data even when the device is powered off. In one-time programmable arrays, each memory cell may be formed in an initial unprogrammed state and transitioned to a programmed state. This change is permanent and these cells cannot be erased. In other types of memories, memory cells are erasable and can be rewritten many times.

In addition, the cells may differ in the number of data states each cell can achieve. The data state can be stored by changing certain characteristics of the cell that can be detected, such as, for example, the current flowing through the cell under a given applied voltage or the threshold voltage of a transistor in the cell. The data state is a distinct value of a cell, such as data '0' or data '1'.

Some solutions for achieving erasable or multi-state cells are complex. For example, floating gate and SONOS memory cells operate by storing charge, where the presence, absence, or amount of charge changes the transistor threshold voltage. These memory cells are three-terminal devices that are relatively difficult to manufacture and operate with the very small dimensions required for competitiveness in modern integrated circuits.

Other memory cells operate by changing the resistivity of relatively unusual materials such as chalcogenides. Chalcogenides are difficult to work with most semiconductor manufacturing facilities and can pose challenges at these facilities.

Substantial advantages will be provided by non-volatile memory arrays having erasable or multi-state memory cells formed using conventional semiconductor materials of a structure that easily shrinks to small size.

One embodiment of the invention provides a nonvolatile memory device comprising a semiconductor diode steering element and a semiconductor read / write switching element.

Yet another embodiment of the present invention includes a semiconductor diode steering element; Semiconductor resistor read / write switching elements; At least one conductive layer positioned between the steering element and the read / write switching element; A first electrode in electrical contact with the steering element; And a second electrode in electrical contact with the read / write switching element. The read / write switching element, the at least one conductive layer and the steering element are arranged in series with pillars between the first electrode and the second electrode.

Yet another embodiment of the present invention includes a semiconductor diode steering element; Semiconductor read / write switching elements; At least one conductive layer positioned between the steering element and the read / write switching element; And means for switching the read / write switching element from a first resistivity state to a second resistivity state that is different from the first resistivity state and for switching the read / write switching element from the second resistivity state to the first resistivity state. It provides a nonvolatile memory device comprising a.

Each of the aspects and embodiments described herein can be used alone or in combination with each other. Preferred aspects and embodiments will now be described with reference to the accompanying drawings.

The present invention has the effect of providing a nonvolatile memory device and a method of manufacturing the device.

1 is a circuit diagram illustrating the need for electrical isolation between memory cells in a memory array.
2 and 6 are perspective views of memory cells formed in accordance with a preferred embodiment of the present invention.
3 is a perspective view of a portion of a memory level that includes the memory cell of FIG.
4A-4D are side cross-sectional views illustrating steps in the formation of memory levels formed in accordance with an embodiment of the invention.
5A-5D are schematic side cross-sectional views illustrating alternative diode configurations in accordance with an embodiment of the present invention.

It is known that the resistance of a resistor formed of doped polycrystalline silicon, or polysilicon, can be trimmed and regulated between stable resistance states by applying electrical pulses. These trimable resistors have been used as devices in integrated circuits.

However, typically no trimmable polysilicon resistors are used to store data states in non-volatile memory cells. Fabricating polysilicon resistors of one memory array presents challenges. If resistors are used as memory cells in a large intersection array, there will be undesirable leakage through the semi-selected and unselected cells throughout the array when voltage is applied to one selected cell. For example, going to FIG. 1, assume that a voltage is applied between bitline B and wordline A to set, reset, or sense the selected cell S. Current is intended to flow through the selected cell S. However, alternative paths may allow some leakage current to flow between bitline B and wordline A, for example, through unselected cells U1, U2, U3. There may be many such alternative paths.

In one embodiment of the invention, leakage current can be greatly reduced by forming each memory cell as a two terminal device comprising a diode and a resistor. Diodes have a non-linear I-V characteristic, which allows very little current flow below the turn-on voltage and considerably high current flow above the turn-on voltage. In general, a diode acts like one-way valves that more easily pass current in one direction than the other. Accordingly, unbiased paths (such as the U-U2-U3 sneak path in FIG. 1) along the unintentional paths, as long as biasing schemes are selected to ensure that forward current above the turn-on voltage is only applied to the selected cell only. Leakage current can be greatly reduced.

In an embodiment of the present invention, by applying suitable electrical pulses, the diode steering element and the semiconductor resistor, which function as a memory element formed of a semiconductor material, for example a read / write switching element, exhibit two or more stable resistivity states. Can be achieved. The switching elements are located in series, but are preferably separated from the diode steering element. Preferably, the switching element is separated from the steering element by one or more conductive layers located between the switching element and the steering element, such as by a metal (Ti, W, etc.), metal silicide or titanium nitride layer. The switching element, steering element and conductive isolation layer are arranged in series to form a nonvolatile memory cell. The switching element preferably comprises an amorphous, polycrystalline or combined amorphous and polycrystalline Group IV semiconductor resistor. However, other switching elements such as high resistivity diodes may be used. The steering element preferably comprises a crystallized low resistivity polycrystalline group IV semiconductor diode.

The semiconductor resistor material may be converted from the initial first resistivity state to another resistivity state, and then, upon application of a suitable electrical pulse, may return to the first resistivity state. For example, the first state may be a higher resistivity state than the second state. Alternatively, the second state may be a lower state than the first resistivity state. The memory cell may have two or more data states and may be programmable or rewritable once.

As mentioned, the inclusion of a diode between the conductors in the memory cell makes it possible to form a high density junction memory array. In a preferred embodiment of the present invention, the polycrystalline and / or amorphous semiconductor memory device is formed of discrete diodes and resistors in series.

2 illustrates a memory cell 2 formed in accordance with a preferred embodiment of the present invention. The lower conductor 12 is formed of a conductive material such as tungsten, for example, and extends in the first direction. Barriers and adhesion layers may be included in the bottom conductor 12. The memory cell 2 contains a polycrystalline semiconductor diode 4. The diode 4 preferably has a lower lightly doped n-type region, an intentionally undoped intrinsic region, and an upper heavily doped p-type region, although the orientation of the diode can be reversed. This diode will be referred to as a p-i-n diode, regardless of its orientation. The memory cell contains one or more conductive "decoupler" layers 6, and an amorphous and / or polycrystalline semiconductor resistor 8. The order of the elements in the cell 2 may be reversed, the resistor 8 may be located above the bottom of the cell and the diode 4 may be located above the top of the cell. In addition, the cell 2 may be positioned horizontally rather than vertically with respect to the substrate. The upper conductor 16 may be formed of the same method and the same material as the lower conductor 12 and extends in a second direction different from the first direction. The polycrystalline semiconductor diode 4 is disposed vertically between the lower conductor 12 and the upper conductor 16. The polycrystalline semiconductor diode 4 is preferably formed in a low resistivity state. The resistor 8 is preferably not necessarily formed in a high resistivity state. This memory cell can be formed on a suitable substrate, for example on a single crystal silicon wafer. 3 shows a portion of the memory level of such devices formed of an intersection array, where the cell 2 is disposed between the lower conductors 12 and the upper conductors 16. As shown in Figures 2 and 3, the diodes and resistors preferably have a substantially cylindrical shape. A plurality of memory levels can be stacked over the substrate to form a high density monolithic three dimensional memory array.

The memory cell 2 preferably does not include any additional active device or capacitor, such as a transistor. However, if desired, the memory cell 2 may also include an optional passive device, such as a fuse, antifuse, charge storage material, or phase change material. The memory cell may include an insulating material surrounding the diode and the resistor, and other optional layers, as described below.

In this discussion, regions of intentionally undoped semiconductor material are described as intrinsic regions. However, those skilled in the art will appreciate that the intrinsic region may actually comprise low concentration p-type or n-type dopants. Dopants may diffuse from neighboring regions to intrinsic regions, or may be present in the deposition chamber during deposition due to contamination from previous deposition. It will also be appreciated that the deposited intrinsic semiconductor material (such as silicon) may contain defects that behave as if they are slightly n-doped. The use of the term "intrinsic" to describe silicon, germanium, or silicon-germanium alloy, or any other semiconductor material does not mean that this region contains no dopant or that the region is completely electrically neutral.

The memory cell includes a read / write memory cell, such as a rewritable memory cell. The resistor 8 acts as a read / write element of the memory cell by switching from the first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias (ie, pulse) as described in detail below. do.

In this discussion, the transition from a high resistivity unprogrammed state to a low resistivity programmed state is referred to as a set transition, which is affected by a set current, or a set voltage, or a set pulse, and a low resistivity programmed state. The reverse transition from the high resistivity to the unprogrammed state will be referred to as a reset transition, which is affected by a reset current, or a reset voltage, or a reset pulse. The high resistivity unprogrammed state corresponds to the "1" memory state, and the low resistivity program state corresponds to the "0" memory state.

The resistivity of the doped polycrystalline or monocrystalline semiconductor material, for example silicon, can be changed between stable states by applying suitable electrical pulses. Generally, a set pulse applied to a diode under forward bias sufficient to transition the semiconductor material of the resistor from a given resistivity state to a low resistivity state results in a corresponding reset pulse (switching the same semiconductor material from a low resistivity state to a high resistivity state). It will have a lower voltage amplitude and a longer pulse width than the reset pulse.

By selecting suitable voltages, a set or reset of the semiconductor material constituting the resistor can be achieved without switching the resistivity state of the diode. Preferably, current flows in the forward direction (ie with a forward bias applied) through the diode 4 in both the set and reset transitions of the resistor 8. One or more conventional driver circuits connected to the electrodes 12, 16 may be used to apply electrical pulse (s) to the read / write conversion resistor element 8 to program and read the memory cell 2.

Thus, in use, the read / write switching resistor element 8 of the memory cell 2 switches from the first resistivity state to a second resistivity state different from the first resistivity state in response to an applied electrical pulse. If desired, the application of the second electrical pulse will cause the read / write switching resistor element 8 to transition from the second resistivity state back to the first resistivity state and / or to a third resistivity state different from the first and second resistivity states. Can be. However, the diode steering element 4 does not switch from the first resistivity state to the second resistivity state in response to the applied electric pulse. For example, the diode steering element 4 may be formed in a low resistivity state that does not change in response to an applied electric pulse, while the read / write switching resistor element 8 is in a high resistivity state that changes in response to an applied electric pulse. Is formed.

As will be described in detail below, the memory cell comprises a metal silicide layer, such as a titanium silicide, titanium germanide or titanium silicide-germanide layer, having a C49 phase in contact with the diode 4. The silicide layer acts as a crystallization template for the semiconductor diode 4 such that the diode is manufactured in a low resistivity state. Without wishing to be bound by any theory, it is believed that the low resistivity of the diode is the result of the large grain size of the polycrystalline semiconductor material crystallized in contact with the crystallization template. It is contemplated that a diode formed in a low resistivity state, for example by contact with a silicide template and crystallized, will not transition to a high resistivity state in response to the application of forward bias to the diode. In contrast, the resistor 8 is preferably not formed in contact with the silicide template and is formed in a relatively high resistivity state. Thus, the resistor 8 can be switched to a low resistivity state by the application of forward bias to the diodes and resistors arranged in series.

US Patent Application No. 11 / 148,530 to Herner et al., Filed June 8, 2006, "Nonvolatile Memory Cell Operating by Increasing Order in Polycrystalline Semiconductor Material," and "Memory Cell Comprising a, filed September 29, 2004." Herner's U.S. Patent Application 10 / 954,510, entitled "Semiconductor Junction Diode Crystallized Adjacent to a Siliicide", is the assignee of the present invention and is incorporated herein by reference, the crystallization of polysilicon adjacent to a suitable silicide Describe the influence on the characteristics. Some metal silicides, such as cobalt silicide and titanium silicide, have a lattice structure very close to that of silicon. When amorphous or microcrystalline silicon is crystallized in contact with one of these silicides, the crystal lattice of the silicide provides a template to the silicon during crystallization. The resulting polysilicon will be very ordered and there will be relatively few defects. This high quality polysilicon becomes relatively very conductive when formed when doped with a conductivity enhancing dopant.

After the application of the changeover pulse, a smaller read pulse, for example 1.5 to 2 volts, is applied and a current called the read current flowing through the diode and resistor at the read voltage is measured. As the voltage of the switching pulse is increased in subsequent pulses, the subsequent read current changes at a given read voltage. Accordingly, the distinct data states of the memory cell of embodiments of the present invention are distinguished by detecting the current flow through the memory cell (between the upper conductor 16 and the lower conductor 12) when a read voltage is applied. It corresponds to the resistivity states of the polycrystalline or microcrystalline semiconductor material constituting the resistor. Preferably, there is at least a twofold difference between the read current flowing in any one distinct data state and the different distinct data states so that the difference between states can be easily detected. The read current through the memory cell is greater in the low resistivity resistor set state than in the high resistivity resistor reset state. The memory cell may be used as a single programmable cell or a rewritable memory cell, and may have two, three, four, or more distinct data states. A cell may transition in any order from one of its data states to another of its data states. Examples of writing, reading, and erasing memory cells are described in US Application No. 11 / 496,986, filed Jul. 31, 2006, and 2007, which is part of US Application No. 11 / 237,167, filed September 28, 2005. No. 11 / 693,845, filed Mar. 30, all of which are incorporated herein by reference in their entirety.

So far, this discussion has described switching memory cells between two different data states by applying a suitable electrical pulse to convert the semiconductor material of the resistor from one resistivity state to another. In fact, these set and reset steps can be an iterative process. As described, the difference between current flows during readout in neighboring data states is preferably at least twice, and in many embodiments, for each data state separated by 3, 5, 10, or more times. It may be desirable to set the current range. In some cases, however, after application of an electrical pulse, the read current may not be in the desired range, ie the resistivity state of the semiconductor material of the resistor may be higher or lower than intended. After the electrical pulse is applied to switch the memory cell to the desired data state, the memory cell can be read to determine if the desired data state has been reached. If the desired data state has not been reached, an additional pulse is applied. The additional pulse or pulses may have a larger or smaller amplitude (voltage or current) or longer or shorter pulse width than the original pulse. After an additional set pulse, the cell is read again, and then set or reset pulses are applied as appropriate until the read current is in the desired range. In two-terminal devices, such as memory cells containing diodes and resistors, it would be particularly advantageous to read to verify and, if necessary, adjust the set or reset.

Memory Cell Manufacturing Method

Fabrication of a single memory level will be described in detail. Additional memory levels can be stacked, each monolithically formed vertically. In this embodiment, the polycrystalline and / or amorphous semiconductor resistors will function as switchable memory elements and the diodes will act as steering elements.

4A, formation of the memory begins with the substrate 100. The substrate 100 may comprise IV-IV compounds such as monocrystalline silicon, silicon-germanium or silicon-germanium-carbon, III-V compounds, II-VII compounds, epitaxial layers on, or other such substrates. It can be any semiconductor substrate known in the art, such as any other semiconductor material or non-semiconductor material. The substrate may comprise an integrated circuit fabricated thereon.

The insulating layer 102 is formed on the substrate 100. The insulating layer 102 may be silicon oxide, silicon nitride, high-dielectric film, Si-C-O-H film, or any other suitable insulating material.

The first conductors 200 (ie, the electrode 12 on the lower side shown in FIG. 2) are formed on the substrate and the insulator. An adhesion layer 104 is included between the insulating layer 102 and the conductive layer 106 to allow the conductive layer 106 to attach to the insulating layer 102. If the conductive layer on top is tungsten, titanium nitride is preferable as the adhesion layer 104.

The next layer to be deposited is the conductive layer 106. Conductive layer 106 may comprise any conductive material known in the art, such as tungsten, or other materials, including but not limited to tantalum, titanium, copper, cobalt, or alloys thereof.

Once all the layers to form the conductor have been deposited, the layers may use any suitable masking and etching process to form the substantially parallel, substantially coplanar conductors 200, as shown in cross section in FIG. 4A. Will be patterned and etched. In one embodiment, the photoresist is deposited, patterned by photolithography, the layers are etched, and then the photoresist is removed using standard process techniques. The conductors 200 may instead be formed by the damascene method.

Dielectric material 108 is then deposited on and between the conductor rails 200. Dielectric material 108 may be any known electrically insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. In a preferred embodiment, silicon dioxide is used as the dielectric material 108.

Finally, excess dielectric material 108 is removed over the conductor rails 200 to expose the tops of the conductor rails 200 isolated by the dielectric material 108 and to expose the substantially flat surface 109. Leave The resulting structure is shown in FIG. 4A. This removal of dielectric overcharge to form a flat surface 109 can be performed by any process known in the art, such as chemical mechanical planarization (CMP) or etch back. Etchback techniques that may advantageously be used are described in U.S. Application No. 10 / 883,417 to Raghuram et al., Entitled "Nonselective Unpatterned Etchback to Expose Buried Patterned Features", incorporated herein by reference and filed June 30, 2004. It is described in In this step, a plurality of substantially parallel first conductors were formed at a first height above the substrate 100.

Next, going to FIG. 4B, vertical pillars will be formed over the completed conductor rails 200. (In order to save space, the substrate 100 is not shown in FIG. 4B, which will be assumed to be present). Preferably the barrier layer 110 is deposited as a first layer after planarization of the conductor rails. Any suitable material can be used in the barrier layer, including tungsten nitride, tantalum nitride, titanium nitride, or combinations of these materials. In a preferred embodiment, titanium nitride is used as the barrier layer. If the barrier layer is titanium nitride, it can be deposited in the same manner as the adhesion layer described above.

The semiconductor material to be patterned into pillars is then deposited. The semiconductor material may be silicon, germanium, silicon-germanium alloy, or other suitable semiconductors, or semiconductor alloys. For simplicity, this description will refer to semiconductor materials as silicon, but it will be understood that one of ordinary skill in the art may instead select any of these other suitable materials instead. Preferably, the semiconductor material is deposited in a relatively large resistive amorphous or polycrystalline (including microcrystal) state.

In a preferred embodiment, the pillar comprises a semiconductor junction diode. The term junction diode is used herein to refer to a semiconductor device that has non-ohmic conductive properties, has two terminal electrodes, and is made of a semiconductor material in which one electrode is p-type and the other electrode is n-type. Examples include pn diodes and np diodes, which are in contact p-type semiconductor, such as zener diodes and pin diodes with intrinsic (undoped) semiconductor material interposed between the p-type semiconductor material and the n-type semiconductor material. Material and n-type semiconductor material.

Lower heavily doped region 112 may be formed by any deposition and doping method known in the art. Silicon may be deposited and subsequently doped, but is preferably doped in situ by flowing a donor gas that provides phosphorus, for example as n-type dopant atoms, during deposition of silicon. Highly doped region 112 is preferably about 10 to about 80 nm thick.

Intrinsic layer 114 may be formed by any method known in the art. Layer 114 may be silicon, germanium, or any alloy of silicon or germanium and has a thickness of about 110 to about 330 nm, preferably about 200 nm.

4B, along the underlying barrier layer 110, the now deposited semiconductor layers 114, 112 are patterned and etched to form pillars 300. The pillars 300 have approximately the same pitch and approximately the same width as the underlying conductors 200, so that each pillar 300 is formed above the conductor 200. Some misalignment can be tolerated. As will be described in detail below, the pillar 300 patterning and etching steps may be delayed later in the device fabrication process.

Pillars 300 may be formed using any suitable masking and etching process. For example, photoresist is deposited, patterned by using standard photolithography techniques, and etched, followed by removal of the photoresist. Alternatively, a hard mask of any other material, such as silicon dioxide, may be formed over the semiconductor layer stack with a bottom antireflective coating (BARC) on top, followed by patterning and etching. Likewise, dielectric antireflective coating (DARC) can be used as the hard mask.

US Application No. 10 / 728,436, entitled "Photomask Features with Interior Nonprinting Window Using Alternating Phase Shifting," filed Dec. 5, 2003, owned by the assignee of the present invention and incorporated herein by reference; Or the photolithography techniques described in US Application No. 10/815312 filed "Photomask Features with Chromeless Nonprinting Phase Shifting Window," filed April 1, 2004, for use in forming a memory array according to an embodiment of the present invention. It may be advantageously used to perform any photolithography step that is performed.

The pitch and width of the pillar 300 may vary as needed. In one embodiment, the pitch of the pillars (distance from the center of one pillar to the center of the next pillar) is about 300 nm and the widths of the pillars vary from about 100 to about 150 nm. In another preferred embodiment, the pitch of the pillars is about 260 nm and the widths of the pillars vary from about 90 to 130 nm. In general, the pillars have a substantially circular shape, preferably having a circular or approximately circular cross section with a diameter of 250 nm or less. An "substantially cylindrical" element has an approximately circular cross section, more specifically, the cross section having a straight edge for a length less than 50% of the longest dimension measured through the center of the cross-sectional area of any part of the perimeter. Is not a cross section. Obviously, the straight edges will not be "straight" at the molecular level, may have fine irregularities, and those involved are rounded, as described herein and described in US Pat. No. 6,952,030.

Dielectric material 108 is deposited over and between semiconductor pillars 300 to fill gaps between them. Dielectric material 108 may be any known electrically insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. In a preferred embodiment, silicon dioxide is used as the insulating material.

The dielectric material is then removed over the pillars 300 to expose the tops of the pillars 300 isolated by the dielectric material 108, leaving a substantially flat surface. Such removal of genetic overcharge can be performed by any process known in the art, such as CMP or etch back. The insulating layer 108 is planarized so that it surrounds the semiconductor region of the pillar 300. After CMP or etch back, ion implantation is performed to form a heavily doped p-type top region 116. The p-type dopant is preferably boron or BF 2 . This implantation step completes the formation of diode 111 as shown in FIG. 4B (the same diodes are designated as “4” in FIG. 2). Alternatively, region 116 may be deposited as a layer on layer 114 prior to the pillar patterning step, rather than implanted into layer 114. The resulting structure shown in FIG. 4B is schematically shown in FIG. 5A.

5B-5D show another permutation of diode structures. In the diodes of FIGS. 5A and 5B, the lower region 112 is N + (highly doped n-type silicon) and the upper region 116 is P +. In the diodes of FIGS. 5C and 5D, the lower region 112 is P + and the upper region 116 is N +. 5A and 5C, the intermediate region 114 is N−, and in FIGS. 5B and 5D, the intermediate region 114 is P−. The intermediate region may be intentionally lightly doped, or it may be intrinsic or intentionally not doped. The undoped region will never be completely electrically neutral and there will always be defects or contaminants that will behave as slightly n doped or p doped. Such a diode can be considered as a p-i-n diode. Accordingly, P + / N− / N +, P + / P− / N +, N + / N− / P + or N + / P− / P + diodes may be formed.

4C, a selective insulating oxide, nitride, or oxynitride layer 118 may then be formed on the heavily doped regions 116. Layer 118 will be reduced during formation of titanium silicide layer 124 (but generally not other metal silicide layers), as described below. Alternatively, layer 118 may be omitted. For example, the selective silicon dioxide layer 118 is grown by oxidizing silicon on tops of the heavily doped regions 116 at about 600 to about 850 ° C. for about 20 seconds to about 2 minutes, so that from about 1 to about 5 nm of silicon dioxide is formed. Preferably, oxide layer 118 is formed by exposing the wafer to about 800 degrees for about one minute in an oxygen containing atmosphere. Layer 118 may instead be deposited.

Next, a layer of silicide forming metal 120 is deposited. Preferred silicide forming metals to be used for this purpose include titanium or cobalt. This example will describe the use of titanium for layer 120 but it will be understood that other materials may be used.

Titanium layer 120 is deposited to any suitable thickness, for example about 1 to about 20 nm, preferably about 10 to about 15 nm, most preferably about 10 nm. In order to prevent oxidation of the titanium layer 120, the titanium nitride layer 122 is preferably deposited to a thickness of about 30 nm. Layers 120 and 122 may be deposited by any conventional method, such as by sputtering.

Annealing is performed, for example, in nitrogen for about 10 seconds to about 2 minutes at about 600 ° C. to about 800 ° C., preferably at about 650 ° C. to about 750 ° C., and most preferably at about 670 ° C. for about 20 seconds. Annealing reduces the oxide layer 118 and reacts the titanium layer 120 with the heavily doped regions 116 where a titanium layer is placed over these regions to form titanium silicide. The oxide layer 118 is substantially reduced between the titanium layer 120 and the heavily doped silicon regions 116. If oxide layer 118 was deposited rather than grown, the remaining oxide layer 118 (between the tops of semiconductor pillars 300 overlying dielectric fill 108) would remain.

As in conventional silicide processes, the titanium nitride layer 122 and unreacted titanium may be stripped in selective wet etching, leaving behind titanium silicide layers 124, each of which is a junction diode, as shown in FIG. 4D. On top of one of them a disk-shaped region. Thereafter, one or more decoupler conductive layers 6 (shown in FIG. 2), such as a new titanium nitride layer, are deposited on the silicide layer 124. Alternatively, the titanium nitride cap layer 122 under portions of the unreacted titanium layer 120 is not removed after silicide layer 124 formation and remains in the device to act as decoupler conductive layers 7. .

In a preferred embodiment, the titanium silicide feature 124 formed during annealing includes C49 phase titanium silicide. The C49 phase can be obtained if the annealing temperature is maintained below 700 ° C. for large or small size silicon features, or if the annealing temperature is maintained above 700 ° C., but the silicon feature size is 0.25 microns or less. Accordingly, the diameter of the diode is preferably equal to or less than 0.25 micron to form titanium silicide on C49 at annealing temperatures of 700 ° C. or higher. This phase is preferred due to the lattice match with amorphous silicon during the crystallization process. Conversely, large features (greater than 0.25 micron in size) will cause the titanium silicide to end as titanium silicide on C54 during subsequent annealing at 700 ° C. or higher. Although the C54 phase provides low resistivity (most desired by integrated circuit fabrications), it does not serve as a good lattice match during the crystallization process of amorphous or polycrystalline silicon. Accordingly, titanium silicide on C49 allows for the greatest improvement in grain growth, and low diode resistivity by acting as a crystallization template for the semiconductor material of the diode.

As mentioned, it is assumed in this example that titanium is used for the silicide forming metal layer 120, but other materials, including cobalt, may be used instead. Accordingly, titanium silicide layer 124 may be any other silicide, such as cobalt silicide.

In a preferred embodiment, the junction diode is amorphous silicon upon deposition and crystallized to form large grain low resistivity polysilicon in contact with the silicide layer 124. Crystallization may occur during formation of silicide 124 and / or during separate crystallization annealing after the memory cell is completed. Depending on the degree of crystallization desired, a separate crystallization annealing can be carried out for at least 1 minute, such as from 2 minutes to 24 hours, at a temperature of at least about 600 ° C., such as from 650 to 850 ° C. Low temperatures may be used for germanium and silicon germanium diode materials. The silicide layer 124 is advantageous for reducing the impedance of the junction diode, but may not be desirable in a finished device. In alternative embodiments, following the formation of the silicide layer on the junction diode, the silicide layer may be removed.

After formation of the one or more conductive decoupler layer (s) 120, 122, and / or 124, a semiconductor material to be patterned with the resistor 8 is deposited on the conductive layer (s). The layer of semiconductor material to be patterned into the resistor 8 may be about 10 nm to about 40 nm thick, for example about 20 nm thick. The semiconductor material may be silicon, germanium, or silicon-germanium alloy, or other suitable semiconductors, or semiconductor alloys. For simplicity, the present description will refer to semiconductor materials as silicon, but it will be understood by one skilled in the art that any of these may be selected as other suitable materials. Preferably, the semiconductor material is deposited in a relatively high resistive amorphous or polycrystalline (including microcrystal) state. Preferably, a semiconductor material is deposited on a conductive material, such as titanium nitride 122, which does not function as a crystallization template. Therefore, during crystallization annealing, the diode 4 in contact with the crystallization template material 124 is crystallized in a state of larger grain size with a lower resistivity than the resistor 8 not in contact with the crystallization template material 124.

The material of the resistor 8 is preferably not necessarily intrinsic (undoped) semiconductor material or slightly doped semiconductor material (with a p-type or n-type dopant concentration of less than 1 × 10 17 cm −3 ). If the resistor material is lightly doped, it may be formed by any deposition and doping method known in the art. Silicon may be deposited and subsequently doped, but is preferably doped in situ by flowing a donor gas that provides p or n type dopant atoms, such as boron or phosphorus, during deposition of the silicon.

The decoupler 6 and / or resistor 7 layers are then patterned to form an upper portion of the pillar 300. Patterning includes separate photolithography and etching steps from those used to pattern the diode 4 into the lower portion of the pillar 300 described above.

In an alternative embodiment, the decoupler 6 and resistor 8 layers may be patterned during the same photolithography and etching steps as the diode 4 layer to form the pillar 300 in one patterning step. In this embodiment, the photolithography and etching steps of pillar 300 are delayed until a layer of resistor 8 is deposited. Formation and planarization of dielectric material 108 is performed after pillar 300 formation. If desired, the silicidation step and / or diode crystallization annealing step used to form the silicide 124 may be delayed until after the entire pillar 300 including the resistor 8 portion is patterned. In this case, the titanium nitride layer 122 serves as a capping layer for forming the silicide layer 124 and also as a decoupler layer 6 positioned between the diode 4 and the resistor 8.

6 illustrates a completed memory cell. The upper conductors 400 (ie, the upper electrode 16 shown in FIG. 2) are, for example, a deposition adhesion layer 420, preferably made of titanium nitride, and a conductive layer 422, preferably made of tungsten. By, may be formed in the same manner as the lower conductors 200. Conductive layer 422 and adhesion layer 420 may be formed to form substantially parallel, substantially coplanar conductors 400 as shown in FIG. 6, extending perpendicular to conductors 200. Patterned and etched using suitable masking and etching techniques. In a preferred embodiment, the photoresist is deposited, patterned by photolithography and the layers are etched, and then the photoresist is removed using standard process techniques. If desired, the adhesion layer 420 may be patterned with the pillars 300, and may only be located on the pillars 300, while the conductive layer 422 may be attached to each pillar 300. Rails in contact with each portion of 420.

Next, a dielectric material (not shown) is deposited on and between the conductor rails 400. The dielectric material may be any known insulator such as silicon oxide, silicon nitride, or silicon oxynitride. In a preferred embodiment, silicon oxide is used as this dielectric material.

The formation of the first memory level has been described. Additional memory levels can be formed above this first memory level to form a monolithic three dimensional memory array. In some embodiments, the conductors may be shared between memory levels, that is, the upper conductor 400 will act as the lower conductor of the next memory level. In another embodiment, an interlevel dielectric (not shown) is formed over the first memory level of FIG. 6, its surface is planarized, and on this planarized interlevel dielectric without the conductors shared with the construction of the second memory level. To start.

A monolithic three dimensional memory array is a memory array in which a plurality of memory levels are formed on a single substrate, such as a wafer, without intervening substrates. Layers forming a memory level are deposited or grown directly on an existing level or layers of levels. Conversely, stacked memories were constructed by forming memory levels on individual substrates and attaching the memory levels vertically to each other, as in Leedy's US Pat. No. 5,915,167, "Three dimensional structure memory." Substrates can be thinned or removed from memory levels prior to bonding, but when memory levels are initially formed on individual substrates, these memories are not true monolithic three dimensional memory arrays.

Monolithic three dimensional memory arrays are described in US Pat. No. 6,034,882 to Johnson et al., Entitled " Vertically stacked field programmable nonvolatile memory and method of fabrication "; Johnson, US Pat. No. 6,525,953, entitled “Vertically stacked field programmable nonvolatile memory and method of fabrication”; Knall et al., US Pat. No. 6,420,215, entitled “Three Dimensional Memory Array and Method of Fabrication”; US Patent Application No. 10 / 095,962 to Herner, entitled “Silicide-Silicon Oxide-Semiconductor Antifuse Device and Method of Making”, filed March 13, 2002; US Patent Application No. 10 / 185,507 to Vyvoda et al., Entitled “Electrically Isolated Pillars in Active Devices,” filed June 27, 2002; US Patent Application No. of Vyvoda, filed May 19, 2003, entitled "Rail Schottky Device and Method of Making." 10 / 440,882; And Cleeves, entitled "Optimization of Critical Dimensions and Pitch of Patterned Features in and Above a Substrate," filed December 5, 2003, all of which are owned by the assignee of the present invention. And incorporated herein by reference.

One embodiment of the present invention has been described herein in the context of a monolithic three dimensional memory array formed on a substrate. This array includes at least a first memory level formed at a first height above the substrate, and a second memory level formed at a second height different from the first height. Three, four, eight, or more memory levels may be formed over the substrate in such a multilevel array. Each memory level is formed monolithically below the memory level.

Memory cells formed from a monolithic three dimensional memory array have stacked memory levels, but such cells may obviously be formed from a two dimensional array. The example given shows a silicide layer formed over the junction diode, but those skilled in the art will appreciate that the silicide layer may be formed elsewhere, for example next to or below the junction diode. Many configurations can be envisioned.

In an alternative embodiment, the resistor 8 is formed under the diode 4 in the pillar 300. In this embodiment, a resistor 8 is formed on the lower electrode 12. The decoupler conductive layer 6 is formed on the resistor 4. The diode 4 is then formed on the decoupler layer 6. The silicide crystallization template layer 124 may be formed in contact with the diode above or below the diode 4.

An alternative method of forming a similar array in which conductors are formed using a damascene structure is incorporated herein by reference and is filed on May 31, 2006, assigned to the assignee of the present invention. Protect Patterned Features During Trench Etch, US Pat. No. 11/4445936 to Ragigan et al. Methods of Radigan et al. May be used to form an array according to the present invention.

The foregoing detailed description has described only some of the many forms that this invention can take. For the above reasons, the detailed description is intended to be illustrative and not limiting. It is only the following claims, including all equivalents, which are intended to define the scope of the invention. All patents, patent applications, and publications described herein are incorporated by reference in their entirety.

2: memory cell, 4: polycrystalline semiconductor diode, 6: decoupler conductive layer, 8: polycrystalline semiconductor resistor, 12: bottom conductor, 16: top conductor

Claims (40)

  1. A nonvolatile memory device,
    Semiconductor diode steering element,
    Semiconductor read / write switching element
    And a nonvolatile memory device.
  2. The nonvolatile memory device of claim 1, further comprising at least one conductive layer positioned between the steering element and the read / write switching element.
  3. The nonvolatile memory device of claim 2, wherein the at least one conductive layer comprises a titanium nitride layer.
  4. 3. The nonvolatile memory device of claim 2, wherein the steering element, the at least one conductive layer and the read / write switching element are arranged in series and together comprise a nonvolatile memory cell.
  5. The nonvolatile memory device of claim 4, further comprising a first electrode and a second electrode in electrical contact with the nonvolatile memory cell.
  6. 6. The nonvolatile memory device of claim 5 wherein the read / write switching element comprises a resistor.
  7. The method of claim 6,
    The read / write conversion element comprises an amorphous, polycrystalline, or semiconductor resistor of amorphous and polycrystalline group IV,
    The steering element comprises a crystallized polycrystalline group IV semiconductor diode,
    At least one conductive layer is in contact with both the steering element and the read / write switching element.
  8. 8. The nonvolatile memory device of claim 7, wherein a silicide crystallization template layer is in contact with the steering element.
  9. 6. The nonvolatile memory device of claim 5, wherein the read / write switching element and the steering element are arranged in pillars between the first electrode and the second electrode.
  10. 6. The nonvolatile memory device of claim 5, wherein, in use, the read / write switching element of the memory cell switches from a first resistivity state to a second resistivity state that is different from the first resistivity state in response to an applied electrical pulse. .
  11. The nonvolatile memory device of claim 10, wherein the steering element does not transition from the first resistivity state to the second resistivity state in response to the applied electric pulse.
  12. 12. The nonvolatile device of claim 11, wherein the steering element is formed in a low resistivity state that does not change in response to the applied electric pulse, and the read / write switching element is formed in a high resistivity state that changes in response to the applied electric pulse. Memory device.
  13. 13. The nonvolatile memory device of claim 12 wherein the application of a second electrical pulse is adjusted to switch the read / write switching element from the second resistivity state to the first resistivity state.
  14. A nonvolatile memory device,
    Semiconductor diode steering element,
    A semiconductor resistor read / write switching element,
    At least one conductive layer located between the steering element and the read / write switching element;
    A first electrode in electrical contact with the steering element;
    A second electrode in electrical contact with the read / write switching element
    Including,
    And said read / write switching element, said at least one conductive layer and said steering element are arranged in series between pillars between said first electrode and said second electrode.
  15. 15. The device of claim 14, wherein the device comprises a monolithic three dimensional nonvolatile memory device,
    The read / write switching element comprises an amorphous, polycrystalline, or semiconductor resistor of amorphous and polycrystalline Group IV, the steering element comprises a crystallized polycrystalline Group IV semiconductor diode,
    The at least one conductive layer is in contact with the steering element and the read / write switching element,
    A silicide crystallization template layer is in contact with the steering element.
  16. A nonvolatile memory device,
    Semiconductor diode steering element,
    A semiconductor read / write switching element,
    At least one conductive layer located between the steering element and the read / write switching element;
    Means for switching the read / write switching element from a first resistivity state to a second resistivity state different from the first resistivity state and switching the read / write switching element from the second resistivity state to the first resistivity state;
    And a nonvolatile memory device.
  17. 17. The nonvolatile memory device of claim 16 wherein the steering element does not transition from the first resistivity state to the second resistivity state in response to an applied electrical pulse.
  18. 18. The nonvolatile device of claim 17, wherein the steering element is formed in a low resistivity state that does not change in response to the applied electric pulse, and the read / write switching element is formed in a high resistivity state that changes in response to the applied electric pulse. Memory device.
  19. 17. The nonvolatile memory device according to claim 16, wherein said switching means comprises a driver circuit adapted to apply an electric pulse to said read / write switching element.
  20. 17. The nonvolatile memory device of claim 16 wherein the read / write switching element comprises a resistor.
  21. A method of manufacturing a nonvolatile memory device,
    Forming a semiconductor diode steering element,
    Forming a semiconductor read / write switching element
    Including a non-volatile memory device manufacturing method.
  22. 22. The method of claim 21, further comprising forming at least one conductive layer located between the steering element and the read / write switching element.
  23. 23. The method of claim 22, wherein the at least one conductive layer comprises a titanium nitride layer.
  24. 23. The method of claim 22, wherein the steering element, the at least one conductive layer and the read / write switching element are arranged in series and together comprise a nonvolatile memory cell.
  25. 25. The method of claim 24, further comprising forming a first electrode and a second electrode in electrical contact with the nonvolatile memory cell.
  26. 27. The method of claim 25, wherein the read / write switching element comprises a resistor.
  27. 27. The device of claim 26, wherein the read / write conversion element comprises an amorphous, polycrystalline, or semiconductor resistor of a combination of amorphous and polycrystalline Group IV,
    The steering element comprises a crystallized polycrystalline group IV semiconductor diode,
    And the at least one conductive layer is in contact with the steering element and the read / write switching element.
  28. 28. The method of claim 27, further comprising: crystallizing the steering element positioned in contact with a silicide crystallization template layer while the read / write transition element is not in contact with a silicide crystallization template. A method of manufacturing a nonvolatile memory device having a lower resistivity than a read / write switching element.
  29. 29. The method of claim 28, further comprising patterning the read / write switching element, the at least one conductive layer and the steering element into a vertical pillar, wherein the vertical pillar is between the first electrode and the second electrode. Locating a nonvolatile memory device.
  30. 26. The non- volatile memory device of claim 25, wherein, in use, the read / write switching element of the memory cell switches from a first resistivity state to a second resistivity state that is different from the first resistivity state in response to an applied electrical pulse. Manufacturing method.
  31. 31. The method of claim 30, wherein the steering element does not transition from the first resistivity state to the second resistivity state in response to the applied electric pulse.
  32. 32. The method of claim 31 wherein the application of a second electrical pulse is adjusted to switch the read / write switching element from the second resistivity state to the first resistivity state.
  33. A method of manufacturing a nonvolatile memory device,
    Forming a semiconductor diode steering element,
    Forming a semiconductor resistor read / write switching element;
    Forming at least one conductive layer located between the steering element and the read / write switching element;
    Forming a first electrode in electrical contact with the steering element;
    Forming a second electrode in electrical contact with the read / write switching element
    Including,
    And said read / write switching element, said at least one conductive layer and said steering element are arranged in series between pillars between said first electrode and said second electrode.
  34. 34. The device of claim 33, wherein the read / write switching element comprises an amorphous, polycrystalline, or semiconductor resistor of amorphous and polycrystalline Group IV, the steering element comprises a crystallized polycrystalline Group IV semiconductor diode,
    The at least one conductive layer is in contact with the steering element and the read / write switching element,
    A silicide crystallization template layer is in contact with the steering element.
  35. The method of claim 34, wherein the method is
    Forming the first electrode on a substrate;
    Forming the semiconductor diode steering element on the first electrode;
    Forming a titanium or cobalt first conductive layer over the diode steering element;
    Forming a titanium nitride second conductive layer on the titanium or cobalt layer;
    Forming the resistor read / write switching element;
    Patterning the diode steering element, the first and second conductive layers and the resistor read / write switching element with a pillar;
    Annealing the device to react the first conductive layer with the diode steering element to form a titanium or cobalt silicide layer;
    Crystallizing the diode steering element in contact with the titanium or cobalt silicide layer such that the diode steering element has a lower resistivity than the resistor read / write switching element;
    Forming the second electrode over the resistor read / write switching element.
    Including a non-volatile memory device manufacturing method.
  36. A method of operating a nonvolatile memory device,
    Providing a nonvolatile memory cell comprising a semiconductor diode steering element, a semiconductor read / write switch element, and at least one conductive layer located between the steering element and the read / write switch element;
    A first switching step of switching the read / write switching element from a first resistivity state to a second resistivity state different from the first resistivity state;
    A second switching step of switching the read / write switching element from the second resistivity state to the first resistivity state;
    And operating the nonvolatile memory device.
  37. 37. The method of claim 36, wherein said first and second switching steps comprise applying first and second electrical pulses to said steering element and to said read / write switching element, respectively. .
  38. 38. The method of claim 37, wherein the steering element does not transition from the first resistivity state to the second resistivity state in response to the first and second applied electrical pulses.
  39. 39. The device of claim 38, wherein the steering element is formed in a low resistivity state that does not change in response to the first and second applied electrical pulses,
    The read / write switching element is formed in a high resistivity state that changes in response to the first and second applied electrical pulses,
    Wherein the first and second electrical pulses comprise forward biased electrical pulses of different magnitudes.
  40. 37. The method of claim 36, wherein said read / write switching element comprises a resistor.
KR1020107001752A 2007-06-29 2008-06-23 3d r/w cell with reduced reverse leakage and method of making thereof KR20100049564A (en)

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