KR20100024416A - Filming method, and treating system - Google Patents

Filming method, and treating system Download PDF

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Publication number
KR20100024416A
KR20100024416A KR1020097026131A KR20097026131A KR20100024416A KR 20100024416 A KR20100024416 A KR 20100024416A KR 1020097026131 A KR1020097026131 A KR 1020097026131A KR 20097026131 A KR20097026131 A KR 20097026131A KR 20100024416 A KR20100024416 A KR 20100024416A
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South Korea
Prior art keywords
forming
film
surface
chamber
processing
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KR1020097026131A
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Korean (ko)
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KR101396624B1 (en
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겐사쿠 나루시마
야스시 미즈사와
다카시 사쿠마
사토시 와카바야시
오사무 요코야마
다로 이케다
다츠오 하타노
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도쿄엘렉트론가부시키가이샤
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Priority to JPJP-P-2007-170656 priority Critical
Priority to JP2007170656A priority patent/JP2010192467A/en
Application filed by 도쿄엘렉트론가부시키가이샤 filed Critical 도쿄엘렉트론가부시키가이샤
Priority to PCT/JP2008/061645 priority patent/WO2009001896A1/en
Publication of KR20100024416A publication Critical patent/KR20100024416A/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14Metallic material, boron or silicon
    • C23C14/18Metallic material, boron or silicon on other inorganic substrates
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04Coating on selected surface areas, e.g. using masks
    • C23C16/045Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068Formation and after-treatment of conductors
    • H01L2221/1073Barrier, adhesion or liner layers
    • H01L2221/1084Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L2221/1089Stacks of seed layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]

Abstract

A film forming method is disclosed in which a thin film is formed on a workpiece W having an insulating layer 4 having a recess 6 formed on its surface. A barrier layer forming step of forming the Ti-containing barrier layer 12 on the surface of the object including the surface in the recess, a seed layer forming step of forming the Ru-containing seed layer 16 on the barrier layer by CVD; An auxiliary seed layer forming step of forming the Cu-containing auxiliary seed layer 164 by sputtering on the seed layer is sequentially performed. Thereby, it becomes possible to perform sufficient padding with respect to the recessed part with a small line width or hole diameter, or the recessed part with high aspect ratio over the whole to-be-processed object.

Description

Film deposition method and processing system {FILMING METHOD, AND TREATING SYSTEM}

TECHNICAL FIELD This invention relates to a film-forming method and a processing system. Specifically, It is related with the improvement of the seed layer formed when padding the recessed part formed in the surface of a to-be-processed object, such as a semiconductor wafer.

Generally, when manufacturing a semiconductor device, various processes, such as a film-forming process and a pattern etching process, are repeatedly performed to a semiconductor wafer. In line with the demand for further high integration and finer semiconductor devices, line widths and hole diameters are becoming smaller. Al (aluminum) alloys have been mainly used in the past as wiring materials and padding materials, but in recent years, since line widths and hole diameters have been miniaturized and higher operating speeds of semiconductor devices are required, tungsten (W) and Copper (Cu) also tends to be used.

When using metal materials such as Al, W, and Cu as padding materials for wiring materials and contact holes, (1) silicon diffusion is prevented between insulating materials such as silicon oxide film (SiO 2 ) and the metal materials. The insulating layer for the purpose of (2) improving the adhesion between the thin films, and (3) improving the adhesiveness between conductive layers such as the lower electrode and the wiring layer connected at the bottom of the hole. The barrier layer is interposed between the lower conductive layer and the lower conductive layer. As a film constituting such a barrier layer, a Ta film, a TaN film, a Ti film, a TiN film, and the like are widely known (Japanese Patent Laid-Open No. 11-186197, Japanese Patent Laid-Open No. 2004-232080, and Japanese Patent Laid-Open Patent Publication). 2003-142425, Japanese Patent Laid-Open No. 2006-148074, etc.). A conventional padding technique will be described with reference to FIG. 10.

FIG. 10 is a process chart showing a film formation method performed at the time of padding the recessed portion of the surface of the semiconductor wafer. FIG. As shown in Fig. 10A, a conductive layer 2 serving as a wiring layer, for example, is formed on the surface of a semiconductor wafer W made of, for example, a silicon substrate. An insulating layer 4 made of a SiO 2 film is formed on the entire surface of the semiconductor wafer W to cover the conductive layer 2. The conductive layer 2 is made of, for example, a silicon layer doped with impurities. The conductive layer 2 may correspond to the electrode of a transistor or a capacitor. In the case of a contact connected to a transistor, the conductive layer 2 is formed of NiSi (nickel silicide).

In the insulating layer 4, recesses 6, such as through holes or via holes, are formed for electrical connection to the conductive layer 2. As the recessed part 6, an elongate trench (groove) may be formed. The surface of the conductive layer 2 is exposed at the bottom of the recess 6. In detail, the entire surface of the semiconductor wafer W is made up of the Ti film 8 and the TiN film 10 having the above-described functions on the bottom and side surfaces of the recess 6 and the upper surface of the insulating layer 4. In order to form a two-layered barrier layer, first, a Ti film 8 is formed as shown in Fig. 10B, and then a TiN film is formed on the Ti film 8 as shown in Fig. 10C. (10) is formed.

In addition, the barrier layer 12 may be formed only by the Ti film 8 without forming the TiN film 10. The Ti film 8 can be formed by sputter film deposition or CVD (Chemical Vapor Deposition) using TiCl 4 as a raw material. In addition, the TiN film 10 can be formed by CVD using Ti-containing organic metal material gas or TiCl 4 gas as a raw material.

The barrier layer 12 has various forms. For example, as described above, a two-layer barrier layer formed by sequentially stacking the Ti film 8 and the TiN film 10, a barrier layer having a two-layer structure formed by sequentially stacking a TaN film and a Ta film, a Ti film, There is a one-layer barrier layer composed of any one of a TiN film, a Ta film, and a TaN film. The material and structure of the barrier layer 12 are determined according to the kind of the conductive layer formed on the barrier layer 12 and the required adhesion.

Recently, in particular, attention has been paid to a barrier film made of a single Ti film or a multilayer barrier film containing a Ti film. This is because such a barrier layer can particularly suppress diffusion of metals and the like, and has advantages such as very small electrical resistance, small volume expansion ratio, good adhesion to wiring materials, and the like.

After the barrier layer 12 is formed, as shown in FIG. 10 (d), a Cu film 14 as the seed layer 16 is formed on the barrier layer 12 by performing a sputter film deposition process. In addition, the seed layer 16 is preferably formed on the entire surface of the wafer surface including the surface in the recess 6, but since sputtering is highly directive, it is difficult for Cu atoms to adhere to the side surface in the recess 6, and the seed Formation of layer 16 is difficult.

After forming the seed layer 16, as shown in FIG.10 (e), the inside of the recessed part 6 is padded with the electrically conductive material 18, for example, Cu, by performing electroplating process. Thereafter, the wafer surface is polished by CMP (Chemical Mechanical Polishing) to cut away unnecessary conductive member 18, seed layer 16 and barrier layer 12 to planarize the wafer surface. The padding of the recessed part 6 is completed by the above.

In the conventional large line width and hole diameter, there is no big problem in the conventional padding method mentioned above. However, when the line width and the hole diameter become small, as shown in Fig. 10 (d), it is difficult to deposit a sufficient amount of the seed film 16 on the sidewalls in the concave portion 6, so that the seed film 16 adheres. There is also a part that does not. In this case, the plating current does not flow enough to the bottom part of the recessed part 6 at the time of plating process, and the problem that the void 20 generate | occur | produces as shown in FIG.10 (e) arises.

Solving the above-mentioned problem is very important in the present time when designing a line width and a hole diameter of 100 nm or less is required, not only when filling a recess with a small diameter and a high aspect ratio such as a contact hole. Do.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a film forming method and a processing system capable of satisfactory padding of a recess having a small line width or hole diameter or a recess having a high aspect ratio.

MEANS TO SOLVE THE PROBLEM As a result of earnestly studying the padding of the recessed part of the semiconductor wafer surface, this invention acquired the knowledge that padding can be optimized by using the Ru (ruthenium) film formed by CVD as a seed layer in a recessed part. It is early.

The present invention provides a film forming method for forming a thin film on an object to be treated with an insulating layer having a recess, wherein the barrier layer comprises a barrier layer containing Ti on the surface of the object including the surface in the recess. And a seed layer forming step of forming a seed layer containing Ru by CVD on the barrier layer, and an auxiliary seed layer forming step of forming an auxiliary seed layer containing Cu on the seed layer by sputtering. Provide a method of film formation.

According to the present invention, an auxiliary seed comprising Cu having low electrical resistance by sputtering on the seed layer over the entire surface of the workpiece while uniformly forming a seed layer containing Ru by CVD on the surface of the recess. Forming a layer. As a result, by the subsequent electroplating process, sufficient padding of Cu can be performed over the whole to-be-processed object also in the recessed part with a small line width or a hole diameter, or a recessed part with a large aspect ratio.

The barrier layer may be formed by chemical vapor deposition (CVD) or sputtering. The barrier layer can be constituted by a single Ti film. Instead of this, the barrier layer can be composed of a stacked Ti film and a TiN film.

Preferably, a pre-cleaning step of pre-cleaning the target object is performed before the barrier layer forming step. It is preferable to perform each said process continuously in a vacuum, without exposing the said to-be-processed object to air | atmosphere. Typically, after the said auxiliary seed layer formation process, the plating process for padding the said recessed part with Cu is performed.

The recess is made of any one or a combination of a via hole, a through hole, a contact hole, and a trench (trench). The diameter or width of the recess can be 100 nm or less.

Further, according to the present invention, in the processing system for forming a thin film on the surface of the workpiece, a processing chamber for forming a thin film containing Ti on the surface of the target object, and a thin film containing Ru on the surface of the target object A processing chamber to be formed, a processing chamber for forming a thin film containing Cu on the surface of the target object, at least one common transport chamber connected to at least one of the processing chambers and capable of vacuum suction, and provided in the common transport chamber There is provided a processing system including a transport mechanism for transporting the object to be processed between the respective processing chambers, and a control unit for controlling the processing system so that the film forming method described above is executed.

The said processing system can further be equipped with the process chamber which performs a pre-cleaning process to the said to-be-processed object.

1 is a schematic plan view showing an example of the configuration of a processing system according to the present invention;

2 is a schematic cross-sectional view showing an example of the configuration of a plasma film forming chamber;

3 is a schematic cross-sectional view showing an example of the configuration of a thermal film forming chamber;

4 is a flowchart showing an example of a film forming method according to the present invention;

5 is a partially enlarged cross-sectional view of the vicinity of a recess of a semiconductor wafer for explaining a film forming situation in each step in the film forming method according to the present invention;

6 is a copy of the photograph for explaining the padding evaluation results;

7 is a graph for explaining the evaluation test results of barrier properties of a thin film;

8 is a copy of a photograph for explaining the results of evaluation evaluation of the cohesiveness of a thin film;

9 is a schematic plan view showing a configuration of a modification of the processing system according to the present invention;

10 is a partially enlarged cross-sectional view of the vicinity of a recess of a semiconductor wafer for explaining the conventional film forming method.

EMBODIMENT OF THE INVENTION Below, the preferable embodiment of the film-forming method and processing system which concern on this invention is described in detail based on an accompanying drawing. 1 is a schematic cross-sectional view showing an example of a configuration of a processing system according to the present invention, FIG. 2 is a schematic cross-sectional view showing an example of a configuration of a plasma film formation processing chamber, and FIG. 3 is a schematic cross-sectional view showing an example of a configuration of a thermal film processing chamber.

<Description of Processing System>

First, the processing system will be described. As shown in FIG. 1, this processing system 22 is comprised as what is called a cluster tool, and when it sees in plurality, for example, four process chambers 24a, 24b, 24c, 24d, and a planar view, (planar view) The main conveyance chamber 26 of substantially hexagon shape, the 1st and 2nd load lock chambers 28a and 28b which have a load lock function, and the elongate rectangular introduction side conveyance chamber 30 are mainly included.

Each of the processing chambers 24a to 24d is joined to four sides of the common transfer chamber 26, and the first and second load lock chambers 28a and 28b are respectively joined to the remaining two sides. The introduction side conveyance chamber 30 is connected to the 1st and 2nd load lock chambers 28a and 28b. In this embodiment, a Ti (titanium) film is formed in the first processing chamber 24a, a Ru (ruthenium) film is formed in the second processing chamber 24b, and a Cu (copper) film is formed in the third processing chamber 24c. In the fourth processing chamber 24d, a pre-cleaning process for removing the native oxide film or the like on the wafer surface is performed by plasma sputter etching. When the pre-cleaning process is not performed, the fourth processing chamber 24d can be omitted.

It is connected between the common conveyance chamber 26 and each process chamber 24a-24d, and between the common conveyance chamber 26 and the 1st and 2nd load lock chambers 28a, 28b through the gate valve G, The yarns 24a to 24d, 28a and 28b can communicate with the common transfer chamber 26. The inside of the common conveyance chamber 26 is vacuum-sucked. The gate valve G is also interposed between the first and second load lock chambers 28a and 28b and the introduction side transfer chamber 30. In the first and second load lock chambers 28a and 28b, vacuum suction and return to atmospheric pressure are repeated as the wafer is taken in and out.

In the common conveyance chamber 26, the 1st conveyance which consists of the articulated arm which can be stretched and turned, provided so that the loadlock chambers 28a and 28b and all the process chambers 24a-24d can be accessed. The mechanism 32 is provided. The 1st conveyance mechanism 32 has two picks 34a and 34b which can be independently extended in the opposite direction, and can handle two wafers at once. The 1st conveyance mechanism 32 may have only one pick.

The introduction side conveyance chamber 30 is formed in horizontally long box shape, One or more long sides are provided with one or more (three in the example) entrance openings for introducing the semiconductor wafer which is a to-be-processed object. The door 36 is provided in each entrance. Corresponding to each delivery port, an introduction port (stage) 38 is provided, respectively, and one cassette container 40 can be mounted therein, respectively. Each cassette container 40 can accommodate a plurality of, for example, 25 wafers W in multiple stages at the same pitch.

In the introduction side conveyance chamber 30, the 2nd conveyance mechanism 42 which is an introduction side conveyance mechanism is provided in order to convey the wafer W along the longitudinal direction of the said conveyance chamber 30. The 2nd conveyance mechanism 42 has two picks 46a and 46b which can be extended and revolved, and can handle two wafers W at a time. The 2nd conveyance mechanism 42 is supported so that slide movement is possible on the guide rail 44 extended along the longitudinal direction of the said conveyance chamber 30 in the introduction port side in the introduction-side conveyance chamber 30. .

At one end of the introduction side transfer chamber 30, an orienter 48 for aligning the wafer is provided. The orienter 48 has the rotating table 48a rotated by a drive motor, and rotates in the state which mounted the wafer W on the rotating table 48a. On the outer circumference of the swivel table 48a, an optical sensor 48b for detecting the periphery of the wafer W is provided, whereby the positioning cutout of the wafer W, for example, the position of the notch or orientation flat and The amount by which the position of the center of the wafer W shift | deviated can be detected.

In order to control the operation of the entire processing system, a control unit 50 made of a computer is provided. Programs required for operation control of the entire processing system are stored in a storage medium 52 such as a floppy disk, compact disc (CD), hard disk, or flash memory. In accordance with the instruction from the control unit 50, control of the loading and unloading of the wafer W, the start of the supply of various gases, the stop and the flow rate control, the process temperature, the process pressure, and the like are performed.

The outline of the operation of the processing system 22 will be described. First, the unprocessed semiconductor wafer W is carried into the introduction side conveyance chamber 30 by the 2nd conveyance mechanism 42 from the cassette container 40 provided in the introduction port 38, and the wafer W is taken into the introduction side conveyance chamber ( It is conveyed to the orienter 48 provided in the end of 30), and positioning is performed there.

The wafer W on which positioning has been made is carried in to either one of the 1st and 2nd load lock chambers 28a and 28b by the 2nd conveyance mechanism 42. After the load lock chamber is vacuum sucked, the wafer W in the load lock chamber is loaded into the common transport chamber 26 by the first transport mechanism 32 in the common transport chamber 26 which has been vacuum suction in advance.

Subsequently, the wafer W is loaded into the fourth processing chamber 24d and pre-cleaned therein. Then, the wafer W is loaded into the first processing chamber 24a, where the formation of the Ti film (or Ti film and TiN film) is prevented. Then, the wafer W is carried into the second processing chamber 24b and the Ru film is formed there. Next, the wafer W is carried into the third processing chamber 24c and the Cu film is formed there.

In this way, the wafer W subjected to the pre-cleaning treatment, the Ti film (Ti film and TiN film) film forming process, the Ru film film forming process, and the Cu film film forming process is either the load lock chamber 28a or 28b and the introduction side conveyance chamber. The wafer 30 is accommodated in the cassette container 40 for wafers after the introduction port 38 has been processed. Subsequently, the wafer W is conveyed to the plating apparatus, whereby the padding of the recesses by Cu is performed by the electroplating treatment. The above series of processing will be described later in detail.

<Description of plasma film forming processing chamber>

Next, the plasma film forming chamber will be described with reference to FIG. 2. Among the first to fourth processing chambers 24a to 24d, a processing chamber for performing a film forming process using plasma, specifically, a first processing chamber 24a for forming a Ti film by plasma processing, corresponds to a plasma film forming chamber. As shown in FIG. 2, the plasma film forming chamber 54 has a cylindrical processing container 56 formed of an aluminum alloy or the like. The processing container 56 is grounded. In the processing container 56, a mounting table 58 made of ceramic such as aluminum nitride is provided. The mounting table 58 is supported by the strut 57 standing up at the bottom of the processing container 56. The wafer W can be mounted on the upper surface of the mounting table 58.

In the mounting table 58, a heating means 60 made of a tungsten wire heater is provided, whereby the wafer W can be heated to a predetermined temperature. In the mounting table 58, a mesh-shaped conductive member 62 is provided above the tungsten wire heater 60. The conductive member 62 is grounded by wiring (not shown), whereby the mounting table 58 acts as a lower electrode at the time of plasma generation. A bias high frequency voltage may be applied to the conductive member 62. The mounting table 58 is provided with a lift pin (not shown) that lifts and lifts the wafer W when mounting the wafer W on the mounting table 58 and when removing the wafer W from the mounting table 58.

The exhaust port 64 is formed in the bottom part of the processing container 56. An exhaust system 66 including a vacuum pump, a pressure regulating valve, and the like is connected to the exhaust port 64, whereby the inside of the processing container 56 can be sucked in a vacuum and maintained at a predetermined pressure.

In the side wall of the processing container 56, an opening 68 having a size capable of carrying in and out of the wafer W is formed. The gate valve G mentioned above is provided in this opening 68. The upper end of the processing container 56 is opened, and the shower head 72 as the gas introduction means is hermetically mounted with the insulating member 70 interposed between the opening ends of the processing container 56. The shower head 72 can be formed of, for example, an aluminum alloy. The diffusion chamber 74 is formed in the shower head 72.

In the lower surface of the shower head 72, a plurality of gas injection holes 78 communicating with the diffusion chamber 74 are formed, so that a desired gas can be introduced into the processing container 56. The gas introduction port 80 is formed in the upper part of the shower head 72, and it can introduce | transduce the raw material gas required for film-forming from this gas introduction port 80, respectively, controlling flow volume. The gas introduced from the gas introduction port 80 diffuses in the diffusion chamber 74 of the shower head 72, and is uniformly injected from the gas injection hole 78 into the space above the wafer W.

The shower head 72 is connected to a power supply line 86 to which a matching circuit 82 and a high frequency power source 84 at a predetermined frequency (for example, 450 kHz) for plasma generation are connected. Thus, the shower head 72 functions as an upper electrode at the time of plasma generation. In a state where the wafer W is heated to a predetermined temperature by the heating means 60, the predetermined processing gas is introduced into the processing space in the processing container 56, and the mounting table as the shower head 72 as the upper electrode and the lower electrode is provided. The plasma is generated by applying high frequency energy between 58, so that the plasma W can be subjected to a predetermined plasma treatment, for example, a Ti film deposition process.

<Description of the thermal film processing chamber>

Next, the thermal film forming chamber will be described with reference to FIG. 3. In the first to fourth processing chambers 24a to 24d, a process chamber which performs a film formation process by heat treatment such as thermal CVD, specifically, a second process chamber 24b which forms a Ru film by thermal CVD, and a Cu film is formed by thermal CVD. The third processing chamber 24c corresponds to the thermal film processing chamber.

As shown in FIG. 3, the thermal film forming chamber 88 has a cylindrical processing container 90 formed of an aluminum alloy or the like. In the processing container 90, a mounting table 94 made of ceramic such as aluminum nitride is provided. The mounting table 94 is supported by a support 92 standing up from the bottom of the processing container 90. The wafer W can be mounted on the upper surface of the mounting table 94.

In the mounting table 94, a heating means 96 made of a tungsten wire heater is provided, whereby the wafer W can be heated to a predetermined temperature. The mounting table 94 is provided with a lifter pin (not shown) that lifts and lifts the wafer W when mounting the wafer W on the mounting table 94 and when removing the wafer W from the mounting table 94.

The exhaust port 98 is formed in the bottom part of the processing container 90. An exhaust system 100 including a vacuum pump, a pressure regulating valve, or the like is connected to the exhaust port 98, whereby the inside of the processing container 90 can be sucked in a vacuum and maintained at a predetermined pressure.

In the side wall of the processing container 90, an opening 102 having a size capable of carrying in and out of the wafer W is formed. The gate valve G mentioned above is provided in this opening 102. The upper end of the processing container 90 is opened, and the shower head 104 as a gas introduction means is hermetically attached to the opening end of the processing container. The shower head 104 may be formed of, for example, an aluminum alloy or the like.

The first gas inlet 106 and the second gas inlet 108 are provided above the shower head 104. In the shower head 104, the first diffusion chamber 110 communicates with the first gas introduction port 106 and the second gas introduction port 108, and is isolated from the first diffusion chamber 110. The second diffusion chamber 112 is formed. On the gas injection surface of the lower surface of the shower head 104, a plurality of first gas injection holes 114 communicating with the first diffusion chamber 110 and a plurality of second gases communicating with the second diffusion chamber 112 are provided. The injection hole 116 is formed. Other gases are uniformly injected into the processing space in the processing vessel 90 from the first and second gas injection holes 114 and 116, and the injected gases are first mixed after being introduced into the processing vessel 90.

Such a gas mixing method is called a postmix. Moreover, it is possible to supply the source gas required for film-forming, respectively, to the 1st gas introduction port 106 and the 2nd gas introduction port 108, controlling flow rate.

The predetermined thin film, for example, described above on the surface of the wafer W by thermal CVD by supplying a gas required for the processing space in the processing container 90 while the wafer W is heated to a predetermined temperature by the heating means 96. , Ru film, Cu film and the like can be formed. When the post-mixing gas supply is not necessary, a shower head having only one gas diffusion chamber can be used as shown in the shower head 72 shown in FIG. 2.

<Description of the film formation method>

Next, the film formation method according to the present invention performed using the processing system 22, in particular, the processing chambers 24a to 24d will be described. 4 is a flowchart showing an example of the film forming method of the present invention, and FIG. 5 is a partially enlarged cross-sectional view near the recessed portion of the semiconductor wafer for explaining the film forming situation of each film forming step.

As shown in FIG. 4, the film-forming method which concerns on this invention contains the pre-cleaning process S1 which performs the pre-cleaning process with respect to the surface of the semiconductor wafer W, and Ti on the surface (including the surface without a recessed part) of the wafer W. As shown in FIG. A barrier layer forming step S2 for forming a barrier layer, a seed layer forming step S3 for forming a seed layer containing Ru on the barrier layer, and a Cu containing Cu to assist conductivity of the seed layer on the seed layer. It is mainly comprised by auxiliary seed layer formation process S4 which forms an auxiliary seed layer, and plating process S5 which performs plating process in order to pad the inside of a recess with a conductive member. In addition, depending on the processing conditions, the pre-cleaning step S1 may be omitted.

Next, each said process is demonstrated. In Fig. 5, the same reference numerals are given to the same elements as in Fig. 10.

<Pre-cleaning Step>

First, as shown in Fig. 5A, the wafer W, in which the concave portion 6 made of a contact hole, a through hole, or the like is formed in the insulating layer 4 of the semiconductor wafer W, is referred to as a fourth processing chamber 24d (see Fig. 1). Bring in). At the bottom of the recess 6, as described above in the background art, a conductive layer 2 made of a silicide film such as a silicon layer or a NiSi film doped with impurities is exposed. On the surface of the conductive layer 2, a natural oxide film is formed by contact with oxygen and moisture in the air atmosphere. In order to remove this natural oxide film etc., a pre-cleaning process is performed (S1 of FIG. 4).

Specifically, as the fourth processing chamber 24d, a plasma etching processing chamber having an ICP (inductively coupled) plasma etching function is used. Plasma is generated by flowing a rare gas, for example, Ar gas, into the fourth processing chamber 24d, and sputter etching processing, that is, pre-cleaning processing is performed by the plasma. As a result, the native oxide film on the surface of the conductive layer 2 exposed at the bottom of the recess 6 is removed.

<Barrier layer forming process>

After completion of the pre-cleaning step, the wafer W is conveyed to the first processing chamber 24a, where a barrier layer forming step is performed (S2 in FIG. 4). Here, as the first processing chamber 24a, the plasma film forming processing chamber 88 described above with reference to FIG. 2 is used. In this barrier layer forming step, a Ti film 8 is first formed as shown in FIG. 5 (b), and the surface portion of the Ti film 8 is nitrided by plasma nitridation treatment. The TiN film 10 shown is continuously formed in the same process chamber, and the barrier layer 12 which consists of the Ti film 8 and the TiN film 10 is formed by this.

Specifically, first, TiCl 4 gas, which is a raw material gas, H 2 gas, which is a reducing gas, and Ar gas, which is a diluting gas, are supplied into a processing chamber, and the Ti film (by a plasma CVD is performed under a predetermined process temperature and a predetermined process pressure). 8) is deposited. As a result, the Ti film 8 is formed on the inner surface of the recess 6 and the upper surface of the insulating layer 4. The barrier effect of the barrier layer 12 depends on the film thickness of the Ti film 8, and in order to have a sufficient barrier effect, the film thickness of the Ti film 8 needs to be 10 nm or more.

When the film formation of the Ti film 8 is completed, the gas to be supplied next is switched to nitride the surface of the Ti film. As a necessary gas used here, NH 3 gas, which is a nitriding gas, and N 2 gas, which is a dilution gas, are supplied into a processing chamber, plasma is generated under a predetermined high frequency power and a predetermined process pressure, and the surface of the Ti film 8 is plasma nitrided. To form a TiN film 10.

As a result, a TiN film 10 as a Ti-containing film is formed on the Ti film 8. As a result, the barrier layer 12 of the two-layer structure which consists of the Ti film 8 and the TiN film 10 as a Ti containing barrier layer is formed.

<Seed layer formation process>

After completion of the barrier layer forming step, the wafer W is then conveyed to the second processing chamber 24b, where the seed layer forming step S3 is performed. In this seed layer forming step, a Ru film 160 which is a Ru-containing film shown in FIG. 5 (d) is formed as the seed layer 16.

Specifically, as the second processing chamber 24b, the thermal film processing chamber 88 as described above with reference to FIG. 3 is used as described above. In this seed layer forming step, since the gas is not supplied by the postmix method, the shower head provided in the thermal film processing chamber 88 may have one gas diffusion chamber. In film formation, Ru 3 (CO) 12 (see international publication WO2004 / 111297) which is a metal carbonyl (organic metal compound) and a rare gas such as Ar gas, which are metal carbonyl (organic metal compound), are used as the Ru-containing raw material. Specifically, for example, the liquid Ru-containing raw material is bubbled with Ar gas to vaporize it and supplied to the process chamber, and the Ru film 160 is deposited by thermal CVD under a predetermined process temperature and a predetermined process pressure. As a result, the Ru film 160, that is, the seed layer 16 made of the Ru-containing film is formed on the entire surface of the barrier layer 12 (including the inner surface of the recess 6).

The process time of the seed layer forming step can be set, for example, about 60 sec, thereby forming the Ru film 160 having a film thickness of about 3 nm on the uppermost surface of the wafer W. In the vaporization of the Ru-containing liquid raw material, for example, the Ru-containing liquid raw material is heated to about 50 to 100 ° C. and bubbled with Ar gas at a flow rate of about 50 to 200 sccm. The wafer temperature at the time of a process can be in the range of 150-600 degreeC, and a process pressure can be in the range of 1-100 Pa.

The reason why the Ru film 160 is used as the seed layer 16 is because the crystal lattice constant of the Ru metal is very close to the crystal lattice constant of Cu (copper), so that the Ru film 160 and the Cu film 162 described later This is because the affinity is good and the adhesion of the Cu film 162 onto the Ru film 160 is good. In addition, since the Ru film 160 is formed by CVD, as shown in FIG. 5 (d), it is desirable to form the Ru film 160 over the entire surface of the concave portion 6 having a high aspect ratio over the entire surface. It becomes possible.

<Second seed layer forming process>

After completion of the seed layer forming step, the wafer W is then transferred to the third processing chamber 24c, where the auxiliary seed layer forming step S4 is performed. In this auxiliary seed layer forming step, as shown in FIG. 5E, a Cu film 162 that is a Cu-containing film is formed as the auxiliary seed layer 164.

Specifically, the sputter film-forming chamber which has the function of ionization sputter film-forming is used as the 3rd process chamber 24c. A rare gas such as Ar gas is supplied into the processing chamber, and the Ar gas is converted into plasma by the energy of the electromagnetic field generated by the induction coil, and the generated ions collide with the metal target made of Cu to emit Cu metal particles. Is incident on the wafer W to deposit the Cu film 162 to form the auxiliary seed layer 164. Since the Cu film 162 is formed by sputtering with high directivity, as shown in Fig. 5E, the Cu film 162 is mainly deposited on the uppermost surface of the wafer W and the bottom portion in the recess 6.

The reason for forming the auxiliary seed layer 164 is as follows. That is, since the electrical resistance of the Ru film 160 is relatively high, the plating current supplied from the periphery of the wafer W is not sufficiently supplied to the center of the wafer W in the subsequent plating process. Therefore, by forming the auxiliary seed layer 164 made of the Cu film 162 having a low electrical resistance on the seed layer 16 made of the Ru film 160, the plating current is sufficiently supplied to the center portion of the wafer W. It is. For the above reason, it is not necessary to form the Cu film 162 inside the recessed portion 6. Therefore, in forming the Cu film 162, the sputtering method which can form into a film at high speed is used. In addition, in consideration of the film thickness ratio with the Ru film, the film thickness of the Cu film 162 is preferably about 10 nm.

Plating process

After the completion of the auxiliary seed layer forming step, the wafer W is taken out of the third processing chamber 24c, taken out of the processing system, and subjected to plating by an electroplating apparatus (not shown), thereby showing in FIG. 5 (f). Likewise, the inside of the recess 6 is padded with a conductive member 18 made of Cu (S5 in FIG. 4).

As described above, since the seed layer 16 made of the Ru film 160 is sufficiently formed on the inner surface of the concave portion 6, unlike the conventional method shown in FIG. 10E, no void is generated. The inside of the recess 6 can be padded with Cu. As described above, the series of steps of the film forming method according to the present invention is completed.

As explained above, in the said embodiment, when padding the recessed part 6 of the surface of the semiconductor wafer W which is a to-be-processed object, Ti is included in the surface of the wafer W including the surface in the recessed part 6. A barrier layer forming step of forming the barrier layer 12, a seed layer forming step of forming a seed layer 16 including Ru on the barrier layer by CVD, and an auxiliary containing Cu on the seed layer 16. An auxiliary seed layer forming step of forming the seed layer 164 by sputtering is performed. For this reason, the seed layer 16 containing Ru can be formed uniformly in the inner surface of the recessed part 6, and the auxiliary seed layer 164 containing Cu which is low in electrical resistance is put on the wafer W whole surface. It can form over. As a result, by the subsequent electroplating process, the padding of Cu into the recess can be sufficiently performed over the entire wafer surface even for the recess having a small line width or hole diameter or a recess having a high aspect ratio.

In addition, since the wafer W is not exposed to the atmosphere between the pre-clean process and the auxiliary seed layer 164 forming process, unnecessary oxide films are not formed in each thin film formed in each process, so that the film quality and characteristics of each film are maintained. Therefore, good device performance can be obtained.

<Evaluation of Padding of the Method of the Present Invention>

An experiment was conducted to evaluate the padding property according to the film forming method of the present invention. The result is demonstrated below. 6 is a copy of an electron micrograph of a cross section of a sample, (a) is padded by a conventional method (Cu plating after formation of a Ti / TiN barrier layer and a Cu seed layer), (b) is a method of the present invention The padding was carried out by (plating Cu after formation of the Ti / TiN barrier layer, the Ru seed layer and the Cu auxiliary seed layer). Photos are slanted for convenience of photography. The aspect ratio of the recess is about 10.

As shown in Fig. 6 (a), in the conventional method, the lower half of the concave portion was not sufficiently padded with Cu. On the other hand, in the case of the method of the present invention shown in Fig. 6 (b) using the Ru film as the seed layer, it was sufficiently padded with Cu to the bottom of the recess. Thereby, it was confirmed that the padding property can be remarkably improved by the method of the present invention.

<Evaluation of barrier property and cohesiveness of the method of the present invention>

The experiment which evaluates the barrier property and cohesion of the thin film formed by the film-forming method of this invention was done. The result is demonstrated below. 7 is a graph showing experimental results of evaluating barrier properties of a thin film, and FIG. 8 is a copy of a photograph showing a surface state of a Cu film for evaluation of the cohesiveness of a thin film. Cohesiveness here is an index which measures the extent to which Cu atoms move easily when a Cu film is formed on the surface of a base. When Cu atom is easy to move, as shown in FIG.8 (a), a surface form deteriorates and a padding by Cu cannot be performed normally in a subsequent Cu plating process. On the other hand, when Cu atom does not move, a smooth surface is obtained as shown to FIG. 8 (b), and the device which has a favorable characteristic (reliability) by which processing is performed normally in the subsequent Cu plating process can be obtained. have.

In this experiment, Ti (barrier) / TiN (barrier) / Cu (seed) laminated structure formed according to the conventional method and Ti (barrier) / TiN (barrier) / Ru (seed) / Cu formed according to the present invention method (Secondary seed) About the laminated structure, the annealing process for 30 minutes was performed at the temperature of 400 degreeC. The sheet resistance was measured before and after the annealing treatment, and the surface (the surface of the Cu seed layer / Cu auxiliary seed layer) was observed with an electron microscope after the annealing treatment.

As described above, the barrier property is caused by the Ti / TiN film. If the barrier property of the Ti / TiN film is deteriorated under the influence of Ru film formation, mutual diffusion occurs between the Cu film and the Si-containing layer of the base during annealing, and the sheet resistance of the Cu film is greatly increased. As a result of the experiment, it was confirmed that there was no such problem. That is, as shown in FIG. 7, before annealing, the sheet resistance of the laminated structure of the conventional method and the laminated structure of the method of this invention was 0.15 [ohms / sq.]. And after annealing, the sheet resistance of the laminated structure of the conventional method and the laminated structure of the method of this invention was 0.13 [ohms / sq.]. That is, it was confirmed that the laminated structure according to the method of the present invention has barrier properties equivalent to those of the laminated structure according to the conventional method in which it is confirmed that there is no problem in barrier property.

In addition, as shown in Fig. 8A, in the conventional method, the surface form was significantly degraded by annealing, and it was confirmed that large lumps were scattered on the surface of the Cu film. In contrast, as shown in Fig. 8 (b), in the case of the method of the present invention, no lump was seen on the surface of the Cu film, and the flat surface was formed. That is, it was confirmed that cohesiveness can be significantly improved by the method of the present invention.

<Evaluation of adhesion>

In addition, the adhesiveness was evaluated by the scratch tape test about the Ti / TiN / Cu laminated structure formed by the conventional method, and the Ti / TiN / Ru / Cu laminated structure formed by the method of this invention. As a result, in the laminated structure which concerns on the conventional method, peeling of the thin film was confirmed. On the other hand, in the laminated structure which concerns on the method of this invention, it was confirmed that there is no peeling of a thin film and adhesiveness can be improved significantly.

<Modification Example of Processing System>

Next, the modification of the processing system which concerns on this invention is demonstrated. 9 is a schematic plan view showing a configuration of a modification of the processing system according to the present invention. In addition, in FIG. 9, the same code | symbol is attached | subjected to the same component part as FIGS. 1-4, and description of those component parts is abbreviate | omitted. In the processing system shown in FIG. 1, one common conveyance chamber 26 was provided and four process chambers were connected to the circumference | surroundings. In contrast, in the processing system 170 shown in FIG. 9, in order to include more processing chambers in one processing system, a second common transfer chamber 172 is provided in addition to the first common transfer chamber 26. . The 2nd common conveyance chamber 172 is comprised so that the inert gas can be supplied in the inside and vacuum suction and pressure adjustment in the inside can be performed.

Third and fourth load lock chambers 28c and 28d are provided between the second common transport chamber 172 and the first common transport chamber 26. A gate is provided between the first common transport chamber 26 and the third and fourth load lock chambers 28c and 28d, and between the second common transport chamber 172 and the third and fourth load lock chambers 28c and 28d. Valve G is provided, respectively. The third and fourth load lock chambers 28c and 28d are configured to be able to supply an inert gas therein and to perform vacuum suction and pressure adjustment therein. In the 2nd common conveyance chamber 172, the 3rd conveyance mechanism which can be stretched and turned with two picks 176a and 176b comprised similarly to the 1st conveyance mechanism 32 in the said 1st common conveyance chamber 26 is possible. 174 is provided.

5th and 6th process chambers 24e and 24f are respectively connected to the 1st common conveyance chamber 26 through the gate valve G. As shown in FIG. The seventh, eighth, and ninth processing chambers 24g, 24h, 24i are connected to the second common transfer chamber 172 through the gate valve G, respectively. The fifth processing chamber 24e is a processing chamber in which a Ti film is formed by the plasma CVD method, and the plasma film forming processing chamber 54 as shown in FIG. 2 is used for this. The sixth processing chamber 24f is a processing chamber for forming a TiN film by thermal CVD, and a thermal film processing chamber 88 as shown in FIG. 3 is used for this.

In order to move the wafer W between the fifth (or sixth) processing chamber 24e and 24f and the first common transfer chamber 26, the gate valve G is always opened in the first common transfer chamber 26. The pressure is made higher than the pressure in the fifth (or sixth) processing chamber 24e and 24f so that the atmosphere in the fifth (or sixth) processing chamber 24e and 24f flows out into the first common transfer chamber 26. It is preventing. The reason is that the fifth and sixth processing chambers 24e and 24f are used to prevent the corrosive TiCl 4 gas remaining in the processing chamber from entering the first common transfer chamber 26. Claim is a first common transfer chamber 26 that, an atmosphere of an inert gas such as noble gas or N 2 gas of the Ar pressure at a significantly lower pressure than the atmospheric pressure.

When the gate valve G between any of the first to fourth load lock chambers 28a to 28d and the first common transfer chamber 26 is opened to communicate with each other, the pressure in the first common transfer chamber 26 is higher than the pressure in the first common transfer chamber 26. The pressure in the load lock chamber communicated with this is increased so that the atmosphere always flows from the load lock chamber into the first common transfer chamber 26. Thus, even if corrosive gas is present in the first common transfer chamber 26, This prevents it from flowing into the loadlock chamber. Moreover, in this processing system 176, the processing chamber corresponding to the 4th processing chamber 24d which performs the pre-cleaning process provided in the processing system 22 of FIG. 1 is not provided.

The 7th process chamber 24g connected to the 2nd common conveyance chamber 172 is a process chamber which forms a Ru film by the thermal CVD method, and the thermal film processing chamber 88 as shown in FIG. 3 is used for this. The eighth processing chamber 24h is a processing chamber for forming a Ti film by sputtering using Ti metal as the metal target.

The ninth process chamber 24i is a process chamber for forming a Cu film by sputtering using Cu metal as a metal target.

Even if the processing system 170 shown in FIG. 9 is used, the film forming method similar to each film forming method performed using the processing system 22 shown in FIG. 1 can be executed. However, the pre-cleaning process is not performed in the processing system 170. The movement of the wafer W between the first and second common transfer chambers 26 and 172 is performed through the third and fourth load lock chambers 28c and 28d. In the processing system 22 of FIG. 1, the Ti film was deposited in one processing chamber and the TiN film was formed by plasma nitriding on the surface of the Ti film. However, in the processing system 170 shown in FIG. 9, the Ti film is formed here. And TiN film formation are performed by plasma CVD processing in another processing chamber, that is, in the fifth processing chamber 24e and thermal CVD processing in the sixth processing chamber 24f, respectively.

In the processing system 170, since the fifth and sixth processing chambers 24e and 24f using the corrosive gas, for example, TiCl 4 gas, are connected to only one common transfer chamber 26, the seventh to ninth processing chambers ( 24g, 24h, 24i) are reliably prevented from being adversely affected by the corrosive gas.

Moreover, in each said embodiment, although the barrier layer 12 of the two-layer structure which consists of Ti film 8 and TiN film 10 is formed as shown to FIG. 5 (c), it is limited to this. Alternatively, a barrier layer having a single layer structure composed of only the Ti film 8 without the TiN film 10 may be formed. In this case, it is only necessary to omit the formation process of the TiN film 10 by the above-mentioned film-forming method. In this case, when using the processing system 170 shown in FIG. 9, the Ti film may be formed by sputtering in the eighth processing chamber 24h, thereby eliminating the need for using a highly corrosive TiCl 4 gas.

The object to be processed is not limited to the semiconductor wafer, but may be a glass substrate, an LCD substrate, a ceramic substrate, or the like.

Claims (12)

  1. In the film-forming method which forms a thin film in the to-be-processed object in which the insulating layer which has a recessed part was formed in the surface,
    A barrier layer forming step of forming a barrier layer containing Ti on a surface of the workpiece including a surface in the recess;
    A seed layer forming step of forming a seed layer including Ru by CVD (Chemical Vapor Deposition) on the barrier layer;
    An auxiliary seed layer forming process of forming an auxiliary seed layer containing Cu by sputtering on the seed layer.
    Formation method comprising the.
  2. The method of claim 1,
    The barrier layer is formed of a Ti film.
  3. The method of claim 1,
    And the barrier layer is formed of a stacked Ti film and a TiN film.
  4. The method of claim 1,
    And a pre-cleaning step for pre-cleaning the target object before the barrier layer forming step.
  5. The method of claim 1,
    Each said process is performed continuously in a vacuum, without exposing the said to-be-processed object to air | atmosphere. The film-forming method characterized by the above-mentioned.
  6. The method of claim 1,
    And a plating step for padding the recess with Cu is performed after the auxiliary seed layer forming step.
  7. 7. The method according to any one of claims 1 to 6,
    And the recess is formed of at least one of a via hole, a through hole, a contact hole, and a trench.
  8. The method of claim 7, wherein
    A film forming method, wherein the concave portion has a diameter or width of 100 nm or less.
  9. In the processing system for forming a thin film on the surface of the workpiece,
    A processing chamber for forming a thin film containing Ti on the surface of the target object;
    A processing chamber for forming a thin film containing Ru on the surface of the target object;
    A processing chamber for forming a thin film containing Cu on the surface of the target object;
    At least one common conveying chamber connected to at least one of the respective processing chambers and capable of vacuum suction;
    A transport mechanism provided in the common transport chamber and transporting the object to be processed between the processing chambers;
    Control unit for controlling the processing system to execute the film forming method according to claim 1
    Processing system comprising a.
  10. The method of claim 9,
    The process target body is provided with the process chamber which pre-cleans-processes,
    The control unit is configured to control the processing system so that the film forming method according to claim 7 is executed.
    Processing system.
  11. A processing chamber for forming a thin film containing Ti on the surface of the workpiece,
    A processing chamber for forming a thin film containing Ru on the surface of the target object;
    A processing chamber for forming a thin film containing Cu on the surface of the target object;
    At least one common conveying chamber connected to at least one of the respective processing chambers and capable of vacuum suction;
    A transport mechanism provided in the common transport chamber and transporting the object to be processed between the processing chambers;
    Control unit that controls the operation of the entire processing system
    In forming a thin film on the surface of the to-be-processed object by the processing system provided with the,
    Storing a computer readable program for causing the control unit to execute a control operation so that the film forming method according to claim 1 is executed
    Storage medium characterized in that.
  12. A processing chamber for forming a thin film containing Ti on the surface of the workpiece,
    A processing chamber for forming a thin film containing Ru on the surface of the target object;
    A processing chamber for forming a thin film containing Cu on the surface of the target object;
    Process chamber which performs pre-cleaning process to the said to-be-processed object
    And
    At least one common conveying chamber connected to at least one of the respective processing chambers and capable of vacuum suction;
    A transport mechanism provided in the common transport chamber and transporting the object to be processed between the processing chambers;
    Control unit that controls the operation of the entire processing system
    In forming a thin film on the surface of the to-be-processed object by the said processing system provided with,
    Storing a computer readable program for causing the control unit to execute a control operation so that the film forming method according to claim 4 is executed
    Storage medium characterized in that.
KR1020097026131A 2007-06-28 2008-06-26 Filming method, and treating system KR101396624B1 (en)

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WO2012109438A2 (en) * 2011-02-10 2012-08-16 Applied Materials, Inc. Seed layer passivation
WO2012109438A3 (en) * 2011-02-10 2012-10-04 Applied Materials, Inc. Seed layer passivation
US8357599B2 (en) 2011-02-10 2013-01-22 Applied Materials, Inc. Seed layer passivation

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KR101396624B1 (en) 2014-05-16
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WO2009001896A1 (en) 2008-12-31
JP2010192467A (en) 2010-09-02
TWI445130B (en) 2014-07-11
CN101689490B (en) 2011-12-21

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