KR20090045101A - Data processing apparatus and method - Google Patents

Abstract

The data processing apparatus communicates data bits via a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processing apparatus performs parity interleaving on LDPC encoded data bits obtained by performing LDPC interleaving according to a parity check matrix of an LDPC code including a parity matrix corresponding to a parity bit of a low density parity check (LDPC) code. The parity bits of the LDPC encoded data bits are interleaved to different parity bit positions, including a parity interleaver operable to do so. The parity matrix has a stepwise structure. A mapping unit maps the parity interleaved bits to data symbols corresponding to modulation symbols of a modulation scheme of OFDM subcarrier signals. The symbol interleaver is configured to input a predetermined number of data symbols for mapping to OFDM subcarrier signals into a symbol interleaver memory and to read data symbols for OFDM subcarrier signals from the interleaver memory to achieve mapping. do. The read is in a different order than the input, the order being determined from the address set, and the data symbols interleaved in the subcarrier signal. The address set is generated by an address generator optimized to interleave data symbols into subcarrier signals of OFDM carrier signals for certain operating modes of an OFDM system, such as the 32K operating mode for DVB-T2 or DVB-C2.

Data processing apparatus, OFDM symbol, de-mapping unit, inverse exchanger, de-interleaver

Description

DATA PROCESSING APPARATUS AND METHOD}

The present invention relates to a data processing method and apparatus for communicating data bits via a plurality of subcarrier signals of Orthogonal Frequency Division Multiplexed (OFDM) symbols.

Embodiments of the present invention may provide an OFDM transmitter.

Digital Video Broadcasting-Terrestrial (DVB-T) utilizes OFDM to deliver data representing video images and sound to receivers via broadcast wireless communications signals. Two modes are known in the DVB-T standard, known as 2k and 8k modes. The 2k mode provides 2048 subcarriers, while the 8k mode provides 8192 subcarriers. Similar to the Digital Video Broadcasting-Handheld (DVB-H) standard, a 4k mode with 4096 subcarriers has been provided.

Error correction coding schemes, such as LDPC / BCH coding proposed for DVB-T2, are better performed when noise and drop in symbol values resulting from communication are uncorrelated. Terrestrial broadcast channels can be corrupted from fading correlated in both time and frequency domains. As such, by dividing the encoded data bits into different data symbols and dividing the communication of the data symbols into different subcarrier signals of the OFDM symbol as much as possible, the performance of the error correction coding scheme can be improved.

In order to improve the integrity of data delivered using DVB-T or DVB-H, a symbol interleaver is used to interleave the input data symbols when the symbols are mapped to subcarrier signals of OFDM symbols. It is known to provide. Configurations for the 2k mode and the 8k mode for generating addresses to achieve mapping are disclosed in the DVB-T standard. Similar to the 4k mode of the DVB-H standard, a configuration for generating an address for mapping is provided, and an address generator for implementing this mapping is disclosed in European Patent Application No. 04251667.4. The address generator includes a linear feedback shift register and a permutation circuit that operate to generate a pseudo random bit sequence. The substitution circuit replaces the order of the contents of the linear feedback shift register to generate an address. The address provides an indication of the memory location of the interleaver memory for writing an input data symbol to the interleaver memory or for reading the input data symbol from the interleaver memory for mapping of the OFDM symbol to one of the subcarrier signals. Similarly, the address generator of the receiver is configured to generate an address of the interleaver memory for writing the received data symbols to the interleaver memory or for reading the data symbols from the interleaver memory to form an output symbol stream.

In accordance with the more developed digital video broadcast terrestrial standard known as DVB-T2, improved communication of data bits, and more specifically, interleaving encoded data bits and data symbols into subcarrier signals of OFDM symbols with LDPC codes It is desirable to provide a configuration.

According to the present invention, a data processing apparatus for communicating data bits via a predetermined number of subcarrier signals of an OFDM symbol is provided. The data processing apparatus includes a parity interleaver operable to perform parity interleaving on LDPC encoded data bits obtained by performing LDPC interleaving according to a parity check matrix of an LDPC code including a parity matrix corresponding to a parity bit of an LDPC code. In addition, the parity bits of the LDPC code are interleaved with different parity bit positions. The parity matrix has a stepped structure. The mapping unit maps the parity interleaved bits into data symbols corresponding to modulation symbols of the modulation scheme of the OFDM subcarrier signals. The symbol interleaver is configured to input a predetermined number of data symbols for mapping to OFDM subcarrier signals into a symbol interleaver memory and to read data symbols for OFDM subcarrier signals from the interleaver memory to achieve mapping. do. The read is in a different order than the input, the order being determined from the address set, and the data symbols interleaved in the subcarrier signal.

An address generator is operable to generate an address set, and an address is generated for each of the data symbols to represent a subcarrier signal of one of the subcarrier signals to which the data symbol is mapped.

The address generator,

A linear feedback sheet register comprising a predetermined number of register stages and operable to generate a pseudo-random bit sequence in accordance with a generation polynomial;

A substitution circuit operable to receive the contents of the seat register stage and replace the bits present in the register stage according to the substitution code, thereby forming an address of one of the OFDM subcarriers, and

And a control unit operable with the address checking circuit to regenerate the address when the generated address exceeds a predetermined maximum valid address.

R'_i-1[1]

R'_i-1[2]

R'_i-1[12]의 선형 피드백 시트프 레지스터에 대한 생성 다항식을 갖는 14개의 레지스터 스테이지를 갖고, 치환 코드는, 하나의 추가 비트와 함께, 이하의 표에 따라서 n번째 레지스터 스테이지 R'_i[n]에 존재하는 비트로부터 i번째 데이터 심볼에 대한 15 비트 어드레스 R_i[n]을 형성한다:In one example, where the OFDM symbol is generated according to the 32K mode, the predetermined maximum valid address is approximately 32000, and the linear feedback sheet register is _R'i [13] = _R'i-1 [0].

R ' _i-1 [1]

R ' _i-1 [2]

R _'i-1 having 14 register stages with a generator polynomial for the linear feed back sheet print register of [12], substitution code, with one additional bit, in accordance with the following Table n-th register stage R' _i From the bits present in [n] form a 15 bit address R _i [n] for the i th data symbol:

R ' _i bit position 13 12 11 10 9 8 7 6 5 4 3 2 One 0 R _i bit position 6 5 0 10 8 One 11 12 2 9 4 3 13 7

In other modes, the maximum effective address, the number of stages of the linear feedback sheet register, the generation polynomial, and the substitution code can be adapted according to the predetermined number of subcarrier signals per OFDM symbol in each mode.

Embodiments of the present invention include a bit interleaver coupled with a symbol interleaver to improve the performance of an OFDM communication system utilizing LDPC error correction encoding. The bit interleaver includes a substituting unit which performs a substituting process of substituting code bits of the LDPC code when two or more code bits of the LDPC code are transmitted and received as one symbol, and the information matrix corresponding to the information bits of the LDPC code. The plurality of code bits corresponding to the value of 1 in any row of are not combined into the same symbol.

The data processing device may be a standalone device or may be an internal block included in a device such as a transmitter or in another embodiment a receiver.

LDPC codes can provide high error correction performance in communication paths other than Additive White Gaussian Noise (AWGN) channels, and are superior to convolutional code or Reed Solomon (RS) convolutional codes. Do. This may be provided to a communication channel that exhibits an error burst causing the cancellation. Accordingly, there is a need to provide a method of increasing the resistance to burst error or cancellation while maintaining the performance of the AWGN communication path.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and by connecting a bit interleaver and a symbol interleaver for LDPC encoded data bits, data which can increase resistance to errors in code bits of an LDPC code such as burst error or erasure can be increased. A processing apparatus and method are provided.

That is, according to an embodiment of the present invention, parity interleaving is performed on an LDPC code obtained by performing LDPC encoding according to a parity check matrix including a parity matrix of a stepwise structure corresponding to a parity bit of an LDPC code, thereby performing Parity bits are interleaved with different parity bit positions.

In the application investigated in the present invention, various modes of operation of OFDM systems have been found. For example, to provide even sparser development of DVB transmitters in a single frequency network, it has been proposed to provide a 32k mode. In order to implement the 32k mode, a symbol interleaver must be provided for mapping the input data symbols to the subcarrier signals of the OFDM symbols.

Embodiments of the present invention may provide a data processing apparatus operable as a symbol interleaver for mapping data symbols to be delivered in OFDM symbols having approximately 32,000 subcarrier signals. In one embodiment, the number of subcarrier signals may be substantially between 24,000 and 32,768. The OFDM symbol also includes a pilot subcarrier configured to carry a known symbol, and the predetermined maximum effective address depends on the number of pilot subcarrier symbols present in the OFDM symbol. As such, 32k mode may be provided for DVB standards such as, for example, DVB-T2, DVB-Cable2, DVB-T, or DVB-H.

The mapping data symbol to be transmitted in the subcarrier signal of the OFDM symbol, where the number of subcarrier signals is approximately 32,000, needs to be simulated and tested to set the permutation order and the appropriate generation polynomial for the linear feedback sheet register. This represents a technical problem. This is because the mapping requires that symbols be interleaved into subcarrier signals, with the intention that successive symbols from the input data stream are divided in frequency to the maximum possible amount in order to optimize the performance of the error correction coding scheme.

As described below, it has been found from simulation performance analysis that the resulting polynomials for linear feedback sheet registers, together with the substitution circuit sequence described above, provide excellent performance. The symbol for 32k mode is also provided by changing the tap of the generation polynomial and substitution order for the linear feedback sheet register, thereby providing an address generation for each of the 2k mode, 4k mode and 8k mode. The interleaver can be implemented cost effectively. In addition, the transmitter and receiver can be changed among 1K mode, 2K mode, 4K mode, 8K mode, 16K mode and 32K mode by changing the generation polynomial and the substitution order. It may be implemented in software (or by embedded signaling) and may be implemented flexibly.

Various aspects and features of the invention are defined in the appended claims. Another aspect of the invention includes a data processing apparatus operable to communicate data bits via a predetermined number of subcarrier signals of an OFDM symbol, as well as a transmitter.

1 provides an example block diagram of an OFDM transmitter that may be used to transmit video images and audio signals, for example, in accordance with the DVB-T2 standard. In Figure 1, the program source generates data to be transmitted by the OFDM transmitter. The video coder 2, the audio coder 4 and the data coder 6 generate video, audio and other data to be transmitted which is supplied to the program multiplexer 10. The output of the program multiplexer 10 forms a multiplexed stream with video, audio and other information required to communicate the data. The multiplexer 10 provides a stream on the access channel 13. There may be multiplexed streams feeding different branches A, B, and the like. For clarity, only branch A will be described.

As shown in FIG. 1, OFDM transmitter 11 receives a stream at multiplexer adaptation and energy spreading block 20. The multiplexer adaptation and energy spreading block 20 randomly extracts data and supplies appropriate data to a forward error correction encoder 21 that performs error correction encoding of the stream. Bit interleaver 22 is provided to interleave the encoded data bits, which in the example of DVB-T2 are LDPC encoder outputs. The output from the bit interleaver 22 is fed to a bit into constellation mapper 26 which maps the group of bits to an array point to be used to convey the encoded data bits. The output from the bit array mapper 26 is an array point label representing the real and imaginary components. The constellation point label represents a data symbol formed from two or more bits, depending on the modulation scheme used. These will be referred to as data cells. This data cell passes through a time interleaver 30 which interleaves data cells from multiple LDPC code words. The data cells from time interleaver 30 are then fed to a modulation and frame builder 27 that maps the data cells to modulation symbols for transmission.

The data cell is received in the modulator 27 by the frame builder 32 via another channel 31, and the data cell is generated by branch B of FIG. Frame builder 32 then forms a plurality of data cells in the sequence to be conveyed in the OFDM symbol, where the OFDM symbol comprises a plurality of data cells, each data cell being mapped to one of the subcarriers. The number of subcarriers will depend on the operating mode of the system, which may include one of 1k, 2k, 4k, 8k, 16k, or 32k, each of which may be a different number of subcarriers, for example, in accordance with the table below. To provide.

mode Subcarrier 1K 756 2K 1512 4K 3024 8K 6048 16K 12096 32K 24192

      Number of subcarriers adapted from DVB-T / H

Thus, in one example, the number of subcarriers for 32k mode is 24,192. In a DVB-T2 system, the number of subcarriers per OFDM symbol may vary depending on the number of other reserved carriers and pilots. Therefore, in DVB-T2, unlike DVB-T, the number of subcarriers for carrying data is not fixed. The broadcaster can select one of the operating modes from 1k, 2k, 4k, 8k, 16k, 32k, each providing a range of subcarriers for data per OFDM symbol, the maximum number available for each of these modes being 1024, 2048, 4096, 8192, 16384, 32768. In DVB-T2, a physical layer frame is composed of a plurality of OFDM symbols. In general, a frame begins with one or more preamble or P2 OFDM symbols, followed by a number of payload forwarding OFDM symbols. The end of the physical layer frame is represented by a frame closure symbol. For each mode of operation, the number of subcarriers may be different for each symbol type. In addition, this may vary depending on whether bandwidth extension is selected, whether tone reservation is enabled, and which pilot subcarrier pattern is selected. Generalization of a specific number of subcarriers per OFDM symbol is difficult. However, the frequency interleaver for each mode may interleave any symbol whose number of subcarriers is less than or equal to the maximum effective number of subcarriers for a given mode. For example, in the 1k mode, the interleaver may operate on symbols with a number of subcarriers of 1024 or less and for a 16k mode, on an number of subcarriers of 16384 or less.

Then, the sequence of data cells to be delivered in each OFDM symbol is sent to the symbol interleaver 33. OFDM symbols are then generated by the OFDM symbol builder block 37 which introduces the pilot and synchronization signals supplied from the pilot and embedded signal formers 36. The OFDM modulator 38 then forms an OFDM symbol in the time domain, which is fed to a guard insertion processor 40 for generating guard intervals between the symbols and then a digital to analog converter ( 42) and finally from antenna 46 to the RF amplifier in RF front end 44 for final broadcast by the OFDM transmitter.

An embodiment of the present invention provides an OFDM communication system including a bit interleaver for interleaving bits encoded with an LDPC encoder, together with a symbol interleaver, wherein the symbol interleaver is capable of OFDM symbols representing one or more interleaved encoded bits. Interleaving with a symbol subcarrier signal. The bit interleaver and the symbol interleaver according to the exemplary embodiment are both described in the following paragraphs, and the bit interleaver described in LDPC encoding is described first.

Bit Interleaver for LDPC Encoding

LDPC error correction code

LDPC codes have high error correction performance and are used in satellite digital broadcasting such as DVB-S.2, which has been used in Europe (see, eg, DVB-S.2: ETSI EN 302 307 V1.1.2 (2006-06)). Recently used in a communication scheme including a. The application of LDPC codes to next-generation terrestrial digital broadcasting is also discussed.

Recent studies show that, similar to turbo codes, the performance of LDPC codes approaches the shannon limit as the code length increases. Since the LDPC code has a characteristic that the minimum distance is proportional to the code length, the LDPC code has excellent block error probability characteristics, and an error floor, which is a phenomenon observed in relation to decoding characteristics such as a turbo code, almost occurs. It does not have the advantage.

Now, we will look at these LDPC codes in detail. LDPC codes are linear codes. The LDPC code is not necessarily binary, but will be described below with reference to the binary LDPC code.

The most important characteristic of an LDPC code is that the parity check matrix that defines each LDPC code is a sparse matrix with a very small number of elements " 1 ", i.

2 shows an example parity check matrix H of an LDPC code.

Each column of the parity check matrix H of FIG. 2 has a weight of 3 (ie, three "1" elements), and each row has a weight of six (ie six "1" elements).

The encoding based on the LDPC code (ie, LDPC encoding) is performed, for example, by calculating the generation matrix G based on the parity check matrix H and multiplying the generation matrix G by the information bits to generate a codeword (LDPC code). .

Specifically, the LDPC encoder first calculates a generation matrix G that satisfies the equation GH ^T = 0 using the transpose matrix H ^T of the parity check matrix H. Here, if the generation matrix G is a K × N matrix, the encoder multiplies the generation matrix G by a K-bit information bit sequence (vector u) to generate an N-bit codeword c (= uG). The codeword (LDPC code) generated by the encoder is received at the receiving side via the communication path.

The LDPC code can be decoded by the message transfer algorithm proposed by Gallager and by the proposed "probabilistic decoding algorithm". The message passing algorithm uses a belief propagation on a Tanner graph that includes a variable node (also referred to as a message node) and a check node. In the following description, the variable node and check node will each be briefly appropriately referred to as a "node."

3 shows a procedure for decoding an LDPC code.

Thereafter, the real value representing the probability that the i th code bit of the LDPC code (codeword) received at the receiving side has a value of "0" as a log likelihood ratio (LLR) is suitably. It is referred to as the received value u ₀₁ . The message output from the check node is also referred to as u _j , and the message output from the variable node is referred to as v _i .

LDPC codes are decoded in the following manner. First, as shown in Fig. 3, in step S11, an LDPC code is received, the message (check node message) u _j is initialized to " 0 ", and the variable k having an integer value as a counter of mutual processing is " Initialized to 0 ". The procedure then proceeds to step S12. In step S12, the calculation (variable node calculation) represented by equation (1) is performed based on the received value u _0i obtained by receiving the LDPC code, so that a message (variable node message) v _i is obtained, and then into equation (2). The calculation expressed (check node calculation) is performed based on the message v _i , whereby the message u _j is obtained.

D _v and d _c in Equations 1 and 2 are arbitrary selectable parameters representing the respective numbers of 1s in the vertical (column) and horizontal (row) directions of the parity check matrix H. to be. For example, for the (3,6) code, d _v = 3 and d _c = 6.

Respective ranges for the calculation in the variable node calculation of Equation 1 and the check node calculation in Equation 2 are 1 to d _v -1 and 1 to d _c -1, which are edges that output a message (ie, a variable). This is because the message received from the line connecting the node and the check node to each other is excluded from each calculation of the equations (1) and (2). Indeed, the check node calculation of equation (2) is, as shown in equation (4), of the function R (v ₁ , v ₂ ) represented by equation (3) defined as one output for two inputs v ₁ and v ₂ . This is done recursively using previously generated tables.

In step S12, the variable k is incremented by " 1 ", and the procedure proceeds to step S13. In step S13, it is determined whether the variable k is greater than the repetition number C of the predetermined decoding. If it is determined in step S13 that the variable k is not larger than C, the procedure returns to step S12 to repeat the same processing.

If it is determined in step S13 that the variable k is greater than C, the procedure proceeds to step S14 to perform the calculation represented by Equation 5 to obtain and output the message v _i as the final decoding result. The LDPC code decoding procedure then ends.

Here, unlike the variable node of Equation 1, the calculation of Equation 5 is performed using the message u _j from all edges connected to the variable node.

4 shows an exemplary parity check matrix H of a (3,6) LDPC code having a code rate of 1/2 and a code length of 12.

As the parity check matrix H of FIG. 2, the parity check matrix H of FIG. 4 has a column weight of 3 and a row weight of 6.

FIG. 5 shows a Tanner graph of the parity check matrix H of FIG. 4.

In Fig. 5, "+" represents a check node and "=" represents a variable node. The check node and the variable node correspond to the rows and columns of the parity check matrix H, respectively. Each connecting line connecting the pair of check nodes and variable nodes is an edge corresponding to element "1" of parity check matrix H.

Specifically, if the j th row element and the i th column element of the parity check matrix are "1", the i th variable node "=" (counting from the top) and the j th check node "+" (counting from the top) are shown in FIG. 5. Is connected through the edge of the. An edge indicates that the code bit corresponding to the variable node has a limit corresponding to the check node.

The sum product algorithm, which is an LDPC code decoding algorithm, repeatedly performs variable node calculation and check node calculation.

6 illustrates variable node calculations performed at a variable node.

The message v _i corresponding to the computational edge is obtained according to the variable node calculation of equation (1) using the messages u ₁ and u ₂ and the received value u _0i from the remaining edges connected to the variable node. Messages corresponding to other edges are obtained in the same way.

7 illustrates check node calculation performed at the check node.

Equation 2 for the check node calculation is axb = exp {ln (| a |) + ln (| b |)} × sign (a) × sign (b), where x≥0. The sign (x) is 1 and when x <0, the sign (x) is -1).

Further, if the function φ (x) = ln (tanh (x / 2)) is defined when x≥0, the equation φ- ¹ (x) = 2tanh- ¹ (e ^-x ) is satisfied and accordingly the equation 6 may be rearranged into equation (7).

At the check node, check node calculation in equation (2) is performed according to equation (7).

That is, at the check node, the message u _j corresponding to the computational edge receives messages v ₁ , v ₂ , v ₃ , v ₄ , and v ₅ from the remaining edges connected to the check node as shown in FIG. 7. It is obtained according to the check node calculation of Equation (7). Messages corresponding to other edges are obtained in the same way.

The function φ (x) of Equation 7 is equal to φ (x) = ln ((e ^x +1) / (e ^x- 1)) and φ (x) = φ- ¹ (x) when x> 0. It can also be expressed as: If the functions φ (x) and φ- ¹ (x) are embedded in hardware, they can be embedded using the same lookup table (LUT).

Although LDPC codes are known to exhibit very good performance in AWGN communication paths, in recent years, LDPC codes offer higher error correction performance in other communication paths than conventional convolutional codes or conjunctive Reed Solomon (RS) -convolutional codes. It is also known to have.

That is, if a code having a good performance in the AWGN communication path is selected, the selected code generally shows superior performance in comparison with other codes in other communication paths.

For example, as an LDPC code is applied to terrestrial digital broadcasting, a bit interleaver that combines the LDPC code defined in the DVB-S.2 specification and the modulation scheme defined in the DVB-T specification and interleaves the code bits of the LDPC code. Is provided between the LDPC encoder and modulator to improve the performance of the LDPC code of the AWGN communication path.

However, erasure or burst errors can occur in a communication path assumed to be terrestrial. For example, in an Orthogonal Frequency Division Multiplexing (OFDM) system, the Desired to Undesired Ratio (D / U) becomes 0 dB, so in a multipath environment where the main path power as the desired power is the same as the echo power as the undesired power. The delay of the echo, another path, can cause certain symbols to be erased (i.e., the power source drops to zero).

If the D / U is 0 dB, then all OFDM symbols at a particular time are also erased (i.e. power supply) due to the Doppler frequency of the flutter, which is the communication path to which the Doppler frequency is applied and an echo with a delay of "0" is added. Will fall to zero).

In addition, burst errors may occur due to undesirable conditions or unstable power in the wire from the antenna to the receiver.

In the related art, error correction codes with good performance in AWGN communication paths are also frequently used in communication paths where burst errors or cancellations occur as described above.

On the other hand, if the LDPC code is decoded, the variable node corresponding to the code bits of the LDPC code as well as the column of the parity check matrix H is added to the code bits (received value u _0i ) of the LDPC code as shown in FIG. Calculated according to Equation 1 associated with Thus, the accuracy of the acquired message is reduced if an error occurs in the code bits used in the variable node calculation.

In addition, when the LDPC code is decoded, the test node is calculated according to Equation 7 using the message obtained at the variable node connected to the test node. Therefore, the decoding performance is lowered if an error including erasing occurs simultaneously in a plurality of variable nodes (a plurality of code bits of corresponding LDPC codes) connected to each of a plurality of check nodes.

More specifically, for example, if two or more variable nodes connected to a check node are erased at the same time, the check node may send a message having a probability of "0" equal to the probability of "1" to all variables connected to the check node. Return to the node. In this case, a check node that returns a message with different probability of "0" and "1" does not help one decoding process, which is a set of variable node calculation and check node calculation. This increases the number of decoding processes required, thereby lowering the decoding performance, and increases the power consumption of the receiver performing LDPC code decoding.

Accordingly, there is a need to provide a method of increasing the resistance to burst error or cancellation while maintaining the performance of the AWGN communication path.

Here, a bit interleaver interleaving code bits of the LDPC code is provided between the LDPC encoder and the modulator to improve the performance of the LDPC code in the AWGN communication path as described above, and the bit interleaver is a plurality of variables connected to the test node. If the interleaving is designed to reduce the probability of an error occurring at the node (a plurality of code bits of the corresponding LDPC code), decoding performance can be improved.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a data processing apparatus and method capable of increasing resistance to errors in code bits of an LDPC code such as burst error or erase.

According to an embodiment of the present invention, a data processing apparatus for interleaving data performs parity interleaving on an LDPC code obtained by performing LDPC encoding according to a parity check matrix including a parity matrix corresponding to a parity bit of an LDPC code. Parity interleaver, wherein the parity matrix has a stepped structure, wherein the parity bits of the LDPC code are interleaved with different parity bit positions.

A data processing method of a data processing apparatus for interleaving data according to an embodiment of the present invention, the data processing apparatus is obtained by performing LDPC encoding according to a parity check matrix including a parity matrix corresponding to the parity bits of the LDPC code Parity interleaving in the LDPC code, wherein the parity matrix has a stepped structure, wherein the parity bits of the LDPC code are interleaved to different parity bit positions.

That is, according to an embodiment of the present invention, parity interleaving is performed on an LDPC code obtained by performing LDPC encoding according to a parity check matrix including a parity matrix of a stepped structure corresponding to a parity bit of an LDPC code, thereby performing an LDPC code. The parity bit of is interleaved with different parity bit positions.

The data processing device may be a single device or an internal block included in the device.

Detailed Description of Example Bit Interleaver

FIG. 8 shows in more detail the parts of the transmitter shown in FIG. 1 and shows the operation of the bit interleaver. The LDPC encoder 21 will now be described in detail. The LDPC encoder 21 encodes target data including information bits corresponding to the target data into LDPC encoded data bits according to the parity check matrix, and the parity matrix corresponding to the parity bits of the LDPC code has a stepped structure.

Specifically, the LDPC encoder 21 encodes target data with an LDPC code defined according to the DVB-S.2 specification, for example, and outputs the LDPC code.

The LDPC code defined according to the DVB-S.2 specification is an Irregular Repeat Accumulate (IRA) code, and the parity matrix of the parity check matrix of the LDPC code has a stepped structure. Details of the parity matrix and its stepwise structure will be described later. Examples of IRA codes are described in H.Jin, A. Khandekar, and R.J., of the Second International Symposium Bulletin on Turbo Codes and Related Topics, September 2000. McEliece's "Irregular Repeat-Accumulate Codes".

The LDPC code output from the LDPC encoder 21 is provided to the bit interleaver 22.

The bit interleaver 22 is a data processing device for interleaving data, and includes a parity interleaver 23, a column twist interleaver 24, and a demultiplexer 25.

The parity interleaver 23 performs parity interleaving in the LDPC code from the LDPC encoder 21 to interleave the parity bits of the LDPC code to different parity bit positions, and provide the parity interleaved LDPC code to the column twist interleaver 24. .

The thermal twist interleaver 24 performs thermal twist interleaving on the LDPC code from the parity interleaver 23 and then provides the thermal twist interleaved LDPC code to the demultiplexer 25.

Therefore, the LDPC code is transmitted after two or more code bits of the LDPC code are mapped to one orthogonally modulated symbol through the mapping section 26 described later.

The column twist interleaver 24 performs a substitution (e.g., column twist interleaving) process in the code bits of the LDPC code received from the parity interleaver 23, so that the parity check matrix used by the LDPC encoder 21 is performed. Do not allow a plurality of code bits of the LDPC code corresponding to "1" in any row of to be mapped to one symbol.

The demultiplexer 25 performs a reordering process on the LDPC code received from the column twist interleaver 24 so that the positions of two or more code bits of the LDPC code to be mapped to one symbol are rearranged, thereby resisting the AWGN. After this increased LDPC code is obtained, the obtained LDPC code is provided to the mapping unit 26.

The mapping section 26 maps two or more code bits of the LDPC code from the demultiplexer 25 to each signal point, which is used by the quadrature modulator 27 to perform orthogonal modulation (multi-value modulation). Is determined according to the modulation scheme.

More specifically, the mapping unit 26 converts the LDPC code from the demultiplexer 25 into a symbol (symbol value) represented by a signal point determined according to the modulation scheme of the IQ plane (IQ array). The plane is defined as the I axis representing the I component in the same phase as the carrier wave, and the Q axis representing the Q component orthogonal to the carrier wave.

The modulation scheme used by the OFDM transmitter of FIG. 1 to perform orthogonal modulation includes modulation schemes defined in the DVB-T specification, such as Quadrature Phase Shift Keying (QPSK), 16 Quadrature Amplitude Modulation (QAM). Quadrature Amplitude Modulation), 64QAM, 256QAM, 1024QAM, 4096QAM. One of the modulation schemes that quadrature modulator 27 uses to perform orthogonal modulation is preset, for example, through operation by an operator operating the transmitter of FIG. Examples of other modulation schemes that quadrature modulator 27 uses to perform orthogonal modulation include 4 Pulse Amplitude Modulation (4PAM).

The symbols obtained in the mapping section 26 are provided to a time interleaver for interleaving different LDPC code words into different OFDM symbols. The output of the time interleaver 30 is supplied to the frame builder of FIG. The rest of the transmitter shown in FIG. 1 generates a modulated signal by performing orthogonal modulation of the subcarrier signal of the OFDM symbol received from the mapping unit 26, and then transmits the modulated signal.

FIG. 9 shows the parity check matrix H used by the LDPC encoder 21 of FIG. 8 for LDPC encoding.

The parity check matrix H has a low-density generation matrix (LDGM) structure and includes an information matrix H _A as a left component and a parity matrix H _T as a right component "H = [H _A | H _T ] ", Where the information matrix H _A corresponds to the information bits of the code bits of the LDPC code, and the parity matrix H _T corresponds to the parity bits.

Here, the number of information bits and the number of parity bits among the code bits of one LDPC code (one codeword) are defined by information length K and parity length M, and the number of code bits is code length N (= K). + M).

The information length K and the parity length M of the LDPC code of code length N are determined based on the code rate. Thus, parity check matrix H is an M × N matrix. The information matrix H _A is an M × K matrix, and the parity matrix H _T is an M × M matrix.

Fig. 10 shows the parity matrix H _T of the parity check matrix H of the LDPC code defined in the DVB-S.2 specification.

The parity matrix H _T of the parity check matrix H of the LDPC code defined in the DVB-S.2 specification has a stepped structure so that elements of " 1 " of the parity matrix H _T are arranged stepwise as shown in FIG. The first row of parity check matrix H has a weight of 1 and the remaining rows have a weight of 2.

The LDPC code of the parity check matrix H having the parity matrix H _T of the stepped structure can be easily generated using the parity check matrix H.

More specifically, it is assumed that row vector c represents an LDPC code (codeword), and C ^T represents a column vector obtained by transposing the row vector. In addition, it is assumed that row vector A represents the information bit portion of row vector c, which is an LDPC code, and row vector T represents the parity bit portion.

In this case, the row vector c may be represented by the equation "c = [A | T]" having the row vector A as the left component and the row vector T as the right component, where the row vector A is assigned to the information bit. And the row vector T corresponds to a parity bit.

The parity check matrix H and the row vector c = [A | T] corresponding to the LDPC code must satisfy the equation “Hc ^T = 0”. Therefore, the value of each element of the row vector T corresponding to the parity bit included in the row vector c = [A | T] is equal to the parity matrix H _T of the parity check matrix H = [H _A | H _T ]. If it has a stepped structure as shown, it can be obtained sequentially by setting the elements of each row of the column vector Hc ^T of the equation " Hc ^T = 0 " to 0 in the order starting from the elements of the first row.

12A and 12B show the column weights defined in the DVB-S.2 specification and the parity check matrix H of the LDPC code.

That is, FIG. 111A shows the parity check matrix H of the LDPC code defined in the DVB-S.2 specification.

First, the KXth column of the parity check matrix H has a column weight of X, the next K3 column has a column weight of 3, the next M-1 column has a column weight of 2, and the last column has a column weight of 1. Has a weight.

Here, the sum of the number of columns "KX + K3 + M-1 + 1" is equal to the code length N.

In the DVB-S.2 specification, the number of columns KX, K3, and M (parity length) and the column weight X are defined as shown in FIG. 111B.

That is, FIG. 111B shows the number of columns KX, K3 and M and the column weight X for each code rate of the LDPC code defined in the DVB-S.2 specification.

Two LDPC codes with N code lengths of 64800 bits and 16200 bits, respectively, are defined in the DVB-S.2 specification.

In addition, as shown in FIG. 111B, eleven nominal code rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6. , 8/9, and 9/10 are defined for LDPC codes with code length N of 64800 bits, and 10 nominal code rates 1/4, 1/3, 2/5, 1/2, 3/5, 2 / 3, 3/4, 4/5, 5/6, and 8/9 are defined for LDPC codes whose code length N is 16200 bits.

In the LDPC code, it is known that the error rate of the code bit decreases as the weight of the column corresponding to the code bit of the parity check matrix H increases.

For the parity check matrix H defined in the DVB-S.2 specification shown in FIGS. 12A and 12B, as the ordinal number of the column decreases (ie, as the column approaches the left end of the parity check matrix H) As the weight of the column increases, and as the ordinal of the code bits decreases, the code bits of the LDPC code corresponding to the parity check matrix H become stronger (resistive) to errors (i.e., the first code bits are most resistant). Is larger, the weaker the error (i.e., the last code bit is weakest) as the ordinal of the code bit increases.

12A and 12B show the configuration of 16 symbols (corresponding signal points) on the IQ plane when 16QAM is performed in the quadrature modulator 27 of FIG.

That is, Fig. 13A shows a symbol of 16QAM.

In 16QAM, one symbol represents 4 bits and 16 (= 2 ⁴ ) symbols are provided. In addition, 16 symbols are arranged in a square of 4x4 symbols in the I and Q directions and center the origin of the IQ plane.

Here, when y ₀ , y ₁ , y ₂ , y ₃ represent four bits represented by one symbol of 16QAM, starting from the most significant bit MSB, the mapping unit 26 of FIG. Four code bits of the LDPC code are mapped to symbols of four bits y ₀ to y ₃ corresponding to four code bits when the modulation scheme is 16QAM.

13B shows the bit boundaries of four bits y ₀ to y ₃ represented by 16QAM symbols.

Here, the bit boundary of bit y _i (i = 0, 1, 2, 3 in FIGS. 12A and 12B) is the boundary between the symbol where bit y _i is "0" and the symbol where bit y _i is "1".

As shown in FIG. 13B, the boundary corresponding to the Q axis of the IQ plane is the only bit boundary for the first bits (ie, MSB) y ₀ of four bits y ₀ to y ₃ represented by 16QAM symbols, and IQ The boundary corresponding to the I axis of the plane is the only bit boundary for the second bit (ie, the second MSB) y ₁ .

Also, one boundary between the first and second columns (counting from the left) of the symbol of the 4x4 symbol, and the other boundary between the third and fourth columns, i.e., the two boundaries are added to the third bit y ₂ . Is the bit boundary.

Also, one boundary between the symbols of the first and second rows (counting from the top) of the 4x4 symbol and the other boundary between the third and fourth rows, i.e., the two boundaries are the fourth bit y _3. Is the bit boundary for.

Each bit y _i represented by a symbol is stronger for error as the number of symbols farther from the bit boundary increases, and weaker for error as the number of symbols near the bit boundary increases.

Bits that are resistant to errors (strong) are called "strong bits" and bits that are weak (sensitive) to errors are called "weak bits", as shown in Figures 12A and 12B. Similarly, the first bit (ie, MSB) y ₀ and the second bit y ₁ are strong bits, and the third bit y ₂ and fourth bit y ₃ are weak bits.

13 to 15 show the configuration of 64 symbols (corresponding signal points) on the IQ plane when 64QAM is performed in the quadrature modulator 27 of FIG.

In 64QAM, one symbol represents four bits and 64 (= 2 ⁶ ) symbols are provided. In addition, 64 symbols are arranged in a square of 8x8 symbols in the I and Q directions, and are centered on the origin of the IQ plane.

Here, when y ₀ , y ₁ , y ₂ , y ₃ , y ₄ , and y ₅ represent six bits represented by one symbol of 64QAM, substantially starting from the most significant bit (MSB), FIG. 8. The mapping unit 26 maps six code bits of the LDPC code to six bits y ₀ to y ₅ symbols corresponding to six code bits in the case where the modulation scheme is 64QAM.

FIG. 13 shows the bit boundaries of the first and second bits y ₀ and y ₁ of the six bits y ₀ to y ₅ represented by the 64QAM symbol, and FIG. 14 shows the bit boundaries of the third and fourth bits y ₂ and y ₃ . The bit boundaries are shown, and FIG. 15 shows the bit boundaries of the fifth and sixth bits y ₄ and y ₅ .

One bit boundary exists for each of the first and second bits y ₀ and y ₁ as shown in FIG. 14. Two bit boundaries exist for the third and fourth bits y ₂ and y _3, respectively, as shown in FIG. 14, and four bit boundaries exist for the fifth and sixth bits y ₄ and as shown in FIG. 15. y ₅ is present for each.

Thus, of the six bits y ₀ to y ₅ represented by the 64QAM symbol, the first and second bits y ₀ and y ₁ are the strongest bits, and the third and fourth bits y ₂ and y ₃ are the second strongest bits. , Fifth and sixth bits y ₄ and y ₅ are weak bits.

12, 13, and 15, it can be seen that in the case of bits of orthogonal modulated symbols, the more important bits are the strong bits and the less important bits are the weak bits.

The LDPC code output from the LDPC encoder 21 of FIG. 8 includes a code bit vulnerable to error and a code bit strong to error as described above with reference to FIG.

The bits of a symbol orthogonally modulated by the quadrature modulator 27 include strong and weak bits as described above with reference to FIGS. 12-15.

Thus, if a code bit that is weak in an error of an LDPC code is mapped to a weak bit in a quadrature modulated symbol, the overall resistance to error is lowered.

Accordingly, the present invention proposes an interleaver to interleave code bits of an LDPC code so that code bits that are weak to errors in the LDPC code are mapped to strong bits of orthogonally modulated symbols.

The demultiplexer 25 of FIG. 8 performs the operation of this interleaver.

16A-16D illustrate the operation of demultiplexer 25 of FIG.

Specifically, FIG. 16A shows an exemplary functional configuration of demultiplexer 25.

The demultiplexer 25 includes a memory 31 and a reordering unit 32. The LDPC code is provided to the memory 31. The memory 31 has a storage capacity for storing mb bits in the row (horizontal) direction and N / mb bits in the column (vertical) direction. The code bits of the LDPC codes provided to the memory 31 are written to the memory 31 in the column direction, read from the memory 31 in the row direction, and then the read code bits are provided to the reordering unit 32.

Here, "m" represents the number of code bits of the LDPC code mapped to one symbol, and "b" represents a certain positive integer ("m" multiplied to obtain an integral multiple of "m"). Namely, factor). Further, "N" (= information length K + parity length M) indicates the code length of the LDPC code as described above.

16A shows an exemplary configuration of demultiplexer 25 when the modulation scheme is 64QAM. Therefore, the number "m" of code bits of the LDPC code mapped to one symbol is six.

In Fig. 16A, the factor " b " is 1, thus the memory 31 has a storage capacity of N / (6x1) x (6x1) bits in the column and row directions.

In the following, the storage area of the memory 31, which is 1 bit in the row direction and extends in the column direction, is appropriately referred to as a column. In the example of FIG. 16A, the memory 31 includes 6 (= 6 × 1) columns.

The demultiplexer 25 writes the code bits of the LDPC code in the memory 31 in the column direction from the top to the bottom of each column sequentially from the leftmost to the right.

When the code bits are written completely to the bottom of the rightmost column, the code bits are sequentially stored in the row direction starting from the first row of every column of the memory 31 in units of 6 bits (ie, mb bits). ) And the read code bits are provided to the reordering unit 32.

The reordering unit 32 rearranges the positions of the six code bits received from the memory 31, and replaces the six reordered bits with six bits y ₀ , y ₁ , y ₂ , y ₃ , representing one 64QAM symbol. Output as y ₄ and y ₅ .

More specifically, if six code bits read from the memory 31 in the row direction are represented by b ₀ , b ₁ , b ₂ , b ₃ , b ₄ , and b ₅ starting sequentially from the MSB, FIG. 111 is shown. According to the column weight relationship as described above with reference, the code bit adjacent to and including bit "b ₀ " is a code bit that is resistant to error, and the code bit adjacent to bit "b ₅ " and containing it is weak to error. Is a code bit.

Reordering unit 32 to rearrange the position of the 6 code bits b ₀ to b ₅ received from the memory 31, a weak code bits in the 6 code bits b ₀ to b ₅ of the error is one from the memory 31 Is assigned to the strongest bit of the six bits y ₀ to y ₅ representing the 64QAM symbol of.

A number of companies have proposed various ways to reorder six code bits b ₀ to b ₅ from memory 31 and assign them to six bits y ₀ to y ₅ , each representing one 64QAM symbol.

FIG. 16B shows the first reordering method, FIG. 16C shows the second reordering method, and FIG. 16D shows the third reordering method.

In FIGS. 16B-16D, the lines connecting bits b _i and y _j are similar to FIGS. 17A and 17B, which will be described later, in which code bit b _i is assigned to symbol bit y _j (ie, the location of code bit b _{i Change to} the position of the symbol bit y _j ).

The first reordering method of FIG. 16B proposes to use one of three reordering forms, and the second reordering method of FIG. 16C proposes to use one of two reordering forms.

The third reordering method of FIG. 16D proposes sequential selection and use of six reordering forms.

17A and 17B show an exemplary configuration of the demultiplexer 25, and the modulation method is 64QAM (thus the number of code bits " m " of the LDPC code mapped to one symbol as in FIG. 16 is 6) factor " A fourth reordering method when b "is 2 is shown.

When the factor "b" is 2, the memory 31 has a storage capacity of N / (6 × 2) × (6 × 2) bits in the column and row directions, and has 12 (= 6 × 2) columns. .

17A shows the order in which code bits of the LDPC code are written to the memory 31.

The demultiplexer 25 writes the code bits of the LDPC code in the memory 31 in the column direction from the top to the bottom of each column sequentially from the leftmost column to the right as described above with reference to Fig. 16A.

When the code bits are written completely to the bottom of the rightmost column, the code bits are sequentially stored in the row direction starting from the first row of every column of the memory 31 in units of 12 bits (ie, mb bits). ) And the read code bits are provided to the reordering unit 32.

The reordering unit 32 rearranges the positions of the 12 code bits received from the memory 31 and converts the 12 rearranged bits into 12 bits representing two symbols (ie, b symbols) of 64QAM. 6 bits representing the 64QAM symbols of y ₀ , y ₁ , y ₂ , y ₃ , y ₄ , and y ₅ , and 6 bits representing the symbols different from y ₀ , y ₁ , y ₂ , y ₃ , y ₄ , and y ₅ Output as.

FIG. 17B illustrates a fourth reordering method performed by the reordering unit 32 of FIG. 17A.

The optimal reordering method to minimize the error rate in the AWGN communication path depends on the code rate, such as LDPC code.

Now how parity interleaver 23 of FIG. 8 performs parity interleaving will be described with reference to FIGS.

18 shows a part of the Tanner graph of the parity check matrix of the LDPC code.

If an error such as erasure occurs simultaneously on two or more variable nodes connected to a check node (or corresponding two or more code bits), then the check node has a message with a probability of "0" equal to that of "1". Is returned to all the variable nodes connected to the check node as shown in FIG. Thus, decoding performance is degraded when multiple variable nodes connected to the same check node are erased.

The LDPC code defined in the DVB-S.2 specification output by the LDPC encoder 21 of FIG. 8 is an IRA code, and the parity matrix H _T of the parity check matrix H has a stepped structure as shown in FIG. 11.

19A and 19B show tanner graphs corresponding to parity matrix H _T and parity matrix H _T having a stepped structure.

That is, FIG. 19A shows a parity matrix H _T having a stepped structure, and FIG. 19B shows a Tanner graph corresponding to the parity matrix H _T of FIG. 19A.

If the parity matrix H _T has a staged structure, the variable node for which a message is obtained using adjacent code bits (parity bits) of the LDPC code, corresponding to a column containing a device having a value of "1" in the parity matrix H _T , The parity matrix H _T is connected to the same check node of the Tanner graph.

Therefore, if an error such as a burst error or an erase occurs simultaneously in adjacent parity bits, the check node connected to the variable node (that is, the variable node whose message is obtained using the parity bits) respectively corresponds to the parity bit in error. The decoding performance is degraded, because a message having a probability of "0" equal to that of "1" is returned to all variable nodes connected to the check node. Decoding performance is also degraded when the burst length, which is the number of errored bits due to burst, is maximum.

Next, the parity interleaver 23 of FIG. 8 performs parity interleaving in the LDPC code from the LDPC encoder 21, and interleaves the parity bits of the LDPC code to different parity bit positions in order to prevent degradation of decoding performance.

20 illustrates the parity matrix H _T of the parity check matrix H corresponding to the LDPC code after the parity interleaver 23 of FIG. 8 performs parity interleaving on the LDPC code.

Here, the information matrix H _A of the parity check matrix H corresponding to the LDPC code defined in the DVB-S.2 specification output from the LDPC encoder 21 has a cyclic structure.

The term "cyclic structure" refers to a structure that matches another column when the column is cyclically shifted. An example of the recursive structure is that the position of the element "1" in each row of every P column is the first of the column P in which the position of the element "1" is cyclically shifted in the column direction by a value proportional to the value "q" obtained by dividing the parity length "M". It includes a structure corresponding to one position. Next, the number "P" of the columns of the cyclic structure is referred to as the number of units of the rows having the appropriate cyclic structure.

Examples of LDPC codes defined in the DVB-S.2 specification output from the LDPC encoder 21 are two types of LDPC codes having respective code lengths N of 64800 bits and 16200 bits as described above with reference to FIG. It includes.

The following description will focus on the form of an LDPC code having a code length N of 64800 bits among the two forms of an LDPC code having a code length N of 64800 bits and 16200 bits. Eleven nominal code rates are defined for LDPC codes whose code length N is 64800 as described above with reference to FIG.

For any LDPC code with a code length N of 64800 bits each of eleven nominal code rates, the number of units P of columns with a recursive structure is the divisors of parity length M of the DVB-S.2 specification (1 and M). Is defined as "360".

For LDPC codes with a code length N of 64800 bits each of the 11 nominal code rates, parity length M is non-determined according to M = q × P = q × 360 using the value “q” which varies with code rate. Calculated as a non-prime value. Thus, similar to the unit number P of a column having a cyclic structure, the value "q" is another divisor of the parity length M (except 1 and M), and the parity length M is determined by the unit number P of the column having a cyclic structure. Calculated by dividing (ie parity length M is the product of divisor " P " and " q " of parity length M).

When K is the information length, x is an integer greater than or equal to 0 and less than P, y is an integer greater than or equal to 0 and less than q, and the parity interleaver 23 performs parity interleaving on the LDPC code received from the LDPC encoder 21. Interleaving the K + qx + y + 1st code bits among the parity bits that are K + 1st to K + M (= N) th code bits of the LDPC code to K + Py + x + 1st code bit positions do.

According to this parity interleaving method, the variable node (corresponding parity bit) connected to the same check node is at a distance corresponding to the unit number P (360 bits in this example) of the column having the recursive structure, and thus, the same An error can be prevented from occurring simultaneously in a plurality of variable nodes connected to the check node. This can improve resistance to burst errors.

Parity interleaving is performed so that the K + qx + y + 1st code bit is interleaved to the K + Py + x + 1st code bit position. The LDPC code performs a column substitution on the original parity check matrix H. Parity check matrix obtained by replacing (specifically, exchanging) the K + Py + x + 1st column of H's parity check matrix H with the K + qx + y + 1st column (hereinafter referred to as the transformed parity check matrix). Is the same as LDPC code.

The parity matrix of the converted parity check matrix has a pseudo-cyclic structure in which the number of units of columns is "P" ("360" in FIG. 20) as shown in FIG.

Herein, the term "pseudo-cyclic structure" refers to a structure in which a part of the parity matrix has a cyclical structure except for a specific part of the parity matrix. The transformed parity check matrix obtained by performing a column substitution corresponding to parity interleaving on the parity check matrix of the LDPC code defined in the DVB-S.2 specification is described in the short cyclic structure having only one element " 1 " Corresponding to the shifted matrix) (i.e., the 360x360 right corner portion has an element of "0" rather than "1" as required in the recursive structure). Since the transformed parity check matrix does not have a (complete) cyclic structure, it is referred to as having a "pseudo cyclic structure".

In practice, the transformed parity check matrix of FIG. 20 is obtained by performing row substitution on the original parity check matrix H, in addition to column substitution corresponding to parity interleaving, such that the converted parity check matrix includes a component matrix described below. do.

Now, how the thermal twist interleaver 24 of FIG. 8 performs thermal twist interleaving as a substitution process will be described with reference to FIGS. 21 to 24.

The transmitter 11 of FIG. 8 transmits two or more code bits of the LDPC code as one symbol in order to improve the efficiency of using the frequency. For example, QPSK is used as the modulation method when two code bits are transmitted as one symbol, and 16QAM is used as the modulation method when four code bits are transmitted as one symbol.

If an error such as an erase error occurs in one symbol when two or more code bits are transmitted as symbols as described above, all the code bits of the symbol are in error (i.e., erased).

Thus, in order to improve the decoding performance, in order to lower the probability that the variable nodes (corresponding to code bits) connected to the same check node are simultaneously erased, the variable nodes corresponding to the code bits of one symbol are connected to the same check node. It needs to be prevented.

On the other hand, in the case of the parity check matrix H of the LDPC code defined in the DVB-S.2 specification output from the LDPC encoder 21, the information matrix H _A of the parity check matrix H has a cyclical structure, and the parity matrix H _T Has a stepwise structure as described above. In the case of the transformed parity check matrix, which is the parity check matrix of the parity interleaved LDPC code, the parity matrix also has a cyclic structure (specifically, a pseudo cyclic structure) as described above with reference to FIG.

21A and 21B show the transformed parity check matrix.

Specifically, FIG. 21A shows the transformed parity check matrix of the parity check matrix H of an LDPC code having a code length N of 64800 bits and a code rate r of 3/4.

In Fig. 21A, the position of each element having a value of "1" in the transformed parity check matrix is shown by the point ".".

FIG. 21B illustrates the operation that demultiplexer 25 of FIG. 8 performs on the LDPC code of the transformed parity check matrix of FIG. 21A, ie, the parity interleaved LDPC code.

In FIG. 21B, using 16QAM as the modulation method, the code bits of the parity interleaved LDPC code are written in the column direction in four columns constituting the memory 31 of the demultiplexer 25. In FIG.

Code bits written in the column direction in four columns of the memory 31 are read in the row direction in units of 4 bits as one symbol.

In this case, four code bits B ₀ , B ₁ , B ₂ , B ₃ of one symbol will include a plurality of code bits corresponding to “1” of any row in the transformed parity check matrix of FIG. 21A. Can be. In this case, variable nodes corresponding to four code bits B ₀ , B ₁ , B ₂ , B ₃ are connected to the same check node.

Thus, if erasure occurs in a symbol when the four code bits B ₀ , B ₁ , B ₂ , B ₃ of the symbol contain code bits corresponding to "1" of any row in the transformed parity check matrix, It is difficult to obtain an appropriate message for the same check node connected to the variable nodes corresponding to the code bits B ₀ , B ₁ , B ₂ , B ₃ , respectively, thus degrading decoding performance.

If a code rate other than 3/4 is used, a plurality of code bits corresponding to a plurality of variable nodes connected to the same check node may constitute one 16QAM symbol.

Thus, the column twist interleaver 24 performs column twist interleaving on the parity interleaved LDPC code from the parity interleaver 23 to interleave the code bits of the parity interleaved LDPC code, thereby causing any row in the transformed parity check matrix. A plurality of code bits corresponding to "1" of U is not mapped to one symbol.

22 illustrates how thermal twist interleaving is performed.

Specifically, FIG. 22 shows the memory 31 of the demultiplexer 25 shown in FIGS. 16 and 17.

The memory 31 has a storage capacity for storing mb bits in the row (horizontal) direction and N / mb bits in the column (vertical) direction, and includes mb columns as described above with reference to FIG. The column twist interleaver 24 is used in each column of the memory 31 in which writing is started in the column when the code bits of the LDPC code are written to the memory 31 in the column direction and read from the memory 31 in the row direction. Thermal twist interleaving is performed by controlling the recording start position of.

More specifically, the column twist interleaver 24 suitably changes the recording start position at which the code bits start to be written in each of the plurality of columns, so that a plurality of code bits read in the row direction so as to form one symbol are converted. The parity check matrix does not include the plurality of code bits corresponding to "1" of any row. That is, the column twist interleaver 24 replaces code bits of the LDPC code so that a plurality of code bits corresponding to "1" of any row in the parity check matrix are not combined into the same symbol.

FIG. 22 shows an exemplary configuration of the memory 31 when 16QAM is used as the modulation method and the factor "b" described with reference to FIG. 16 is "1". Accordingly, the number "m" of code bits of the LDPC code mapped to one symbol is 4, and the memory 31 includes 4 (= mb) columns.

The column twist interleaver 24 of FIG. 22 (instead of the demultiplexer 25 of FIG. 16) starts from the leftmost column and sequentially to the right, in a column direction from top to bottom of each of the four columns of the memory 31. The code bit of the LDPC code is written to the memory 31.

When the code bits are written completely to the rightmost column, the column twist interleaver 24 reads the code bits in units of four bits (mb bits) in the row direction, starting from the first row of every column of the memory 31. The read code bits are output to the reordering unit 32 of the demultiplexer 25 shown in FIGS. 16 and 17 as column twist interleaved LDPC codes.

When the address of the first (upper) position of each column is represented by "0", and the address of each position along the column direction is represented by an integer that sequentially increases, the column twist interleaver 24 of FIG. The address of the recording start position is "0", the address of the recording start position of the second column is "2", the address of the recording start position of the third column is "4", and the address of the recording start position of the fourth column is "7". Decide.

After the code bit has been written to the column having the write start position at an address other than "0" to the lower position of the column, the column twist interleaver 24 returns to the first position of the column at address "0" and immediately before the write start position. Continue writing the code bits in the column until the position. The column twist interleaver 24 then writes to the next right column.

Performing column twist interleaving as described above includes a method in which a plurality of code bits corresponding to a plurality of variable nodes connected to the same check node have a code length N of 64800 as defined in the DVB-S.2 specification. It is possible to prevent being allocated to one symbol of 16QAM (ie, combined into the same symbol) for the LDPC code of the code rate. This can improve decoding performance in the communication path where cancellation occurs.

Figure 23 shows each modulation method for each LDPC code of 11 code rates having the number of columns of memory 31 required for column twist interleaving, and a code length N of 64800 as defined in the DVB-S.2 specification. Shows the address of the recording start position associated with the.

When one of the first to third reordering methods of FIG. 16 is used in the realigning process of the demultiplexer 25 shown in FIG. 8, and QPSK is used as the modulation method, the number of bits "m" of one symbol is 2 And factor "b" is one.

In this case, the memory 31 has two columns for storing 2x1 (= mb) bits in the row direction, and stores 64800 / (2x1) bits in the column direction as shown in FIG. do. The write start position of the first column of the two columns of the memory 31 is at address "0", and the write start position of the second column is at address "2".

In addition, when the fourth reordering method of FIG. 17 is used in the realigning process of the demultiplexer 25 shown in FIG. 8, and QPSK is used as the modulation method, the number "m" of bits of one symbol is two, and the factor. "b" is two.

In this case, the memory 31 has four columns for storing 2x2 bits in the row direction, and stores 64800 / (2x2) bits in the column direction as shown in FIG. The write start position of the first column of the four columns of the memory 31 is at address "0", the write start position of the second column is at address "2", the write start position of the third column is at address "4", The recording start position of the fourth column is at address " 7 ".

Further, when one of the first to third reordering methods of FIG. 16 is used in the realigning process of the demultiplexer 25 shown in FIG. 8, and 16QAM is used as the modulation method, the number of bits of one symbol "m" Is 4 and the factor "b" is 1.

In this case, the memory 31 has four columns for storing 4x1 bits in the row direction, and stores 64800 / (4x1) bits in the column direction as shown in FIG. The write start position of the first column of the four columns of the memory 31 is at address "0", the write start position of the second column is at address "2", the write start position of the third column is at address "4", The recording start position of the fourth column is at address " 7 ".

In addition, when the fourth reordering method of FIG. 17 is used in the realigning process of the demultiplexer 25 shown in FIG. 8, and 16QAM is used as the modulation method, the number "m" of bits of one symbol is four, and a factor. "b" is two.

In this case, the memory 31 has eight columns for storing 4x2 bits in the row direction, and stores 64800 / (4x2) bits in the column direction as shown in FIG. The write start position of the first column of the eight columns of the memory 31 is at address "0", the write start position of the second column is at address "0", the write start position of the third column is at address "2", The recording start position of the fourth column is at address "4", the recording start position of the fifth column is at address "4", the recording start position of the sixth column is at address "5", and the recording start position of the seventh column is At the address "7", the write start position of the eighth column is at the address "7".

Further, when one of the first to third reordering methods of FIG. 16 is used in the realigning process of the demultiplexer 25 shown in FIG. 8, and 64QAM is used as the modulation method, the number of bits of one symbol "m" Is 6 and the factor "b" is 1;

In this case, the memory 31 has six columns for storing 6x1 bits in the row direction, and stores 64800 / (6x1) bits in the column direction as shown in FIG. The write start position of the first column of the six columns of the memory 31 is at address "0", the write start position of the second column is at address "2", the write start position of the third column is at address "5", The write start position of the fourth column is at address "9", the write start position of the fifth column is at address "10", and the write start position of the sixth column is at address "13".

Further, when the fourth reordering method of FIG. 17 is used in the realigning process of the demultiplexer 25 shown in FIG. 8, and 64QAM is used as the modulation method, the number "m" of bits of one symbol is 6, and the factor "b" is two.

In this case, the memory 31 has 12 columns for storing 6x2 bits in the row direction, and stores 64800 / (6x2) bits in the column direction as shown in FIG. The write start position of the first column of the 12 columns of the memory 31 is at address "0", the write start position of the second column is at address "0", the write start position of the third column is at address "2", The write start position of the fourth column is at address "2", the write start position of the fifth column is at address "3", the write start position of the sixth column is at address "4", and the write start position of the seventh column is at address At the "4", the write start position of the eighth column is at address "5", the write start position of the ninth column is at address "5", the write start position of the tenth column is at address "7", and the eleventh The write start position of the column is at address "8", and the write start position of the twelfth column is at address "9".

Further, when one of the first to third reordering methods of FIG. 16 is used in the realigning process of the demultiplexer 25 shown in FIG. 8, and 256QAM is used as the modulation method, the number of bits of one symbol "m" Is 8 and the factor "b" is 1.

In this case, the memory 31 has eight columns for storing 8x1 bits in the row direction, and stores 64800 / (8x1) bits in the column direction as shown in FIG. The write start position of the first column of the eight columns of the memory 31 is at address "0", the write start position of the second column is at address "0", the write start position of the third column is at address "2", The write start position of the fourth column is at address "4", the write start position of the fifth column is at address "4", the write start position of the sixth column is at address "5", and the write start position of the seventh column is at address Is in " 7 ", and the recording start position in the eighth column is in address " 7 ".

In addition, when the fourth reordering method of FIG. 17 is used in the realigning process of the demultiplexer 25 shown in FIG. 8 and 256QAM is used as the modulation method, the number "m" of bits of one symbol is 8, and the factor "b" is two.

In this case, the memory 31 has 16 columns for storing 8x2 bits in the row direction, and stores 64800 / (8x2) bits in the column direction as shown in FIG. The write start position of the first column of the 16 columns of the memory 31 is at address "0", the write start position of the second column is at address "2", the write start position of the third column is at address "2", The write start position of the fourth column is at address "2", the write start position of the fifth column is at address "2", the write start position of the sixth column is at address "3", and the write start position of the seventh column is at address In the "7", the write start position in the eighth column is at address "15", the write start position in the ninth column is at address "16", and the write start position in the tenth column is at address "20", and the 11th The write start position of the column is at address "22", the write start position of the 12th column is at address "22", the write start position of the 13th column is at address "27", and the write start position of the 14th column is at address "27". ", Column 15 Recording start position is at the address "28", a recording start position is at the 16th column address "32".

Further, when one of the first to third reordering methods of FIG. 16 is used in the realigning process of the demultiplexer 25 shown in FIG. 8, and 1024QAM is used as the modulation method, the number of bits of one symbol "m" Is 10 and the factor "b" is 1.

In this case, the memory 31 has ten columns for storing 10x1 bits in the row direction, and stores 64800 / (10x1) bits in the column direction as shown in FIG. The write start position of the first column of the ten columns of the memory 31 is at address "0", the write start position of the second column is at address "3", the write start position of the third column is at address "6", The write start position of the fourth column is at address "8", the write start position of the fifth column is at address "11", the write start position of the sixth column is at address "13", and the write start position of the seventh column is at address At "15", the write start position of the eighth column is at address "17", the write start position of the ninth column is at address "18", and the write start position of the tenth column is at address "20".

In addition, when the fourth reordering method of FIG. 17 is used in the realigning process of the demultiplexer 25 shown in FIG. 8, and 1024QAM is used as the modulation method, the number "m" of bits of one symbol is 10, and a factor. "b" is two.

In this case, the memory 31 has 20 columns for storing 10x2 bits in the row direction, and stores 64800 / (10x2) bits in the column direction as shown in FIG. The write start position of the first column of the 20 columns of the memory 31 is at address "0", the write start position of the second column is at address "1", the write start position of the third column is at address "3", The write start position of the fourth column is at address "4", the write start position of the fifth column is at address "5", the write start position of the sixth column is at address "6", and the write start position of the seventh column is at address At the "6", the write start position of the eighth column is at address "9", the write start position of the ninth column is at address "13", the write start position of the tenth column is at address "14", and the eleventh The write start position of the column is at address "14", the write start position of the 12th column is at address "16", the write start position of the 13th column is at address "21", and the write start position of the 14th column is at address "21". "In the 15th column The recording start position is at address "23", the recording start position of the 16th column is at address "25", the recording start position of the 17th column is at address "25", and the recording start position of the 18th column is at address "26". ", The recording start position of the 19th column is at address" 28 ", and the recording start position of the 20th column is at address" 30 ".

Further, when one of the first to third reordering methods of FIG. 16 is used in the realigning process of the demultiplexer 25 shown in FIG. 8, and 4096QAM is used as the modulation method, the number of bits of one symbol "m" Is 12 and the factor "b" is 1.

In this case, the memory 31 has 12 columns for storing 12x1 bits in the row direction, and stores 64800 / (12x1) bits in the column direction as shown in FIG. The write start position of the first column of the 12 columns of the memory 31 is at address "0", the write start position of the second column is at address "0", the write start position of the third column is at address "2", The write start position of the fourth column is at address "2", the write start position of the fifth column is at address "3", the write start position of the sixth column is at address "4", and the write start position of the seventh column is at address At the "4", the write start position of the eighth column is at address "5", the write start position of the ninth column is at address "5", the write start position of the tenth column is at address "7", and the eleventh The write start position of the column is at address "8", and the write start position of the twelfth column is at address "9".

In addition, when the fourth reordering method of FIG. 17 is used in the realigning process of the demultiplexer 25 shown in FIG. 8, and 4096QAM is used as the modulation method, the number of bits "m" of one symbol is 12, Factor "b" is two.

In this case, the memory 31 has 24 columns for storing 12x2 bits in the row direction, and stores 64800 / (12x2) bits in the column direction as shown in FIG. The write start position of the first column of the 24 columns of the memory 31 is at address "0", the write start position of the second column is at address "5", the write start position of the third column is at address "8", The write start position of the fourth column is at address "8", the write start position of the fifth column is at address "8", the write start position of the sixth column is at address "8", and the write start position of the seventh column is at address In the "10", the write start position in the eighth column is at address "10", the write start position in the ninth column is at address "10", the write start position in the tenth column is at address "12", and the 11th The write start position of the column is at address "13", the write start position of the 12th column is at address "16", the write start position of the 13th column is at address "17", and the write start position of the 14th column is at address "19". ", Column 15 The recording start position is at address "21", the recording start position of the 16th column is at address "22", the recording start position of the 17th column is at address "23", and the recording start position of the 18th column is at address "26". At the beginning of the 19th column is at address "37", the recording start position at the 20th column is at address "39", and the recording start position of the 21st column is at address "40", and the recording start of the 22nd column is at The position is at address "41", the recording start position in the 23rd column is at address "41", and the recording start position in the 24th column is at address "41".

Figure 24 shows each modulation method for each LDPC code of 10 code rates having the number of columns of memory 31 required for column twist interleaving, and a code length N of 16200 as defined in the DVB-S.2 specification. Shows the address of the recording start position associated with the.

When one of the first to third reordering methods of FIG. 16 is used in the realigning process of the demultiplexer 25 shown in FIG. 8, and QPSK is used as the modulation method, the number of bits "m" of one symbol is 2 And factor "b" is one.

In this case, the memory 31 has two columns for storing 2x1 bits in the row direction, and stores 16200 / (2x1) bits in the column direction as shown in FIG. The write start position of the first column of the two columns of the memory 31 is at address "0", and the write start position of the second column is at address "0".

In addition, when the fourth reordering method of FIG. 17 is used in the realigning process of the demultiplexer 25 shown in FIG. 8, and QPSK is used as the modulation method, the number "m" of bits of one symbol is two, and the factor. "b" is two.

In this case, the memory 31 has four columns for storing 2x2 bits in the row direction, and stores 16200 / (2x2) bits in the column direction as shown in FIG. The write start position of the first column of the four columns of the memory 31 is at address "0", the write start position of the second column is at address "2", the write start position of the third column is at address "3", The recording start position of the fourth column is at address " 3 ".

Further, when one of the first to third reordering methods of FIG. 16 is used in the realigning process of the demultiplexer 25 shown in FIG. 8, and 16QAM is used as the modulation method, the number of bits of one symbol " m "is 4 and factor" b "is 1.

In this case, the memory 31 has four columns for storing 4x1 bits in the row direction, and stores 16200 / (4x1) bits in the column direction as shown in FIG. The write start position of the first column of the four columns of the memory 31 is at address "0", the write start position of the second column is at address "2", the write start position of the third column is at address "3", The recording start position of the fourth column is at address " 3 ".

In addition, when the fourth reordering method of FIG. 17 is used in the realigning process of the demultiplexer 25 shown in FIG. 8, and 16QAM is used as the modulation method, the number "m" of bits of one symbol is four, and a factor. "b" is two.

In this case, the memory 31 has eight columns for storing 4x2 bits in the row direction, and stores 16200 / (4x2) bits in the column direction as shown in FIG. The write start position of the first column of the eight columns of the memory 31 is at address "0", the write start position of the second column is at address "0", the write start position of the third column is at address "0", The write start position of the fourth column is at address "1", the write start position of the fifth column is at address "7", the write start position of the sixth column is at address "20", and the write start position of the seventh column is at address At "20", the write start position in the eighth column is at address "21".

Further, when one of the first to third reordering methods of FIG. 16 is used in the realigning process of the demultiplexer 25 shown in FIG. 8, and 64QAM is used as the modulation method, the number of bits of one symbol "m" Is 6 and the factor "b" is 1;

In this case, the memory 31 has six columns for storing 6x1 bits in the row direction, and stores 16200 / (6x1) bits in the column direction as shown in FIG. The write start position of the first column of the six columns of the memory 31 is at address "0", the write start position of the second column is at address "0", the write start position of the third column is at address "2", The write start position of the fourth column is at address "3", the write start position of the fifth column is at address "7", and the write start position of the sixth column is at address "7".

Further, when the fourth reordering method of FIG. 17 is used in the realigning process of the demultiplexer 25 shown in FIG. 8, and 64QAM is used as the modulation method, the number "m" of bits of one symbol is 6, and the factor "b" is two.

In this case, the memory 31 has 12 columns for storing 6x2 bits in the row direction, and stores 16200 / (6x2) bits in the column direction as shown in FIG. The write start position of the first column of the 12 columns of the memory 31 is at address "0", the write start position of the second column is at address "0", the write start position of the third column is at address "0", The write start position of the fourth column is at address "2", the write start position of the fifth column is at address "2", the write start position of the sixth column is at address "2", and the write start position of the seventh column is at address In the "3", the write start position in the eighth column is at address "3", the write start position in the ninth column is at address "3", the write start position in the tenth column is at address "6", and the 11th The write start position of the column is at address "7" and the write start position of the twelfth column is at address "7".

Further, when one of the first to third reordering methods of FIG. 16 is used in the realigning process of the demultiplexer 25 shown in FIG. 8, and 256QAM is used as the modulation method, the number of bits of one symbol "m" Is 8 and the factor "b" is 1.

In this case, the memory 31 has eight columns for storing 8x1 bits in the row direction, and stores 16200 / (8x1) bits in the column direction as shown in FIG. The write start position of the first column of the eight columns of the memory 31 is at address "0", the write start position of the second column is at address "0", the write start position of the third column is at address "0", The write start position of the fourth column is at address "1", the write start position of the fifth column is at address "7", the write start position of the sixth column is at address "20", and the write start position of the seventh column is at address At "20", the write start position in the eighth column is at address "21".

Further, when one of the first to third reordering methods of FIG. 16 is used in the realigning process of the demultiplexer 25 shown in FIG. 8, and 1024QAM is used as the modulation method, the number of bits of one symbol "m" Is 10 and the factor "b" is 1.

In this case, the memory 31 has ten columns for storing 10x1 bits in the row direction, and stores 16200 / (10x1) bits in the column direction as shown in FIG. The write start position of the first column of the ten columns of the memory 31 is at address "0", the write start position of the second column is at address "1", the write start position of the third column is at address "2", The write start position of the fourth column is at address "2", the write start position of the fifth column is at address "3", the write start position of the sixth column is at address "3", and the write start position of the seventh column is at address At "4", the write start position of the eighth column is at address "4", the write start position of the ninth column is at address "5", and the write start position of the tenth column is at address "7".

In addition, when the fourth reordering method of FIG. 17 is used in the realigning process of the demultiplexer 25 shown in FIG. 8, and 1024QAM is used as the modulation method, the number "m" of bits of one symbol is 10, and a factor. "b" is two.

In this case, the memory 31 has 20 columns for storing 10x2 bits in the row direction, and stores 16200 / (10x2) bits in the column direction as shown in FIG. The write start position of the first column of the 20 columns of the memory 31 is at address "0", the write start position of the second column is at address "0", the write start position of the third column is at address "0", The write start position of the fourth column is at address "2", the write start position of the fifth column is at address "2", the write start position of the sixth column is at address "2", and the write start position of the seventh column is at address In the "2", the write start position in the eighth column is at address "2", the write start position in the ninth column is at address "5", the write start position in the tenth column is at address "5", and the 11th The recording start position of the column is at address "5", the recording start position of the 12th column is at address "5", the recording start position of the 13th column is at address "5", and the recording start position of the 14th column is address "7". In the "15th column, The start position is at address "7", the recording start position of the 16th column is at address "7", the recording start position of the 17th column is at address "7", and the recording start position of the 18th column is located at address "8". The recording start position of the 19th column is at address "8", and the recording start position of the 20th column is at address "10".

Further, when one of the first to third reordering methods of FIG. 16 is used in the realigning process of the demultiplexer 25 shown in FIG. 8, and 4096QAM is used as the modulation method, the number of bits of one symbol "m" Is 12 and the factor "b" is 1.

In this case, the memory 31 has 12 columns for storing 12x1 bits in the row direction, and stores 16200 / (12x1) bits in the column direction as shown in FIG. The write start position of the first column of the 12 columns of the memory 31 is at address "0", the write start position of the second column is at address "0", the write start position of the third column is at address "0", The write start position of the fourth column is at address "2", the write start position of the fifth column is at address "2", the write start position of the sixth column is at address "2", and the write start position of the seventh column is at address In the "3", the write start position in the eighth column is at address "3", the write start position in the ninth column is at address "3", the write start position in the tenth column is at address "6", and the 11th The write start position of the column is at address "7" and the write start position of the twelfth column is at address "7".

In addition, when the fourth reordering method of FIG. 17 is used in the realigning process of the demultiplexer 25 shown in FIG. 8, and 4096QAM is used as the modulation method, the number of bits "m" of one symbol is 12, Factor "b" is two.

In this case, the memory 31 has 24 columns for storing 12x2 bits in the row direction, and stores 16200 / (12x2) bits in the column direction as shown in FIG. The write start position of the first column of the 24 columns of the memory 31 is at address "0", the write start position of the second column is at address "0", the write start position of the third column is at address "0", The write start position of the fourth column is at address "0", the write start position of the fifth column is at address "0", the write start position of the sixth column is at address "0", and the write start position of the seventh column is at address Is at "0", the write start position of the eighth column is at address "1", the write start position of the ninth column is at address "1", the write start position of the tenth column is at address "1", and the 11th The recording start position of the column is at address "2", the recording start position of the 12th column is at address "2", the recording start position of the 13th column is at address "2", and the recording start position of the 14th column is address "3". In the "15th column, The start position is at address "7", the write start position of the 16th column is at address "9", the write start position of the 17th column is at address "9", and the write start position of the 18th column is located at address "9". The recording start position of the 19th column is at address "10", the recording start position of the 20th column is at address "10", the recording start position of the 21st column is at address "10", and the recording start position of the 22nd column Is at address "10", the recording start position of the 23rd column is at address "10", and the recording start position of the 24th column is at address "11".

The transmission procedure performed by the transmitter 11 of FIG. 8 will now be described with reference to the flowchart of FIG. 25.

The LDPC encoder 21 waits until the target data is received in step S101, encodes the received target data into an LDPC code, sends the LDPC code to the bit interleaver 22, and then the procedure proceeds to step S102.

In step S102, the bit interleaver 22 performs bit interleaving on the LDPC code from the LDPC encoder 21, sends the bit interleaved LDPC code to the mapping section 26, and then the procedure goes to step S103.

More specifically, in step S102, the parity interleaver 23 in the bit interleaver 22 performs parity interleaving on the LDPC code from the LDPC encoder 21, and converts the parity interleaved LDPC code into the column twist interleaver 24. send.

The column twist interleaver 24 performs thermal twist interleaving on the LDPC codes from the parity interleaver 23, and the demultiplexer 25 performs reordering processing on the LDPC codes thermally twisted interleaved by the column twist interleaver 24. do. The demultiplexer 25 then sends the rearranged LDPC code to the mapping section 26.

In step S103, the mapping unit 26 maps the m code bits of the LDPC code from the demultiplexer 25 to symbols represented by signal points determined according to the modulation scheme that the quadrature modulator 27 uses to perform orthogonal modulation. And sends the mapped symbol to quadrature modulator 27, then the procedure proceeds to step S104.

In step S104, the orthogonal modulator 27 performs orthogonal modulation of the carrier on the symbols from the mapping unit 26, and then the procedure proceeds to step S105 to transmit the orthogonally modulated signal, and then the procedure ends. .

The transmission procedure of FIG. 25 is repeated.

Performing parity interleaving or column twist interleaving as described above may increase resistance to burst error or erasure when a plurality of code bits of an LDPC code are transmitted as one symbol.

The parity interleaver 23, which is a block that performs parity interleaving, and the column twist interleaver 24, which is a block that performs column twist interleaving, has a parity interleaver 23 and a column twist interleaver 24 in FIG. 8 for ease of description. Although shown as being individually configured, it may be integrally configured.

More specifically, both the parity interleaver and the column twist interleaver can write code bits to and read code bits from the memory, and the address (write address) at which the code bits are written is read from the address (write address) Address).

Thus, by converting code bits using a matrix obtained by multiplying a matrix representing parity interleaving and a matrix representing column twist interleaving, a parity interleaved LDPC code can then be obtained.

The demultiplexer 25 may also be integrated with the parity interleaver 23 and the thermal twist interleaver 24.

More specifically, the reordering process performed by the demultiplexer 25 can be represented by a matrix that converts the write address of the memory 31 that stores the LDPC code into a read address.

Therefore, parity interleaving, column twist interleaving, and reordering processing can be integrally performed using a matrix obtained by multiplying a matrix representing parity interleaving, a matrix representing column twist interleaving, and a matrix representing realignment processing.

Parity interleaving or thermal twist interleaving may be performed alone.

Now, the simulation of measuring the bit error rate performed by the transmitter 11 of FIG. 8 will be described with reference to FIGS. 26 to 28.

The simulation was performed using a communication path of 0dB D / U flutter.

26A and 26B show a model of the communication path used for the simulation.

Specifically, FIG. 26A shows a model of the flutter used for the simulation.

FIG. 26B shows a model of a communication path whose model has the flutter shown in FIG. 26A.

“H” in FIG. 26B represents a model of the flutter of FIG. 26A. "N" represents Inter-Carrier Interference (ICI) of FIG. 26B. In the simulation, the expected value E [N ² ] of the power of ICI is close to AWGN.

27 and 28 show the relationship between the Doppler frequency f _d of the flutter and the error rate from the simulation.

More specifically, FIG. 27 shows the relationship between the Doppler frequency f _d and the error rate when the modulation scheme is 16QAM, the code rate r is 3/4, and the reordering method is the first reordering method. Fig. 28 shows the relationship between the Doppler frequency f _d and the error rate when the modulation scheme is 64QAM, the code rate r is 5/6, and the reordering method is the first reordering method.

In Figs. 27 and 28, the thick line represents the relationship between the Doppler frequency f _d and the error rate when all of the parity interleaving, thermal twist interleaving, and realignment processing have been performed, and the thin line shows only the realignment processing among the three processes. The relationship between the Doppler frequency f _d and the error rate when performed.

27 and 28, it can be seen that the error rate when parity interleaving, thermal twist interleaving, and realignment processing are all performed (ie, lowered) compared to when only the reordering process is performed.

receiving set

29 provides an exemplary illustration of a receiver that may be used to detect an OFDM symbol and recover data bits from a subcarrier signal of the OFDM symbol. As shown in FIG. 29, an OFDM signal is received by antenna 500, detected by tuner 502, and converted to digital form by analog-to-digital converter 504. The guard spacing processor 506 is a Fast Fourier Transform (FFT) processor 508 with a channel estimator and corrector 510 operating in conjunction with the in-signaling decoding unit 511 in accordance with known techniques. ) To remove the guard interval from the received OFDM symbol before the data is recovered from the OFDM symbol. The demodulated data symbols are recovered from the demapper 512 and supplied to the symbol deinterleaver 514, which operates to reverse map the received data symbols to output symbols as deinterleaved data symbols. Rebuild the stream. The symbol deinterleaver 514 will be described in more detail shortly.

Bit Interleaver and LDPC Decoder

As shown in FIG. 29, the receiver also includes a demapping unit 52, a deinterleaver 53, and an LDPC decoder 56. The demapping unit 52 is operable to receive a symbol (having respective values in the I and Q axis directions) from the symbol deinterleaver 514 and to demap the symbol into encoded bits of the LDPC code, The encoded bit is sent to the bit deinterleaver 53. Demapping of the received data symbols is performed by identifying the bits represented by the data symbols identified from the subcarrier signals of the OFDM symbols.

The bit deinterleaver 53 includes a demultiplexer 54 and a column twist deinterleaver 55 and deinterleaves the code bits of the LDPC code from the demapping unit 52.

More specifically, the demultiplexer 54 performs the reverse reordering process, which is an inversion of the reordering process performed by the demultiplexer 25 of FIG. 8, on the LDPC code from the demapping unit 52. Specifically, the demultiplexer 54 performs a reverse reordering process to restore the position of the code bits rearranged by the reordering process to the original position, and sends the rearranged LDPC codes to the thermal twist deinterleaver 55.

The thermal twist deinterleaver 55 performs an inverse thermal twist deinterleaving process, which is an inversion of the thermal twist interleaving as the substitution process performed by the thermal twist interleaver 24 of FIG. 8, on the LDPC code from the demultiplexer 54. do. Specifically, the thermal twist deinterleaver 55 performs reverse substitution processing (for example, thermal twist deinterleaving) to recover the original order of the code bits of the LDPC code rearranged by the thermal twist interleaving as the code bit substitution processing. Perform

More specifically, the column twist deinterleaver 55 writes the code bits of the LDPC code into the memory for deinterleaving configured similarly to the memory 31 shown in FIG. 22 and writes the code bits of the LDPC code from the memory. Thermal twist deinterleaving is performed by reading.

However, the column twist deinterleaver 55 writes the code bits in the row direction in the memory for deinterleaving using the read address in which the code bits are read from the memory 31 as the write address. Further, the column twist deinterleaver 55 reads the code bits in the column direction from the memory for deinterleaving using the write address in which the code bits are written into the memory 31 as the read addresses.

The thermal twist deinterleaver 55 sends the thermal twist deinterleaved LDPC code to the LDPC decoder 56.

Although parity interleaving, thermal twist interleaving, and reordering processing were performed sequentially for the LDPC code provided from the demapping unit 52 to the deinterleaver 53, the deinterleaver 53 performed two processes for the LDPC code, That is, only the reverse reordering process corresponding to the reordering process and the thermal twist deinterleaving corresponding to the thermal twist interleaving are performed. Thus, the deinterleaver 53 does not perform parity deinterleaving (ie, reverse processing of parity interleaving) corresponding to parity interleaving. That is, the deinterleaver 53 does not perform parity deinterleaving to recover the original order of the code bits of the LDPC code rearranged by parity interleaving.

Thus, an LDPC code for performing reverse reordering and thermal twist deinterleaving and no parity deinterleaving is provided from the deinterleaver 53 (the thermal twist deinterleaver 55) to the LDPC decoder 56.

The LDPC decoder 56 uses a de-interleaver (a transformed parity check matrix obtained by performing at least column substitution corresponding to parity interleaving on the parity check matrix H used by the LDPC encoder 21 of FIG. 8 for LDPC encoding). LDPC decoding is performed on the LDPC code from 53), and the resulting data is output as decoded target data.

30 is a flowchart showing a reception procedure performed by the receiver 12 of FIG.

The quadrature demodulator 51 receives the modulated signal from the transmitter 11 in step S111. The procedure then proceeds to step S112 to perform orthogonal demodulation on the modulated signal. Then, the orthogonal demodulator 51 sends the symbol obtained through the orthogonal demodulation to the demapping unit 52, and then the procedure goes from step S112 to step S113.

In step S113, the demapping unit 52 demaps the symbols from the quadrature demodulator 51 into the code bits of the LDPC code, and sends the code bits of the LDPC code to the deinterleaver 53. The procedure then proceeds to step S114.

In step S114, the deinterleaver 53 performs deinterleaving on the code bits of the LDPC code from the demapping unit 52, and then the procedure goes to step S115.

More specifically, in step S114, the demultiplexer 54 of the deinterleaver 53 performs a reverse reordering process on the LDPC code from the demapping unit 52, and heats up the resulting LDPC code into a thermal twist deinterleaver ( 55).

The thermal twist deinterleaver 55 performs thermal twist deinterleaving on the LDPC code from the demultiplexer 54 and sends the resulting LDPC code to the LDPC decoder 56.

In step S115, the LDPC decoder 56 uses the transformed parity check matrix obtained by performing at least column substitution corresponding to parity interleaving to the parity check matrix H used by the LDPC encoder 21 of FIG. 8 for LDPC encoding. LDPC decoding is performed on the LDPC code from the column twist deinterleaver 55, and then the resulting data is provided as decoded target data. The procedure then ends.

The receiving procedure of FIG. 30 is repeated.

The demultiplexer 54 which performs the rearrangement process and the thermal twist deinterleaver 55 which performs the thermal twist deinterleaving, the demultiplexer 54 and the thermal twist deinterleaver 55 are as shown in FIG. Although shown separately in FIG. 29 in the same manner, it may be integrally configured.

If the transmitter 11 of FIG. 8 does not perform thermal twist interleaving, it is not necessary to provide a thermal twist deinterleaver 55 to the receiver 12 of FIG.

Now, how the LDPC decoder 56 of FIG. 29 performs LDPC decoding will be discussed.

The LDPC decoder 56 of FIG. 29 uses a transformed parity check matrix obtained by performing at least column substitution corresponding to parity interleaving on the parity check matrix H used by the LDPC encoder 21 of FIG. 8 for LDPC encoding. Performs LDPC decoding of the LDPC code from the column twist deinterleaver 55, where reverse reordering processing and column twist deinterleaving are performed and no parity interleaving is performed.

Here, LDPC decoding has been previously presented, which is performed using the transformed parity check matrix to limit the operating frequency and reduce the size of the circuit within a sufficiently reachable range (for example, Japanese Patent Application Publication No. 2004-343170). Reference).

First, LDPC decoding using the previously proposed transformed parity check matrix is described with reference to FIGS. 31 to 34.

31 shows an exemplary parity check matrix H of LDPC codes with code length N of 90 and code rate of 2/3.

In FIG. 31, as in FIGS. 32 and 33 described later, "0" is represented by a period ".".

The parity matrix of parity check matrix H of FIG. 31 has a stepped structure.

FIG. 32 shows the parity check matrix H 'obtained by performing row substitution of equation (8) and column substitution of equation (9) on the parity check matrix H of FIG.

Line substitution: 6s + t + 1st line → 5t + s + 1st line

Heat substitution: 6x + y + 61th column → 5y + x + 61th column

In Equations 8 and 9, s, t, x, and y are integers, and 0 ≦ s <5, 0 ≦ t <6, 0 ≦ x <5, and 0 ≦ y <6.

According to the row substitution of Equation 8, when the ordinal is divided by 6, the 1st, 7th, 13th, 19th, and 25th lines having "1" as the remainder are 1st, 2nd, 3rd, The second, eighth, fourteenth, twenty, and twenty-sixth rows are changed (specifically, swapped) to the fourth and fifth rows, respectively, and the ordinal is divided by six, and has "2" as the remainder. 6th, 7th, 8th, 9th, and 10th rows, respectively.

According to the column substitution of Equation 9, of the (parity) columns subsequent to the 60th column, the ordinal numbers are divided into 6, and the 61st, 67th, 73rd, 79th, and 89th columns having "1" as the rest. Is changed to the 61st, 62nd, 63rd, 64th, and 65th columns, respectively, and when the ordinal is divided by 6, the 62nd, 68th, 74th, 80th, and 86 have "2" as the remainder. The fourth column is changed to the 66th, 67th, 68th, 69th, and 70th columns, respectively.

The matrix obtained by performing row and column substitution on the parity check matrix H of FIG. 31 in this manner is the parity check matrix H 'of FIG.

Here, performing row substitution of the parity check matrix H does not affect the order of the code bits of the LDPC code.

In the column substitution of the equation (9), the information length K is "60", the unit number P of the column having a cyclic structure is "5", and the divisor q (M / P) of the parity length M (30 in this example) is When " 6 " corresponds to parity interleaving performed to interleave the K + qx + y + l &lt; th &gt; code bits to the K + Py + x + l &lt; th &gt; code bit positions as described above.

The zero vector is the LDPC code of the parity check matrix H of FIG. 31, where the parity check matrix H 'of FIG. 32 is appropriately referred to as " transformed parity check matrix &quot; Is multiplied by an LDPC code obtained by performing the same substitution as in Equation (9) with respect to Equation (9). More specifically, when " c '" represents a row vector obtained by performing column substitution of equation (9) to row vector &quot; c " as the LDPC code (codeword) of the original parity check matrix H, Due to its characteristics, Hc ^T represents a zero vector, and therefore H'c ' ^{T is} also a zero vector.

Accordingly, the transformed parity check matrix H 'of FIG. 32 is the parity check matrix of the LDPC code c' obtained by performing column substitution of Equation 9 to the LDPC code c of the original parity check matrix H.

Therefore, the same LDPC code of the same original parity check matrix H as obtained through decoding using parity check matrix H, using the transformed parity check matrix H 'of FIG. 32, is the LDPC code of original parity check matrix H. LDPC decoding of the thermally substituted LDPC code c 'generated by performing thermal substitution of Equation 9 to c, and then performing reverse processing of thermal substitution of Equation 9 on the decoded LDPC code c'.

FIG. 33 illustrates the transformed parity check matrix H ′ of FIG. 32 shown as elements arranged spaced apart from each other in units of a 5 × 5 matrix.

In FIG. 33, the transformed parity check matrix H 'is a matrix of 5x5 units, each of which is generated by replacing one or more "1s" of the 5x5 unit matrix with "0" (hereinafter, appropriately " Matrices generated by circularly shifting a quasi-unit matrix, a unit matrix or a quasi-unit matrix (hereinafter referred to as the appropriate "shifted matrix"), each of two or more It is shown as a combination of a unit matrix, a quasi-unit matrix, and a shifted matrix (hereinafter, suitably referred to as a "sum matrix"), and a 5x5 zero matrix.

That is, the transformed parity check matrix H ′ of FIG. 33 may be a matrix including a 5 × 5 unit matrix, a quasi-unit matrix, a shifted matrix, a sum matrix, and a 5 × 5 zero matrix. Thus, the 5x5 matrix constituting the transformed parity check matrix H 'will now be properly referred to as "component matrices."

 The decoding of the LDPC code represented by the parity check matrix represented by the P × P component matrix may be performed using a structure that simultaneously performs P check node calculation and P variable node calculation.

34 is a block diagram illustrating an exemplary configuration of a decoding apparatus that performs decoding as described above.

More specifically, FIG. 34 is a decoding for performing decoding of an LDPC code using the transformed parity check matrix H 'of FIG. 33 obtained by performing at least column substitution of Equation 9 to the original parity check matrix H of FIG. 31. An exemplary configuration of the device is shown.

The decoding apparatus of FIG. 34, six FIFO 300 ₁ to 300 ₆ the edge selector 301, a check node calculation section 302 to the data storage memory 300, select one of the FIFO 300 ₁ to 300 _6, including, two cyclic shift circuits (303 and 308), 18 FIFO 304 ₁ to the selector 305, the received information to 304 edge data storage memory 304 including _18, select one of the FIFO 304 ₁ to 304 ₁₈ The received data memory 306, the variable node calculator 307, the decoded word calculator 309, the received data substitute 310, and the decoded data substitute 311 are stored.

First, a method of storing data in the edge data storage memories 300 and 304 is discussed.

The edge data storage memory 300 has six FIFOs 300 ₁ which are equal to the number obtained by dividing the number "30" of the converted parity check matrix H 'by the number "5" of the rows of each component matrix. To 300 ₆ . Each FIFO 300 _y (y = 1, 2, ..., 6) allows each message corresponding to an "5" edge, which is equal to the number of rows and columns of each component matrix, to be written or read simultaneously. Each storage area of the plurality of stages is included. The number of stages in the storage area of each FIFO 300 _y is "9" equal to the maximum value of the number of 1s (Hamming weight) in the row direction of the transformed parity check matrix of FIG.

Data corresponding to the position of "1" in the first to fifth rows of the converted parity check matrix H 'of FIG. 33 (i.e., the message v _i from the variable node) is ignored in the horizontal direction of every row. Are simultaneously stored in FIFO 300 ₁ . Specifically, when (j, i) represents the elements of the jth row and the ith column, "1" of the 5x5 unit matrix of (1,1) to (5,5) of the converted parity check matrix H '. Data corresponding to the position of is stored in the storage area of the first stage of FIFO 300 ₁ . Corresponds to the position of "1" in the shifted matrix of (1,21) to (5,25) of the transformed parity check matrix H 'obtained by cyclically shifting the 5x5 unit matrix by three elements to the right. The data to be stored is stored in the storage area of the second stage. Similarly, data is stored in a storage area of the third to eighth stages associated with the transformed parity check matrix H '. (1) of the transformed parity check matrix H 'obtained by replacing "1" in the first row with "0" in the 5x5 unit matrix and cyclically shifting the 5x5 unit matrix to the left by one element. , 81) to (5,90) are stored in the storage area of the ninth stage.

Data corresponding to the position of "1" in the sixth to tenth rows of the converted parity check matrix H 'of FIG. 33 is stored in the FIFO 300 ₂ . Specifically, the first shifted matrix obtained by cyclically shifting the 5x5 unit matrix by one element to the right and the second shifted matrix obtained by cyclically shifting the 5x5 unit matrix by two elements to the right The data corresponding to the position of &quot; 1 " of the first shifted matrix included in the sum matrix of (6,1) to (10,5) of the transformed parity check matrix H 'obtained by summing up the FIFO 300 ₂ It is stored in the storage area of the first stage. The data corresponding to the position of "1" of the second shifted matrix included in the sum matrix of (6,1) to (10,5) of the converted parity check matrix H 'is stored in the second stage of the FIFO 300 ₂ . Stored in the area.

More specifically, a matrix of components having a weight of at least 2, at least two P × P unit matrices having a weight of 1, a quasi-unit matrix generated by replacing at least one “1” of the unit matrix with “0”, and Expressed as the sum of the shifted matrices produced by cyclically shifting the unit matrix or quasi-unit matrix, corresponding to the position of the unit matrix with a weight of 1, the quasi-unit matrix, or the position of "1" in the shifted matrix Data (ie, messages corresponding to edges belonging to an identity matrix, a quasi-unit matrix, or a shifted matrix) is stored at the same address (the same FIFO of FIFOs 300 ₁ through 300 ₆ ).

The data is also stored in storage areas of the third to ninth stages associated with the transformed parity check matrix H '.

Similarly, data is stored in FIFOs 300 ₃ through 300 ₆ associated with the transformed parity check matrix H '.

The edge data storage memory 304 has 18 FIFO 304 ₁ to 304 ₁₈ which is the same number obtained by dividing the number "90" of columns of the converted parity check matrix H 'by the number "5" of columns of each component matrix. Each FIFO 304 _x (x = 1, 2, ..., 18) simultaneously records each message corresponding to the "5" edge, which is the same number of rows and columns of each transformed component matrix H ' Or each storage area of a plurality of stages that can be read.

Data corresponding to positions "1" of the first to fifth columns of the transformed parity check matrix H 'of FIG. 33 (i.e., message u _i from the check node) simultaneously ignores "0" in the vertical direction of every column. Stored in FIFO 304 ₁ Specifically, data corresponding to the position "1" of the 5x5 unit matrix of (1,1) to (5,5) of the converted parity check matrix H 'is stored in the storage area of the first stage of FIFO 304 ₁ . Stored. A first shifted matrix generated by cyclically shifting a 5 × 5 unit matrix by one element to the right and a second shifted matrix generated by cyclically shifting the 5 × 5 unit matrix by two elements to the right. The data corresponding to the position of "1" of the first shifted matrix included in the sum matrix of (6,1) to (10,5) of the transformed parity check matrix H 'obtained by summing is stored in the second stage. Stored in the area. Data corresponding to the position of "1" of the second shifted matrix included in the sum matrix of (6,1) to (10,5) of the converted parity check matrix H 'is stored in the storage area of the third stage .

More specifically, a matrix of components having a weight of at least 2, at least two P × P unit matrices having a weight of 1, a quasi-unit matrix generated by replacing at least one “1” of the unit matrix with “0”, and Expressed as the sum of the shifted matrices produced by cyclically shifting the unit matrix or quasi-unit matrix, corresponding to the position of the unit matrix with a weight of 1, the quasi-unit matrix, or the position of "1" in the shifted matrix data (i.e., the unit matrix, quasi-messages corresponding to edges belonging to the unit matrix or shift matrix) are stored in the same address (FIFO 304 ₁ to 304 ₁₈ of the same FIFO).

The data is also stored in storage areas of the fourth and fifth stages associated with the transformed parity check matrix H '. The number of stages in the storage area of FIFO 304 ₁ is "5" equal to the maximum value of the number of 1s (hamming weight) in the row direction of the first to fifth columns of the transformed parity check matrix H '.

Similarly, data is stored in FIFOs 304 ₂ and 304 ₃ associated with the transformed parity check matrix H ', and the length of each FIFO (ie, the number of stages) is "5". Similarly, data is stored in FIFOs 304 ₄ through 304 ₁₂ associated with the transformed parity check matrix H ', and the length of each FIFO is "3". Similarly, data is stored in FIFOs 304 ₁₃ through 304 ₁₈ associated with the transformed parity check matrix H ', and the length of each FIFO is "2".

The operation of the decoding device of FIG. 34 will now be discussed.

In the edge data storage memory 300 including _six FIFOs 300 ₁ to 300 ₆ , five FIFOs storing data are received from a cyclic shift circuit 308 located above the edge data storage memory 300. According to the information (matrix data) D312 indicating the row of the converted parity check matrix H 'to which the message D311 belongs, it is selected from FIFOs 300 ₁ to 300 ₆ , and five messages D311 are collected and stored in order in the selected FIFO. When data is read from the edge data storage memory 300, first five messages D300 ₁ are read in sequence from the FIFO 300 ₁ and then provided to the selector 301 located below the edge data storage memory 300. . After the message is completely read from FIFO 300 ₁ , the message is read in order from FIFOs 300 ₂ to 300 ₆ of edge data storage memory 300 and then provided to selector 301 in the same manner.

The selector 301 selects five messages received from the FIFO from which data is currently being read out of the FIFO 300 ₁ to 300 ₆ according to the selection signal D301, and provides the selected message to the test node calculation unit 302 as the message D302. .

The check node calculator 302 includes five check node calculators 302 ₁ to 302 ₅ and includes a message D302 (corresponding to the message v _i of equation 7) received through the selector 301 (D302 ₁ to D302 _5). ), The check node calculation is performed according to equation (7), and five messages D303 (D303 ₁ to D303 ₅ ) obtained through check node calculation are provided to the cyclic shift circuit 303.

The cyclic shift circuit 303 checks the inspection node based on the information (matrix data) D305 indicating the number of elements whose original unit matrix is cyclically shifted to obtain corresponding respective edges of the converted parity check matrix H '. The five messages D303 ₁ to D303 ₅ obtained by the calculation unit 302 are cyclically shifted to provide the edge data storage memory 304 with the cyclically shifted message as the message D304.

In the edge data storage memory 304 comprising ₁₈ FIFOs 304 ₁ to 304 ₁₈ , five FIFOs storing data are received from a cyclic shift circuit 303 located above the edge data storage memory 304. According to the information D305 indicating the row of the transformed parity check matrix H 'to which the message D304 belongs, it is selected from FIFO 304 ₁ to 304 ₁₈ , and five messages D304 are collected and stored in order in the selected FIFO. When data is read from the edge data storage memory 304, first five messages D306 ₁ are read in sequence from FIFO 304 ₁ and then provided to the selector 305 located below the edge data storage memory 304. . After the data has been completely read from FIFO 304 ₁ , the messages are read in order from FIFO 304 ₂ through 304 ₁₈ of edge data storage memory 304 and then provided to selector 305 in the same manner.

The selector 305 selects five messages received from the FIFO from which data is currently being read out of the FIFO 304 ₁ to 304 ₁₈ according to the selection signal D307, and selects the selected message as the message D308 as the variable node calculator 307 and the decoding word. Provided to both calculators 309.

On the other hand, the received data substitution unit 310 performs the column substitution of Equation (9) to replace the LDPC code D313 received through the communication path, and the resulting data data received as the received data D314 as the data memory 306 To provide. The received data memory 306 calculates and stores the reception log likelihood ratio (LLR) from the data D314 received from the received data replacement unit 310, and stores the received LLRs of the five LLR groups as the received value D309. The calculation unit 307 and the decoding word calculation unit 309 are provided to both.

The variable node calculator 307 includes five variable node calculators 307 ₁ to 307 ₅ , and receives the message D308 (corresponding to the message u _j of Equation 1) received through the selector 305 (D308 ₁ to D308 _5). Variable node calculation according to Equation 1 using the five received values D309 (corresponding to the received value u _0i of Equation 1) received from the received data memory 306). The five messages D310 (D310 ₁ to D310 ₅ ) (corresponding to the message v _i of Equation 1) obtained through Equation 1 are provided to the cyclic shift circuit 308.

The cyclic shift circuit 308 cyclically shifts five messages D310 ₁ to D310 ₅ calculated by the variable node calculator 307 based on the information indicating the number of elements, thereby converting the parity check matrix. The original unit matrix is cyclically shifted to obtain each corresponding edge of H 'and provides the edge data storage memory 300 with a cyclically shifted message, such as message D311.

The LDPC code can be decoded once by performing the operations once. After decoding the LDPC code over a predetermined number of times, the decoding apparatus of FIG. 34 obtains and outputs the final decoded data through the decoded word calculator 309 and the decoded data replacer 311.

More specifically, the decoding word calculator 309 includes five decoding word calculators 309 ₁ to 309 ₅ , and as the final processing of the plurality of decoding procedures, output from the selector 305 (Equation 5) Receive five received values D309 (corresponding to received value u _0i of Equation 5) from five messages D308 (D308 ₁ to D308 ₅ ) and received data memory 306 corresponding to message u _j ). The decoded data (eg, a decoded word) is calculated based on Equation 5, and the calculated decoded data D315 is provided to the decoded data replacer 311.

The decoded data replacer 311 performs inversion of the column substitution of Equation 9 on the decoded data D315 received from the decoded word calculator 309, changes the order of the decoded data D315, and then results in the final decoded data D316. Output the data.

As described above, at least one of row substitution and column substitution is performed on a parity check matrix (eg, the original parity check matrix) to convert it into a parity check matrix (eg, a converted parity check matrix). The parity check matrix may be represented by a combination of component matrices. That is, a P × P unit matrix, generated by cyclically shifting a quasi-unit matrix, a unit matrix or a quasi-unit matrix, generated by replacing one or more "1s" of the unit matrix with "0" s. It may be expressed as a combination of a sum matrix generated by adding a shifted matrix, two or more unit matrices, a quasi-unit matrix, or a shift matrix and a P × P zero matrix. By this parity check matrix transformation, it is possible to use an architecture that simultaneously performs P check node calculation and P variable node calculation when the LDPC code is decoded. Performing P-node calculations simultaneously limits the operating frequency to a sufficiently reachable range, thereby allowing decoding to be performed several times.

Similar to the decoding apparatus of FIG. 34, the LDPC decoder 56 included in the receiver 12 of FIG. 29 is designed to decode the LDPC code by simultaneously performing P check node calculation and P variable node calculation.

More specifically, for ease of explanation, it is assumed that the parity check matrix of the LDPC code output from the LDPC encoder 21 included in the transmitter 11 of FIG. 8 is the parity check matrix H in which the parity matrix has a stepped structure. The parity interleaver 23 of the transmitter 11 performs parity interleaving to interleave the K + qx + y + 1st code bits to the K + Py + x + 1st code bit positions, and the information length K is "60." ", The unit number P of the column which has a cyclic structure is 5, and the divisor q (= M / P) of the parity length M is" 6 ".

Since parity interleaving corresponds to the column substitution of Equation 9 described above, the LDPC decoder 56 does not need to perform the column substitution of Equation 9.

Therefore, in the receiver 12 of FIG. 29, an LDPC code that is not parity deinterleaved, that is, an LDPC code that has undergone thermal substitution of Equation 9, is provided from the thermal twist deinterleaver 55 to the above-described LDPC decoder 56. do. The LDPC decoder 56 performs the same processing as that of the decoding apparatus of FIG. 34 except that the thermal substitution of Equation 9 is not performed in the LDPC decoder 56.

More specifically, FIG. 35 shows an exemplary configuration of the LDPC decoder 56 of FIG. 29.

The LDPC decoder 56 shown in FIG. 35 has the same configuration as that of the decoding apparatus of FIG. 34 except that the reception data replacement unit 310 of FIG. 34 is not provided, and the thermal substitution of Equation 9 is performed by the LDPC decoder. Since the same processing as that of the decoding apparatus of FIG. 34 is performed except that the processing is not performed at 56, the same description of the configuration and processing is omitted herein.

Since the LDPC decoder 56 may be configured without the reception data replacer 310 described above, the size of the LDPC decoder 56 may be smaller than that of the decoding apparatus of FIG. 34.

For ease of explanation, FIGS. 31 to 35 show that the code length N of the LDPC code is 90, the information length K is 60, and the unit number P of the columns having a recursive structure (e.g., the number of rows of the component matrix and the number of columns). Divisor q (= M / P) of parity length M is 6, code length N is described with reference to an example, but information length K, the number of units P and divisor q of a column having a recursive structure (= M / P) is not limited to this value.

Accordingly, in the LDPC encoder 21 of the transmitter 11 of FIG. 8, for example, the code length N is 64800, the information length K is N-Pq (= NM), and the number P of columns having a cyclic structure is 360, While the divisor q outputs an LDPC code of M / P, the LDPC decoder 56 of FIG. 35 can be applied to DLPC-decode the LDPC code by performing P check node calculation and P variable node calculation simultaneously.

The above series of processing can be performed by software as well as hardware. When a series of processing is performed by software, a program for implementing the software is installed in a general purpose computer or the like.

36 shows an exemplary configuration of an embodiment of a computer including a program for performing the above series of processes.

The program can be recorded in advance in the hard disk 405 or the ROM 403 as a recording medium built into the computer.

The program may also be temporarily stored on a removable recording medium 411 such as a floppy disk, compact disc-read only memory (CD-ROM), magneto-optical disc (MOD), digital versatile disc (DVD), magnetic disk, or semiconductor memory. Or permanently stored (or recorded). The removable recording medium 411 may be provided as a software package.

Instead of installing the program from the above-described removable recording medium 411 to a computer, the program is wirelessly transmitted from the download site to the computer via a satellite for digital satellite broadcasting, or via a network such as a local area network or the Internet. The computer may be wired to a computer, and the computer may receive a program transmitted through the communication unit 408 and install the received program in a hard disk 405 embedded in the computer.

The computer may include a CPU 402. The CPU 402 is connected to the input / output (IO) interface 410 via the bus 401. The CPU 402 executes a program stored in a ROM 403 (read only memory) when a command input by a user, for example, a keyboard, a mouse, a microphone, or the like, is received through the IO interface 410. Run Alternatively, CPU 402 loads into random access memory (RAM) 404 and executes the program stored on hard disk 405. The executed program was installed in the hard disk 405 after being received from the satellite or network through the communication unit 408, or read in from the removable recording medium 411 installed in the drive 409 and then installed in the hard disk 405. Program. By executing the program in this manner, the CPU 402 performs the process described above with reference to the flowchart or the process performed by the above-mentioned component with reference to the block diagram. Then, if necessary, the CPU 402 outputs a result of the processing through the output unit 406 including, for example, an LCD, a speaker, or the like via the I / O interface 410, or the processing through the communication unit 408. The results are transmitted or the processing results are recorded in the hard disk 405.

In the above description, the steps describing a program for causing a computer to perform various types of processing need not necessarily be performed in the time order described above with reference to the flowchart, and may be performed in parallel or independently (for example, parallel processing or object-oriented processing). Can be performed).

The program can be executed by one computer or by multiple computers in a distributed environment. Also, the program can be sent to the remote computer so that it can be executed at the remote computer.

Those skilled in the art will understand that embodiments of the present invention are not limited to the above description, and that various modifications can be made without departing from the scope of the present invention as set forth in the appended claims.

More specifically, although parity interleaving or column twist interleaving, which is a substitution process, is performed for the LDPC code defined in the DVB-S.2 specification of the previous embodiment, parity interleaving is a parity check matrix in which the information matrix does not have a cyclic structure. Assuming that the parity matrix of the parity check matrix is a stepped structure, column twist interleaving as a substitution process may be, for example, a QC-LDPC code of a parity check matrix having at least column replacement or an overall cyclic structure. (Quasi-Cyclic-LDPC code) can be applied to the LDPC code of the parity check matrix converted to a pseudo cyclic structure (pseudo cyclic structure).

That is, the parity check matrix of the parity interleaved LDPC code only needs to include a parity matrix having a stepped structure, and does not need to include an information matrix having a cyclic structure.

The parity check matrix of the LDPC code that is column twist interleaved as the substitution process is not limited to any specific structure.

In addition, the substitution process only needs to be able to substitute the code bits of the LDPC code such that a plurality of code bits corresponding to "1" of any row of the parity check matrix are not combined into the same symbol, and a method other than column twist interleaving. It can be performed using. More specifically, the substitution process can be performed, for example, by controlling the write and read address using a memory in which data is stored only in one direction instead of the memory 31 in which data is stored in the row and column directions.

Symbol interleaver

It has been proposed to extend the number of valid modes within the DVB-T2 standard to include 1k mode, 16k mode and 32k mode. The following description is provided to explain the operation of the symbol interleaver according to the present technology, and it can be appreciated that the symbol interleaver can be used in other modes and in the DVB standard.

To create a new mode, several elements are defined, one of which is the symbol interleaver 33. Bit array mapper 26, symbol interleaver 33, and frame builder 32 are shown in greater detail in FIG.

As described above, the present invention provides a technique for quasi-optimal mapping of data symbols to OFDM subcarrier signals. According to an exemplary technique, a symbol interleaver is provided to achieve an optimized mapping of input data symbols to OFDM subcarrier signals according to substitution codes and generation polynomials, which have been verified by simulation analysis. Therefore, symbol interleaver combines bit interleaver and LDPC encoding to improve the performance of data communication on the same communication channel as the channel proposed for DVB.

As shown in FIG. 37, a more detailed illustration showing the bit symbol arrangement mapper 26 and frame builder 32 is provided to illustrate an exemplary embodiment of the present invention. Data bits received from the bit interleaver 26 via the channel 62 are grouped into bit sets according to a number of bits per symbol provided by the modulation scheme, and mapped into data cells. Groups of bits forming the data word are provided in parallel to the mapping processor 66 via the data channel 64. The mapping processor 66 then selects one of the data symbols according to the pre-assigned mapping. Constellation points, represented by real and imaginary components, are provided to output channel 29 as one of a set of inputs to frame builder 32.

Frame builder 32 receives data cells from bit array mapper 28 over channel 29, along with data cells from other channels 31. After creating frames of a plurality of OFDM cell sequences, cells of each OFDM symbol are written to and read from the interleaver memory 100 in accordance with the write address and read address generated by the address generator 102. Depending on the write and read order, interleaving of data cells can be achieved by generating the appropriate addresses. Operations of the address generator 102 and the interleaver memory 100 will be described in more detail with reference to FIGS. 38 to 40. The interleaved data cell is combined with the pilot and synchronization symbols received from the pilot and embedded signal generator 36 to the OFDM symbol generator 37 and then forms an OFDM symbol, the OFDM symbol described above with the OFDM modulator 38. Is provided.

38 provides exemplary portions of a symbol interleaver 33 describing the present invention for interleaving symbols. In FIG. 38, data cells input from the frame builder 32 are written to the interleaver memory 100. The data cells are written to the interleaver memory 100 according to the write address provided from the address generator 102 on the channel 104, and the interleaver memory 100 according to the read address provided from the address generator 102 on the channel 106. Is read from The address generator 102 generates a write address and a read address according to whether the OFDM symbol is odd or even and the selected mode, as will be described later. Whether the OFDM symbol is odd or even is identified from the signal provided from channel 108 and the selected mode is identified from the signal provided from channel 110. As described, the mode may be one of 1k mode, 2k mode, 4k mode, 8k mode, 16k mode or 32k mode. As described below, the write address and read address are generated differently for the odd and even symbols described with reference to FIG. 39, which provides an exemplary implementation of the interleaver memory 100. As shown in FIG.

In the example shown in FIG. 39, the interleaver memory is shown to include a top 100 describing the operation of the interleaver memory of the transmitter and a bottom 340 describing the operation of the deinterleaver memory of the receiver. The interleaver 100 and the deinterleaver 340 are shown together to facilitate understanding of the operation of the interleaver memory and the deinterleaver memory. As shown in FIG. 39, communication between the interleaver 100 and the deinterleaver 340 via other devices and transmission channels is briefly represented by the zone 140 between the interleaver 100 and the deinterleaver 340. The operation of the interleaver 100 is described in the following paragraphs.

Although FIG. 39 illustrates only four input data cells on the four exemplary subcarrier signals of an OFDM symbol, the technique described in FIG. 39 applies to 756 for 1k mode, 1512 for 2k mode, 3024 for 4k mode, and 8k mode. It can be extended to a large number of subcarriers such as 6048 for 1648 mode, 12096 for 16k mode, and 24192 for 32k mode.

The input / output addressing of the interleaver memory 100 shown in FIG. 39 is for odd and even symbols. For even OFDM symbols, data cells are extracted from input channel 120 and written to interleaver memory 124.1 according to a series of addresses 120 generated for each OFDM symbol by address generator 102. Write addresses are applied for even symbols so that the described interleaving is achieved by shuffling write addresses. Therefore, y (h (q)) = y '(q) for each interleaved symbol.

The same interleaver memory 122.4 is used for odd symbols. However, as shown in FIG. 39 for odd symbols, the write order 132 is the same address sequence that was used to read the previous even symbol 126. Assuming that a read operation for a given address is performed before a write operation, this characteristic allows odd and even symbol interleaver execution to use only one interleaver memory 100. Data cells written to interleaver memory 124 during odd symbols are read into sequence 134 generated by address generator 102 for subsequent even OFDM symbols and the like. Therefore only one address is generated for one symbol, and reading and writing for odd / even OFDM symbols are performed simultaneously.

In summary, as represented in FIG. 39, if the set of address H (q) is computed for all active subcarriers, the input vector Y '= (y ₀ ', y ₁ ', y ₂ ', ... y _{Nmax -1} ') is processed to generate an interleaved vector Y = (y ₀ , y ₁ , y ₂ , ... y _Nmax-1 ), and the interleaved vector is defined as follows.

q = 0, ..., N y _{H (q)} = for even symbols for _max -1  y ' _q

q = 0, ..., N For odd symbols for _max -1 y _q = y ' _{H (q)}

That is, the input words are written to the memory in an alternate manner for even OFDM symbols and read back sequentially, while for odd symbols they are sequentially written and read again in an alternate manner. In the above cases, the substitution H (q) is defined in the table below.

q 0 One 2 3 H (q) One 3 0 2

Substitution in the simple case where Nmax = 4

As shown in FIG. 39, the deinterleaver 340 applies the same set of addresses generated by the equivalent address generator but reversely applies interleaving applied by the interleaver 100 by applying the write and read addresses back. It works. As such, for even symbols, the write address 342 is in sequential order, while the read address 344 is provided by the address generator. Thus, for odd symbols, the write order 346 is determined from the address set generated by the address generator, while the read 348 is in sequential order.

Address generation for operating modes

A schematic block diagram of the algorithm used to generate the substitution function H (q) is shown in FIG. 40 for the 32k mode. However, the 32k mode interleaver of FIG. 40 can be used to operate as an interleaver according to the 1K, 2K, 4K, 8K or 16K mode by appropriately selecting and using the generated polynomials and substitution codes described below.

In FIG. 40, a linear feedback shift register is formed by an exclusive OR-gate 202 coupled to the thirteen register stages 200 and the stage 200 of the shift registers in accordance with a generation polynomial. Therefore, in accordance with the contents of the shift register 200, by performing an exclusive OR on the contents of the shift registers R [0], R [1], R [2], R [12] according to the following generation polynomial: The next bit of the shift register is provided from the output of the exclusive OR-gate 202.

R'_i-1[1]

R'_i-1[2]

R'_i-1[12]R ' _i [13] = R' _i-1 [0]

R ' _i-1 [1]

R ' _i-1 [2]

R ' _i-1 [12]

According to the generation polynomial, a pseudo random bit sequence is generated from the contents of the shift register 200. However, in order to generate an address for the described 32k mode, the order of the bits in the output when the shift register 200.1 a substitution circuit _{(210) R 'i [n} ] from the R _i [n] to substitution circuit (210 to efficiently substituted ) Is provided. Fourteen bits from the output of the substitution circuit 210 are provided to the connection channel 212 and the most significant bit is provided via the channel 214 via the toggle circuit 218 via the connection channel 212. Is added. Thus, 15 bit addresses are generated on channel 212. However, to ensure the authenticity of the address, the address check circuit 216 analyzes the generated address to determine if it exceeds a predetermined maximum value. The predetermined maximum value corresponds to the maximum number of subcarrier signals, wherein the subcarrier signal is valid for the data signal in the OFDM signal and is valid for the mode in use. However, the interleaver for 32k mode is valid for other modes, and the address generator 102 can also be used for 2k mode, 4k mode, 8k mode, 16k mode and 32k mode by adjusting according to the maximum number of valid addresses. .

When the generated address exceeds the predetermined maximum value, a control signal is generated by the address checker 216 and provided to the controller 224 via the connection channel 220. If the generated address exceeds the predetermined maximum, this address is rejected and a new address is generated again for the particular symbol.

For 32k mode, the (N _r -1) bit word R ' _i is defined, where N _{r =} log ₂ M _max and M _{max =} 32768 when using the Linear Feedback Shift Register (LFSR).

The polynomial used to generate this sequence is:

R'_i-1[1]

R'_i-1[2]

R'_i-1[12]32K mode: R ' _i [13] = R' _i-1 [0]

R ' _i-1 [1]

R ' _i-1 [2]

R ' _i-1 [12]

i has a value from 0 to M _max −1.

_'I When the word is created, R' one R _i Ward another, referred to as _{R i} (N _r - 1) go through a substitution to generate a bit word, R _i is by the bit replacement is given below R _'i Derived from.

R ' _i bit position 13 12 11 10 9 8 7 6 5 4 3 2 One 0 R _i bit position 6 5 0 10 8 One 11 12 2 9 4 3 13 7

Bit substitution for 32k mode

By way of example, which for the 32k mode, R _'i bit number 12 of It is sent to bit position number 5 in R _i .

Then, the address H (q) is derived from R _i through the following equation.

부분은 도 40에서 토글 블록(toggle block) T 218로 표현된다.Gastric

The portion is represented by a toggle block T 218 in FIG. 40.

An address check is then performed on H (q) to verify that the generated address is within the range of acceptable addresses. For example, in 32k mode, when N _max = 24192 and H (q) <N _max , the address is valid. If the address is invalid, it is known to the controller, which attempts to generate a new H (q) by incrementing the index i.

The role of the toggle block is to make sure that you do not create an address twice in the row that exceeds N _max . In fact, if the excess value was generated, this means that the MSB (eg, toggle bit) of address H (q) was one. Thus, the next value generated will have an MSB set to 0, which guarantees to generate a valid address. The additional bits therefore reduce the likelihood that the next address is a valid address if the address exceeds a predetermined maximum valid address. In one example, the additional bit is the most significant bit (MSB).

The following formula summarizes the overall behavior and helps to understand the loop structure algorithm:

Address Generator Support Analysis

The selection of the substitution code and polynomial generator described above for the address generator 102 for each mode of operation, such as the 32k mode, is identified after simulation analysis on the relative performance of the interleaver. The relative performance of the interleaver was evaluated using the interleaver's relative ability to separate consecutive symbols or "interleaving quality". As mentioned above, to use a single interleaver memory, interleaving must be performed efficiently for both odd and even symbols. The relative measure of interleaver quality is determined by defining the distance D (in the number of subcarriers). A criterion C is selected to identify the number of subcarriers whose distance is less than D when the interleaver is input, and the distance is less than or equal to D, and the number of subcarriers for each distance D is weighted relative to the relative distance. Criteria C are evaluated for both odd and even symbols. Minimizing C produces the highest quality interleaver.

N _even (d) and N _odd (d) are the number of subcarriers of each of even and odd symbols that maintain the interval d between subcarriers at the output of the interleaver.

An analysis of the identified interleaver for the 32k mode for the value D = 5 is shown in FIG. 41 (a) for even OFDM symbols and in FIG. 41 (b) for odd OFDM symbols. According to the above analysis, the value of C for the substitution code identified for 32k mode is 21.75, and the weighted number of subcarriers of symbols separated by 5 or less in the output according to the above equation is 21.75.

Correspondence analysis is provided for the alternative substitution codes for the odd OFDM symbol in FIG. 41 (d) and the even OFDM symbol in FIG. 41 (c). As can be seen in comparison with the results shown in Figs. 41 (a) and 41 (b), components representing symbols separated by short distances such as D = 1 and D = 2 are shown in Fig. 41 (a). And more, compared to the results shown in FIG. 41 (b), which shows that the substitution code identified for the 32k mode symbol interleaver produces an interleaver of superior quality.

Alternative substitution codes

The following fifteen alternative codes ([n] R _i bit positions, where n is 1 to 15) have been provided to provide a good quality symbol interleaver as determined by reference C identified below.

R ' _i bit position 13 12 11 10 9 8 7 6 5 4 3 2 One 0 [1] R _i bit position 0 6 One 7 2 11 12 5 9 8 3 10 4 13 [2] R _i bit position 9 5 0 7 2 8 3 6 12 11 4 One 10 13 [3] R _i bit position 9 12 0 One 2 13 5 8 6 3 7 4 10 11 [4] R _i bit position 13 8 One 12 11 0 9 5 3 7 6 2 10 4 [5] R _i bit position 5 8 7 0 3 2 11 4 13 6 One 10 12 9 [6] R _i bit position 8 9 5 13 0 10 7 One 12 3 2 4 11 6 [7] R _i bit position 11 10 0 7 2 9 8 One 5 3 6 4 12 13 [8] R _i bit position 11 4 0 13 10 12 5 7 2 8 3 One 6 9 [9] R _i bit position 4 0 5 One 12 2 10 3 13 9 6 11 8 7 [10] R _i bit position 4 7 0 8 10 One 6 3 2 9 11 12 13 5 [11] R _i bit position 4 6 0 13 12 One 11 2 8 3 10 7 9 5 [12] R _i bit position 0 5 One 9 2 12 3 6 8 7 4 10 11 13 [13] R _i bit position 12 4 2 11 10 One 13 6 0 9 3 8 5 7 [14] R _i bit position 10 6 0 13 12 11 8 5 2 4 3 One 9 7 [15] R _i bit position 7 6 0 One 10 3 9 4 2 5 8 11 12 13

Bit substitution for 32k mode

Address generator for adaptive and different modes of symbol interleaver

As discussed above, the symbol interleaver shown in FIG. 40 can be adapted to interleaver symbols from other modes by simply changing the maximum effective address, the number of stages in the linear feedback shift register, and the substitution code. In particular, according to the above analysis, the following is established for each of the 1K, 2K, 4K, 8K and 16K modes.

1K mode

Maximum effective address: about 1000

Number of stages in the linear feedback shift register: 9

R'_i-1[4] Generation Polynomial: R ' _i [8] = R' _i-1 [0]

R ' _i-1 [4]

Substitution code:

R ' _i bit position 8 7 6 5 4 3 2 One 0 R _i bit position 4 3 2 One 0 5 6 7 8

2K mode

Maximum effective address: approximately 2000

Number of stages in the linear feedback shift register: 10

R'_i-1[3]Generation Polynomial: R ' _i [9] = R' _i-1 [0]

R ' _i-1 [3]

Substitution code:

R ' _i [n] bit position 9 8 7 6 5 4 3 2 One 0 R _i [n] Bit position 0 7 5 One 8 2 6 9 3 4

4K mode

Maximum effective address: about 4000

Number of stages in the linear feedback shift register: 11

R'_i-1[2]Generation Polynomial: R ' _i [10] = R' _i-1 [0]

R ' _i-1 [2]

Substitution code:

R ' _i [n], n = 10 9 8 7 6 5 4 3 2 One 0 While R _i [n], n = 7 10 5 8 One 2 4 9 0 3 6

8K mode

Maximum effective address: about 8000

Number of stages in the linear feedback shift register: 12

R'_i-1[1]

R'_i-1[4]

R'_i-1[6]Generation Polynomial: R ' _i [11] = R' _i-1 [0]

R ' _i-1 [1]

R ' _i-1 [4]

R ' _i-1 [6]

Substitution code:

R ' _i bit position 11 10 9 8 7 6 5 4 3 2 One 0 R _i bit position 5 11 3 0 10 8 6 9 2 4 One 7

16K mode

Maximum effective address: about 16000

Number of stages in the linear feedback shift register: 13

Produce polynomial:

R'_i-1[1]

R'_i-1[4]

R'_i-1[5]

R'_i-1[9]

R'_i-1[11]R ' _i [12] = R' _i-1 [0]

R ' _i-1 [1]

R ' _i-1 [4]

R ' _i-1 [5]

R ' _i-1 [9]

R ' _i-1 [11]

Substitution code:

R ' _i bit position 12 11 10 9 8 7 6 5 4 3 2 One 0 R _i bit position 8 4 3 2 0 77 7 5 12 10 6 7 9

Additional description of the symbol interleaver in the receiver

Returning to the interleaver shown in FIG. 29, as shown in FIG. 42 with the interleaver memory 540 and address generator 542, a symbol de-interleaver 514 is generated from the data processing apparatus. The interleaver memory 540 is shown in FIG. 39 and operates as described above to achieve de-interleaving by utilizing the address set generated by the address generator 542. An address generator 542 is formed as shown in FIG. 40, which is configured to generate a corresponding address to map the data symbols recovered from each OFDM subcarrier signal into the output data stream.

The remainder of the OFDM receiver shown in FIG. 29 affects error correction decoding 518 of LDPC encoded data bits, correcting errors and restoring evaluation of source data.

One advantage that the current technology provides for both receivers and transmitters is that symbol interleavers and symbol deinterleavers operating in receivers and transmitters can be modified in 1k, 2k, 4k, 8k, 16k, and 32k modes by changing the generation polynomials and the order of substitution. Can be switched between. Therefore, the address generator 542 shown in FIG. 42 includes an input 544 indicating a mode and an input 546 indicating whether an odd / even OFDM symbol is present. Thus, a symbol interleaver and de-interleaver together with the address generator shown in FIG. 40 can be formed as shown in FIGS. 38 and 42, thereby providing a flexible implementation. Thus, the address generator can be adapted to other modes by changing the generation polynomial and changing the order of substitution shown for each mode. For example, this can be accomplished using software changes. Alternatively, in another embodiment, an embedded signal indicative of the DVB-T2 transmission mode may be detected at a receiver in the embedded signal processing unit 511 and automatically configures the symbol de-interleaver according to the detected mode. Can be used.

Alternatively, as described above, by simply adapting the maximum valid address according to the mode used, other interleavers can be used with different modes.

Optimized use of odd interleaver

As shown in FIG. 39, two symbol interleaving processes (one for even OFDM symbols and the other for odd OFDM symbols) allow the amount of memory used during interleaving to be reduced. In the example shown in Fig. 39, since the writing order for odd symbols is the same as the reading order for even symbols, while the odd symbols are read from the memory, the even symbols can be written to the just-read position, and then even If a symbol is read from the memory, subsequent odd symbols can be written to the place just read.

As discussed above, for example, shown in Figures 43 (a) and 43 (b), while performing an experimental analysis of the performance of the interleaver (using reference C described above), a 4k symbol interleaver for DVB-H is used. We have found that an interleaving scheme consisting of 2k and 8k symbol interleavers for DVB-T, works better on odd symbols than even symbols. Therefore, it is found from the evaluation results of the interleaver that the odd interleaver performs better than the even interleaver, for example, as described by FIGS. 43 (a) and 43 (b). This can be seen by comparing FIG. 43 (a) showing the result of the interleaver with even symbols and FIG. 43 (b) showing the result with odd symbols. It can be seen that the average distance at the interleaver output of the subcarrier adjacent to the interleaver input is greater for the interleaver for odd symbols than for the interleaver for even symbols.

As can be appreciated, the amount of interleaver memory required to implement the symbol interleaver depends on the number of data symbols mapped to the OFDM carrier symbol. Therefore, the 16k mode symbol interleaver requires half of the memory required to implement the 32k mode symbol interleaver, and similarly the amount of memory required to implement the 8k symbol interleaver is half that required to implement the 16k interleaver. Therefore, the transmitter and receiver are configured to implement a symbol interleaver in a mode that sets the maximum number of data symbols that can be carried per OFDM symbol, thereby providing less than half the number of subcarriers per OFDM symbol in a predetermined maximum mode. Enough memory to implement two odd interleaving processes for any other mode. For example, a receiver and transmitter that include a 32k interleaver have enough memory to accommodate two 16k odd interleaving processes, each with its own 16k memory.

Therefore, in order to develop better performance of odd interleaving processing, a symbol interleaver that can accommodate multiple modulation modes is a mode that includes less than half the number of subcarriers in the maximum mode indicating the maximum number of subcarriers per OFDM symbol. Only odd symbol interleaving processing can be configured to be used. Therefore, this maximum mode sets the maximum memory size. For example, in a transmitter / receiver capable of 32K mode, when operating in a mode of fewer carriers (ie 16K, 8K, 4K or 1K), two odd interleavers may be used rather than using separate odd and even symbol interleaving processing. Can be.

In the case of interleaving the input data symbols with subcarriers of the OFDM symbols only in the odd interleaving mode, a description of the adaptation of the symbol interleaver 33 shown in FIG. 38 is shown in FIG. As shown in FIG. 38, the symbol interleaver 33.1 corresponds exactly to the symbol interleaver 33, except that the address generator 102.1 is adapted to perform only odd interleaving processing. In the example shown in FIG. 44, the symbol interleaver 33.1 shows that the number of data symbols that can be carried per OFDM symbol is half the maximum number that can be transmitted by an OFDM symbol in the operating mode as the maximum number of subcarriers per OFDM symbol. Operate in less mode. As such, the symbol interleaver 33.1 is configured to divide the interleaver memory 100. In the technique shown in FIG. 44, the interleaver memory 100 is divided into two parts 601, 602. As an illustration of symbol interleaver 33.1 operating in a mode in which data symbols are mapped to OFDM symbols using odd interleaver processing, FIG. 44 shows an expanded view of each half of interleaver memories 601 and 602. to provide. The expanded view provides a description of the odd interleaving mode as shown for the transmitter side for the four symbols A, B, C, D reproduced from FIG. 39. Thus, as shown in FIG. 44, for a contiguous set of first and second data symbols, the data symbols are written to the interleaver memories 601 and 602 in a contiguous order and, as already described, generated by the address generator. It is read in accordance with the address generated by the address generator 102 in the order of substitution according to the received address. Therefore, as shown in Fig. 44, since the odd interleaving process is performed for a continuous set of first and second sets of data symbols, the interleaver memory must be divided into two parts. Since the symbol interleaver no longer reuses the same portion of the symbol interleaver memory that can be accommodated when operating in odd and even interleaving modes, the symbols from the first set of data symbols are taken from the first half of the interleaver memory 601. And symbols from the second set of data symbols are written to the second portion of the interleaver memory 602.

Although shown in FIG. 42, a corresponding example of an interleaver of a receiver adapted to operate only by odd interleaving processing is shown in FIG. As shown in FIG. 45, the interleaver memory 540 is divided into two halves 710 and 712, and the address generator 542 writes data symbols into the interleaver memory and stores the data symbols from the interleaver memory. It is adapted to read data symbols into each part, such that successive sets of data symbols implement only odd interleaving processing. Therefore, corresponding to the indication shown in FIG. 44, FIG. 45 is shown in FIG. 39 as an expanded view operating for both the first and second halves of interleaving memories 710, 712 and mapping of interleaving processes performed at the receiver. Indicates. Therefore, the first data symbol set is in a substitution order defined according to an address generated by the address generator 542 as described by the recording order of the data symbols providing the recording sequences of 1, 3, 0, 2. It is written to the first portion of the interleaver memory 710. As described, the data symbols are read from the first portion of the interleaver memory 710 in sequential order to recover the original sequences A, B, C, D.

Accordingly, a second subsequent set of data symbols recovered from successive OFDM symbols is written to the second half of the interleaver memory 712 according to the address generated by the address generator 542 in replacement order and in sequential order. Is read into the output data stream.

In one embodiment, an address generated such that a first set of data symbols is written to the first half of interleaver memory 710 may be reused such that a second subsequent set of data symbols is written to interleaver memory 712. Accordingly, the transmitter can also reuse the address generated for half of the interleaver so that the first set of data symbols reads the second set of data symbols written to the second half of the memory in sequential order.

Use substitution sequences

In one embodiment, the address generator may apply different substitution codes from the substitution code set for consecutive OFDM symbols. Using the substitution sequence in the interleaver address generator reduces the likelihood that any bit of data input to the interleaver will not always modulate the same subcarrier in the OFDM symbol. In another example, two address generators may be used, one generating an address for the first set of data symbols and the first half of the memory, and the other generating the second set of data symbols and the second half of the memory. To generate addresses of different sequences. The second address generator can, for example, differently select a substitution code from the preferred substitution table.

For example, a cyclic sequence may be used such that different substitution codes of a sequence of substitution code sets are used and repeated for successive OFDM symbols. This circular sequence may for example have a length of two or four. In the example of a 16K symbol interleaver, one sequence of two substitution codes that are cycled every OFDM symbol is, for example:

8 4 3 2 0 11 1 5 12 10 6 7 9

7 9 5 3 11 1 4 0 2 12 10 8 6

In contrast, one sequence of four substitution codes may be as follows:

8 4 3 2 0 11 1 5 12 10 6 7 9

7 9 5 3 11 1 4 0 2 12 10 8 6

6 11 7 5 2 3 0 1 10 8 12 9 4

5 12 9 0 3 10 2 4 6 7 8 11 1

Exchanging one substitution code with another substitution code may be achieved in response to a change in the odd / even signal shown in the control channel 108. The control unit 224 changes the substitution code of the substitution code circuit 210 via the control line 111.

In the example of 1k symbol interleaver, the two substitution codes may be as follows:

4 3 2 1 0 5 6 7 8

3 2 5 0 1 4 7 8 6

On the other hand, the four substitution codes can be:

4 3 2 1 0 5 6 7 8

3 2 5 0 1 4 7 8 6

7 5 3 8 2 6 1 4 0

1 6 8 2 5 3 4 0 7

Other sequence combinations may be possible for 2k, 4k and 8k carrier modes or indeed 0.5k carrier modes. For example, the substitution codes described below for 0.5k, 2k, 4k and 8k each provide good de-correlation of symbols and generate an offset in the address generated by the address generator for each mode. Can be used periodically to:

2k mode:

0 7 5 1 8 2 6 9 3 4 *

4 8 3 2 9 0 1 5 6 7

8 3 9 0 2 1 5 7 4 6

7 0 4 8 3 6 9 1 5 2

4k mode:

7 10 5 8 1 2 4 9 0 3 6 **

6 2 7 10 8 0 3 4 1 9 5

9 5 4 2 3 10 1 0 6 8 7

1 4 10 3 9 7 2 6 5 0 8

8k mode:

5 11 3 0 10 8 6 9 2 4 1 7 *

10 8 5 4 2 9 1 0 6 7 3 11

11 6 9 8 4 7 2 1 0 10 5 3

8 3 11 7 9 1 5 6 4 0 2 10

For the substitution code shown above, the first two can be used in two sequence cycles, and for all four can be used in four sequence cycles. In addition, some other sequences of four substitution codes that are cycled to provide an offset in the address generator that produce good de-correlation within an interleaved symbol (some of which are common to those described above) are as follows:

0.5k mode:

3 7 4 6 1 2 0 5

4 2 5 7 3 0 1 6

5 3 6 0 4 1 2 7

6 1 0 5 2 7 4 3

2k mode:

0 7 5 1 8 2 6 9 3 4 *

3 2 7 0 1 5 8 4 9 6

4 8 3 2 9 0 1 5 6 7

7 3 9 5 2 1 0 6 4 8

4k mode:

7 10 5 8 1 2 4 9 0 3 6 **

6 2 7 10 8 0 3 4 1 9 5

10 3 4 1 2 7 0 6 8 5 9

0 8 9 5 10 4 6 3 2 1 7

8k mode:

5 11 3 0 10 8 6 9 2 4 1 7 *

8 10 7 6 0 5 2 1 3 9 4 11

11 3 6 9 2 7 4 10 5 1 0 8

10 8 1 7 5 6 0 11 4 2 9 3

* This is a substitution in the DVB-T standard.

** This is a substitution in the DVB-H standard.

Examples of address generators and corresponding interleavers for 2k, 4k, 8k modes are described in European Patent Application No. 04251667.4, the contents of which are incorporated herein by reference. The address generator for the 0.5k mode is described in pending patent application number 0722553.5.

Various further aspects in the features of the invention are defined by the independent claims. Various modifications may be made to the above-described embodiments without departing from the scope of the invention. In particular, examples of production polynomials and substitution orders used to represent aspects of the invention are not intended to be limiting and extend to equivalents of production polynomials and substitution orders.

It is to be understood that each of the transmitters and receivers shown in FIGS. 1 and 7 is for illustrative purposes and is not limited thereto. For example, it will be appreciated that the positions of the bit interleaver and the symbol interleaver and de-interleaver relative to the mapper and de-mapper may vary. Even if the interleaver is an interleaving I / Q symbol rather than a v-bit vector, it will be appreciated that the effects of the interleaver and de-interleaver do not vary with relative position. Correspondingly, the receiver can be changed. Accordingly, the interleaver and de-interleaver will operate on different data types and may be located differently from the positions described in the example embodiments.

As described above, the generated polynomial and the substitution code of the interleaver can be equally applied to other modes by changing the maximum allowable address selected according to the number of carriers for the mode.

According to one implementation of the receiver, a data processing apparatus is operable to map data symbols received from a predetermined number of subcarrier signals of Orthogonal Frequency Division Multiplexed (OFDM) symbols to an output data stream.

As described above, embodiments of the present invention disclose applications in which DVB standards such as DVB-T, DVB-T2, and DVB-H, which are incorporated herein by reference, are used. For example, embodiments of the present invention may be used in transmitters or receivers that operate specifically in accordance with the DVB-T2 standard according to the ETSI standard EN 302 755, but the present invention is not limited to applications where DVB is used, It can be extended to other standards for fixed or mobile receivers or transmitters. In another example, an embodiment of the present invention uses a cable transmission standard known as DVB-C2.

In addition to the exemplary embodiments described above and aspects and features of the invention defined by the claims, other embodiments provide a data processing apparatus operable to map input symbols to be communicated with a predetermined number of subcarrier signals of OFDM symbols. can do. The predetermined number of subcarrier signals corresponds to a modulation mode, and the input symbols include odd data symbols and even data symbols. The data processing apparatus includes an interleaver operable to perform a first interleaver process of interleaving an odd input data symbol to a subcarrier signal and an even interleaving process of interleaving an even input data symbol into a subcarrier signal. The first odd interleaving process and the even interleaving process input and read data symbols for mapping to an OFDM subcarrier signal. The reading is performed in a different order than the input so that while the odd symbols are read at one location in the memory, the even symbols can be written to the just read location, and if the even symbols are read from that location in the memory, the subsequent odd The symbol can be written to the position just read. The odd interleaving process inputs and reads odd data symbols from the interleaver memory according to the odd interleaving scheme, and the even interleaving process inputs and reads even data symbols from the interleaver memory according to the even interleaving scheme. When the modulation mode is a mode that includes less than half of subcarrier signals relative to the total number of subcarriers that can be accommodated by the interleaver memory, the data device is interleaved according to the first and second odd interleaving processing of interleaving even input symbols. Assign a portion of the memory to the first odd interleaving process, and assign a second portion of the interleaving memory to the second odd interleaving process.

According to another exemplary embodiment, the data processing apparatus is operable to map input symbols to be communicated with a predetermined number of subcarrier signals of OFDM symbols. The predetermined number of subcarrier signals correspond to a modulation mode, and the input symbol includes a first data symbol for mapping to a first OFDM symbol and a second data symbol for mapping to a second OFDM symbol. The data processing apparatus includes an interleaver operable to perform an odd interleaving process of interleaving a first input data symbol into a subcarrier signal and an even interleaving process of interleaving a second input data symbol into a subcarrier signal. The odd interleaving process writes the first input data symbol into the interleaver memory according to the sequential order of the first input data symbol, reads the first data symbol from the interleaver memory into the subcarrier signal according to the order defined by the replacement code. The even interleaving process writes the second input data symbol into the interleaver memory according to the order defined by the substitution code, and reads the second data signal from the interleaver memory into the subcarrier signal according to the sequential order, thereby providing the first input data symbol. Once read from one position in the interleaver memory, the second symbol is written to the position just read, and if the second symbol is read from the position of the interleaver memory, the subsequent first symbol can be written to the position just read. If the modulation mode is a mode that includes a subcarrier signal that is less than half the total number of subcarriers acceptable by the interleaver memory, the data device is operable to interleave both the first and second input symbols in accordance with the odd interleaving process.

 Another example embodiment may provide a method for mapping input symbols to be communicated with a predetermined number of subcarrier signals of an OFDM symbol. The method includes mapping a first data symbol to a first OFDM symbol and mapping a second data symbol to a second OFDM symbol.

The following numbered sections define features and aspects of practicing the invention:

1. A data processing apparatus for interleaving data, comprising:

When two or more code bits of a Low Density Parity Check (LDPC) code are transmitted as one symbol, the plurality of code bits corresponding to the value 1 of any row of the information matrix corresponding to the information bits of the LDPC code are the same. And a substituting unit which performs a substituting process on the LDCP code to replace the code bit of the LDPC code so as not to be coupled to a symbol.

2. A data processing apparatus for interleaving data, comprising:

And, when two or more code bits of the LDPC code are transmitted as one symbol, a replacement part for performing a substitution process on the LDPC code to replace the code bits of the LDPC code,

The parity check matrix of the LDPC code includes an information matrix corresponding to the information bits of the LDPC code, and the information matrix has a cyclic structure;

When the code bits of the LDPC code are written in the column direction to the storage where the code bits of each LDPC code are stored in the row and column direction, and then read from the storage to the row direction to construct a symbol, And the substituting unit performs thermal twist interleaving as the substituting process to change a recording start position at which a code bit of the LDPC code begins to be recorded in each column of the storage in the column direction.

3. The method of clause 2,

The parity check matrix of the LDPC code includes a parity matrix corresponding to the parity bit of the LDPC code, and the parity matrix is a cyclic structure in which a part of the parity matrix except for a specific part of the parity matrix is cyclical through column replacement. The data processing device is converted into a pseudo-cyclic structure so as to have.

4. The method of paragraph 3,

And the parity matrix has a stepped structure and is converted into the pseudo-cyclic structure through column substitution.

5. The method of clause 4,

And the LDPC code is an LDPC code defined in the DVB-S.2 specification.

6. The method of clause 5, wherein

When m code bits of the LDPC code constitute a symbol, the LDPC code has a code length of N bits, and b is a positive integer,

The storage stores mb bits in the row direction and N / mb bits in the column direction;

Code bits of the LDPC code are written to the storage in the column direction, and then read from the storage in the row direction;

And the mb code bits read in the row direction from the storage constitute a b symbol.

7. The method of clause 6, wherein

A parity interleaver for performing parity interleaving on the LDPC code to interleave the parity bits of the LDPC code to different parity bit positions;

And the substituting unit performs the thermal twist interleaving on the parity-interleaved LDPC code.

8. The process of clause 7,

The parity bit number M of the LDPC code is a non-fractional value, P and q are two divisors of the parity bit number M except 1 and M, and the product of the two divisors P and q is equal to the parity bit number M When K is the number of information bits of the LDPC code, x is an integer greater than 0 and less than P, and y is an integer greater than 0 and less than q,

The parity interleaver interleaves a K + qx + y + 1st code bit to a K + Py + x + 1st code bit position among parity bits including K + 1 to K + M th code bits of the LDPC code. , Data processing unit.

9. The method of clause 6, wherein

When the LDPC code is an LDPC code having a code length N of 64800 bits at each of the eleven code rates defined in the DVB-S.2 specification,

The m code bit is 2 code bits and the positive integer b is 1,

The two code bits of the LDPC code are mapped to one of four signal points determined according to a specific modulation method,

The storage includes two columns for storing 2x1 bits in a row direction and stores 64800 / (2x1) bits in a column direction,

The substitution part,

When the address of the first location along the column direction of the reservoir is represented by "0", and the address of each location, besides the first location along the column direction of the reservoir, is represented by an sequentially increasing integer ,

The first recording start position of the two columns of the storage is at the address " 0 "

The second recording start position of the second column of the storage is at address "2"

To determine the data processing apparatus.

10. The method of paragraph 6, wherein

When the LDPC code is an LDPC code having a code length N of 64800 bits at each of the eleven code rates defined in the DVB-S.2 specification,

The m code bit is 2 code bits and the positive integer b is 2,

The two code bits of the LDPC code are mapped to one of four signal points determined according to a specific modulation method,

The storage includes four columns for storing 2x2 bits in a row direction and stores 64800 / (2x2) bits in a column direction,

The substitution part,

When the address of the first location along the column direction of the reservoir is represented by "0", and the address of each location, besides the first location along the column direction of the reservoir, is represented by an sequentially increasing integer ,

The first recording start position of the four columns of the storage is at the address " 0 "

The second recording start position of the four columns of the storage is at the address " 2 "

The third recording start position of the four columns of the storage is at the address "4",

The fourth recording start position of the fourth column of the storage is at the address " 7 "

To determine the data processing apparatus.

11. The method of paragraph 6, wherein

When the LDPC code is an LDPC code having a code length N of 64800 bits at each of the eleven code rates defined in the DVB-S.2 specification,

The m code bit is 4 code bits and the positive integer b is 1,

The 4 code bits of the LDPC code are mapped to one of 16 signal points determined according to a specific modulation method,

The reservoir comprises four columns for storing 4 × 1 bits in a row direction and stores 64800 / (4 × 1) bits in a column direction,

The substitution part,

When the address of the first location along the column direction of the reservoir is represented by "0", and the address of each location, besides the first location along the column direction of the reservoir, is represented by an sequentially increasing integer ,

The first recording start position of the four columns of the storage is at the address " 0 "

The second recording start position of the four columns of the storage is at the address " 2 "

The third recording start position of the four columns of the storage is at the address "4",

The fourth recording start position of the fourth column of the storage is at the address " 7 "

To determine the data processing apparatus.

12. The method of paragraph 6, wherein

When the LDPC code is an LDPC code having a code length N of 64800 bits at each of the eleven code rates defined in the DVB-S.2 specification,

The m code bit is 4 code bits and the positive integer b is 2,

The 4 code bits of the LDPC code are mapped to one of 16 signal points determined according to a specific modulation method,

The storage includes eight columns for storing 4x2 bits in a row direction and stores 64800 / (4x2) bits in a column direction,

The substitution part,

When the address of the first location along the column direction of the reservoir is represented by "0", and the address of each location, besides the first location along the column direction of the reservoir, is represented by an sequentially increasing integer ,

The first recording start position of the eighth column of the storage is at the address " 0 "

The second recording start position of the eighth column of the storage is at the address " 0 "

The third recording start position of the eighth column of the storage is at the address " 2 "

The fourth recording start position of the eighth column of the storage is at the address "4",

The fifth recording start position of the eighth column of the storage is at the address "4",

The sixth recording start position of the eighth column of the storage is at the address " 5 "

The seventh recording start position of the eighth column of the storage is at the address " 7 "

The eighth recording start position of the eighth column of the storage is at the address " 7 "

To determine the data processing apparatus.

13. The method of clause 6, wherein

When the LDPC code is an LDPC code having a code length N of 64800 bits at each of the eleven code rates defined in the DVB-S.2 specification,

The m code bit is 6 code bits and the positive integer b is 1,

The six code bits of the LDPC code are mapped to one of 64 signal points determined according to a specific modulation method,

The reservoir comprises six columns for storing 6 × 1 bits in a row direction and stores 64800 / (6 × 1) bits in a column direction,

The substitution part,

When the address of the first location along the column direction of the reservoir is represented by "0", and the address of each location, besides the first location along the column direction of the reservoir, is represented by an sequentially increasing integer ,

The first recording start position of the six columns of the storage is at the address " 0 "

The second recording start position of the six columns of the storage is at the address " 2 "

The third recording start position of the six columns of the storage is at the address " 5 "

The fourth recording start position of the sixth column of the storage is at the address " 9 "

The fifth recording start position of the sixth column of the storage is at the address " 10 "

The sixth of the sixth row of the storage recording start position is at the address " 13 "

To determine the data processing apparatus.

14. The method of paragraph 6, wherein

When the LDPC code is an LDPC code having a code length N of 64800 bits at each of the eleven code rates defined in the DVB-S.2 specification,

The m code bit is 6 code bits and the positive integer b is 2,

The six code bits of the LDPC code are mapped to one of 64 signal points determined according to a specific modulation method,

The reservoir comprises 12 columns for storing 6x2 bits in a row direction and stores 64800 / (6x2) bits in a column direction,

The substitution part,

When the address of the first location along the column direction of the reservoir is represented by "0", and the address of each location, besides the first location along the column direction of the reservoir, is represented by an sequentially increasing integer ,

The first recording start position of the 12 columns of the storage is at the address " 0 "

The second recording start position of the 12 columns of the storage is at the address " 0 "

The third recording start position of the 12 columns of the storage is at the address " 2 "

The fourth recording start position of the 12 columns of the storage is at the address " 2 "

The fifth recording start position of the 12 columns of the storage is at the address " 3 "

The sixth recording start position of the twelve columns of the storage is at the address " 4 "

The seventh recording start position of the 12 columns of the storage is at the address " 4 "

The eighth recording start position of the 12 columns of the storage is at the address " 5 "

The ninth recording start position of the 12 columns of the storage is at the address " 5 "

The tenth recording start position of the 12 columns of the storage is at the address " 7 "

The eleventh recording start position of the twelve columns of the storage is at the address " 8 "

The recording start position of the second column of the 12 columns of the storage is at the address "9".

To determine the data processing apparatus.

15. The method of clause 6, wherein

When the LDPC code is an LDPC code having a code length N of 64800 bits at each of the eleven code rates defined in the DVB-S.2 specification,

The m code bit is 8 code bits and the positive integer b is 1,

The 8 code bits of the LDPC code are mapped to one of 256 signal points determined according to a specific modulation method,

The storage includes eight columns for storing 8x1 bits in a row direction and stores 64800 / (8x1) bits in a column direction,

The substitution part,

When the address of the first location along the column direction of the reservoir is represented by "0", and the address of each location, besides the first location along the column direction of the reservoir, is represented by an sequentially increasing integer ,

The first recording start position of the eighth column of the storage is at the address " 0 "

The second recording start position of the eighth column of the storage is at the address " 0 "

The third recording start position of the eighth column of the storage is at the address " 2 "

The fourth recording start position of the eighth column of the storage is at the address "4",

The fifth recording start position of the eighth column of the storage is at the address "4",

The sixth recording start position of the eighth column of the storage is at the address " 5 "

The seventh recording start position of the eighth column of the storage is at the address " 7 "

The eighth recording start position of the eighth column of the storage is at the address " 7 "

To determine the data processing apparatus.

16. The method of clause 6, wherein

When the LDPC code is an LDPC code having a code length N of 64800 bits at each of the eleven code rates defined in the DVB-S.2 specification,

The m code bit is 8 code bits and the positive integer b is 2,

The 8 code bits of the LDPC code are mapped to one of 256 signal points determined according to a specific modulation method,

The reservoir comprises 16 columns for storing 8x2 bits in a row direction and stores 64800 / (8x2) bits in a column direction,

The substitution part,

When the address of the first location along the column direction of the reservoir is represented by "0", and the address of each location, besides the first location along the column direction of the reservoir, is represented by an sequentially increasing integer ,

The first recording start position of the 16 columns of the storage is at the address " 0 "

The second recording start position of the 16 columns of the storage is at the address " 2 "

The third recording start position of the 16 columns of the storage is at the address " 2 "

The fourth recording start position of the sixteenth column of the storage is at the address " 2 "

The fifth recording start position of the sixteenth column of the storage is at the address " 2 "

The sixth recording start position of the sixteenth column of the reservoir is at address " 3 "

The seventh recording start position of the sixteenth column of the storage is at the address " 7 "

The eighth recording start position of the sixteenth column of the storage is at the address " 15 "

The ninth recording start position of the sixteenth column of the storage is at the address " 16 "

The tenth recording start position of the sixteenth column of the storage is at the address " 20 "

The eleventh recording start position of the sixteenth column of the storage is at the address " 22 "

The recording start position of the second column of the 16 columns of the storage is at the address " 22 "

The recording start position of the third column of the sixteenth column of the storage is at the address " 27 "

The recording start position of the fourth column of the sixteenth column of the storage is at the address " 27 "

The fifteenth recording start position of the sixteenth column of the storage is at the address " 28 "

The sixteenth recording start position of the sixteenth column of the reservoir is at address "32"

To determine the data processing apparatus.

17. The method of clause 6, wherein

When the LDPC code is an LDPC code having a code length N of 64800 bits at each of the eleven code rates defined in the DVB-S.2 specification,

The m code bit is 10 code bits and the positive integer b is 1,

The 10 code bits of the LDPC code are mapped to one of 1024 signal points determined according to a specific modulation method,

The storage includes 10 columns for storing 10 × 1 bits in a row direction and stores 64800 / (10 × 1) bits in a column direction,

The substitution part,

When the address of the first location along the column direction of the reservoir is represented by "0", and the address of each location, besides the first location along the column direction of the reservoir, is represented by an sequentially increasing integer ,

The first recording start position of the ten columns of the storage is at address " 0 "

The second recording start position of the ten columns of the storage is at the address " 3 "

The third recording start position of the ten columns of the storage is at the address " 6 "

The fourth recording start position of the tenth column of the storage is at the address " 8 "

The fifth recording start position of the tenth column of the storage is at the address " 11 "

The sixth recording start position of the tenth column of the reservoir is at address " 13 "

The seventh recording start position of the tenth column of the storage is at the address " 15 "

The eighth recording start position of the tenth column of the storage is at the address " 17 "

The ninth recording start position of the ten columns of the storage is at the address " 18 "

The tenth recording start position of the tenth column of the storage is at the address "20"

To determine the data processing apparatus.

18. The method of clause 6, wherein

When the LDPC code is an LDPC code having a code length N of 64800 bits at each of the eleven code rates defined in the DVB-S.2 specification,

The m code bit is 10 code bits and the positive integer b is 2,

The 10 code bits of the LDPC code are mapped to one of 1024 signal points determined according to a specific modulation method,

The reservoir comprises 20 columns for storing 10 × 2 bits in a row direction and stores 64800 / (10 × 2) bits in a column direction,

The substitution part,

When the address of the first location along the column direction of the reservoir is represented by "0", and the address of each location, besides the first location along the column direction of the reservoir, is represented by an sequentially increasing integer ,

The first recording start position of the 20 columns of the storage is at the address " 0 "

The second recording start position of the 20 columns of the storage is at the address " 1 "

The third recording start position of the 20 columns of the storage is at the address " 3 "

The fourth recording start position of the twenty-column column of the storage is at the address "4",

The fifth recording start position of the twenty-column column of the storage is at the address " 5 "

The sixth recording start position of the twenty-column of the reservoir is at address " 6 "

The seventh recording start position of the twenty-column of the reservoir is at address " 6 "

The eighth recording start position of the twenty-column of the reservoir is at address " 9 "

The ninth recording start position of the twenty-column column of the storage is at the address "13",

The tenth recording start position of the twenty-column of the reservoir is at address " 14 "

The eleventh recording start position of the twenty-column of the reservoir is at address " 14 "

The recording start position of the second column of the 20 columns of the storage is at the address " 16 "

The third recording start position of the twenty-column column of the storage is at the address " 21 "

The recording start position of the fourth column of the twenty-column of the storage is at the address " 21 ",

The fifteenth recording start position of the twenty-column column of the storage is at the address "23",

The sixteenth recording start position of the twenty-column of the reservoir is at address " 25 "

The seventeenth recording start position of the twenty-column column of the storage is at the address " 25 "

The eighteenth recording start position of the twenty-column of the reservoir is at address " 26 "

The ninth recording start position of the twenty-column column of the storage is at the address " 28 "

The twentieth recording start position of the twenty-column of the reservoir is at address " 30 "

To determine the data processing apparatus.

19. The method of paragraph 6, wherein

When the LDPC code is an LDPC code having a code length N of 64800 bits at each of the eleven code rates defined in the DVB-S.2 specification,

The m code bit is 12 code bits and the positive integer b is 1,

The 12 code bits of the LDPC code are mapped to one of 4096 signal points determined according to a specific modulation method,

The reservoir comprises 12 columns for storing 12 × 1 bits in a row direction and stores 64800 / (12 × 1) bits in a column direction,

The substitution part,

When the address of the first location along the column direction of the reservoir is represented by "0", and the address of each location, besides the first location along the column direction of the reservoir, is represented by an sequentially increasing integer ,

The first recording start position of the 12 columns of the storage is at the address " 0 "

The second recording start position of the 12 columns of the storage is at the address " 0 "

The third recording start position of the 12 columns of the storage is at the address " 2 "

The fourth recording start position of the 12 columns of the storage is at the address " 2 "

The fifth recording start position of the 12 columns of the storage is at the address " 3 "

The sixth recording start position of the twelve columns of the storage is at the address " 4 "

The seventh recording start position of the 12 columns of the storage is at the address " 4 "

The eighth recording start position of the 12 columns of the storage is at the address " 5 "

The ninth recording start position of the 12 columns of the storage is at the address " 5 "

The tenth recording start position of the 12 columns of the storage is at the address " 7 "

The eleventh recording start position of the twelve columns of the storage is at the address " 8 "

The recording start position of the second column of the 12 columns of the storage is at the address "9".

To determine the data processing apparatus.

20. The method of paragraph 6, wherein

When the LDPC code is an LDPC code having a code length N of 64800 bits at each of the eleven code rates defined in the DVB-S.2 specification,

The m code bit is 12 code bits and the positive integer b is 2,

The 12 code bits of the LDPC code are mapped to one of 4096 signal points determined according to a specific modulation method,

The reservoir comprises 24 columns for storing 12 × 2 bits in a row direction and stores 64800 / (12 × 2) bits in a column direction,

The substitution part,

When the address of the first location along the column direction of the reservoir is represented by "0", and the address of each location, besides the first location along the column direction of the reservoir, is represented by an sequentially increasing integer ,

The first recording start position of the 24 columns of the storage is at the address " 0 "

The second recording start position of the 24 columns of the storage is at the address " 5 "

The third recording start position of the 24 columns of the storage is at the address " 8 "

The fourth recording start position of the 24 columns of the storage is at the address " 8 "

The fifth recording start position of the 24 columns of the storage is at the address " 8 "

The sixth recording start position of the 24 columns of the storage is at the address " 8 "

The seventh recording start position of the 24 columns of the storage is at the address " 10 "

The eighth recording start position of the 24 columns of the storage is at the address " 10 "

The ninth recording start position of the 24 columns of the storage is at the address " 10 "

The tenth recording start position of the 24 columns of the storage is at the address " 12 "

The recording start position of the eleventh of the 24 columns of the storage is at the address " 13 "

The recording start position of the second column of the 24 columns of the storage is at the address " 16 "

The recording start position of the third column of the 24 columns of the storage is at the address " 17 "

The recording start position of the fourth column of the 24 columns of the storage is at the address " 19 "

The fifteenth recording start position of the 24 columns of the storage is at the address " 21 "

The sixteenth recording start position of the 24 columns of the storage is at the address " 22 "

The seventeenth recording start position of the 24 columns of the storage is at the address " 23 "

The eighteenth recording start position of the 24 columns of the storage is at the address " 26 "

The ninth recording start position of the 24 columns of the storage is at the address " 37 "

The twentieth recording start position of the 24 columns of the storage is at the address " 39 "

The twenty first recording start position of the 24 columns of the reservoir is at the address " 40 "

The twenty second recording start position of the 24 columns of the reservoir is at the address " 41 "

The twenty-third recording start position of the 24 columns of the reservoir is at the address " 41 "

The twenty-fourth recording start position of the 24 columns of the reservoir is at address "41"

To determine the data processing apparatus.

21. The method of clause 6, wherein

When the LDPC code is an LDPC code having a code length N of 16200 bits at each of the ten code rates defined in the DVB-S.2 specification,

The m code bit is 2 code bits and the positive integer b is 1,

The two code bits of the LDPC code are mapped to one of four signal points determined according to a specific modulation method,

The reservoir includes two columns for storing 2x1 bits in a row direction and stores 16200 / (2x1) bits in a column direction,

The substitution part,

When the address of the first location along the column direction of the reservoir is represented by "0", and the address of each location, besides the first location along the column direction of the reservoir, is represented by an sequentially increasing integer ,

The first recording start position of the two columns of the storage is at the address " 0 "

The second recording start position of the second column of the storage is at the address "0".

To determine the data processing apparatus.

22. The method of paragraph 6, wherein

When the LDPC code is an LDPC code having a code length N of 16200 bits at each of the ten code rates defined in the DVB-S.2 specification,

The m code bit is 2 code bits and the positive integer b is 2,

The two code bits of the LDPC code are mapped to one of four signal points determined according to a specific modulation method,

The reservoir includes four columns for storing 2x2 bits in a row direction and stores 16200 / (2x2) bits in a column direction,

The substitution part,

When the address of the first location along the column direction of the reservoir is represented by "0", and the address of each location, besides the first location along the column direction of the reservoir, is represented by an sequentially increasing integer ,

The first recording start position of the four columns of the storage is at the address " 0 "

The second recording start position of the four columns of the storage is at the address " 2 "

The third recording start position of the fourth column of the storage is at the address " 3 "

The fourth recording start position of the fourth column of the storage is at the address " 3 "

To determine the data processing apparatus.

23. The method of clause 6, wherein

When the LDPC code is an LDPC code having a code length N of 16200 bits at each of the ten code rates defined in the DVB-S.2 specification,

The m code bit is 4 code bits and the positive integer b is 1,

The 4 code bits of the LDPC code are mapped to one of 16 signal points determined according to a specific modulation method,

The reservoir comprises four columns for storing 4 × 1 bits in a row direction and stores 16200 / (4 × 1) bits in a column direction,

The substitution part,

When the address of the first location along the column direction of the reservoir is represented by "0", and the address of each location, besides the first location along the column direction of the reservoir, is represented by an sequentially increasing integer ,

The first recording start position of the four columns of the storage is at the address " 0 "

The second recording start position of the four columns of the storage is at the address " 2 "

The third recording start position of the fourth column of the storage is at the address " 3 "

The fourth recording start position of the fourth column of the storage is at the address " 3 "

To determine the data processing apparatus.

24. The method of paragraph 6, wherein

When the LDPC code is an LDPC code having a code length N of 16200 bits at each of the ten code rates defined in the DVB-S.2 specification,

The m code bit is 4 code bits and the positive integer b is 2,

The 4 code bits of the LDPC code are mapped to one of 16 signal points determined according to a specific modulation method,

The reservoir comprises eight columns for storing 4x2 bits in a row direction and stores 16200 / (4x2) bits in a column direction,

The substitution part,

When the address of the first location along the column direction of the reservoir is represented by "0", and the address of each location, besides the first location along the column direction of the reservoir, is represented by an sequentially increasing integer ,

The first recording start position of the eighth column of the storage is at the address " 0 "

The second recording start position of the eighth column of the storage is at the address " 0 "

The third recording start position of the eighth column of the storage is at the address " 0 "

The fourth recording start position of the eighth column of the storage is at the address " 1 "

The fifth recording start position of the eighth column of the storage is at the address " 7 "

The sixth recording start position of the eighth column of the storage is at the address " 20 "

The seventh recording start position of the eighth column of the storage is at the address "20",

The eighth recording start position of the eighth column of the storage is at the address " 21 "

To determine the data processing apparatus.

25. The method of clause 6, wherein

When the LDPC code is an LDPC code having a code length N of 16200 bits at each of the ten code rates defined in the DVB-S.2 specification,

The m code bit is 6 code bits and the positive integer b is 1,

The six code bits of the LDPC code are mapped to one of 64 signal points determined according to a specific modulation method,

The reservoir comprises six columns for storing 6 × 1 bits in a row direction and stores 16200 / (6 × 1) bits in a column direction,

The substitution part,

When the address of the first location along the column direction of the reservoir is represented by "0", and the address of each location, besides the first location along the column direction of the reservoir, is represented by an sequentially increasing integer ,

The first recording start position of the six columns of the storage is at the address " 0 "

The second recording start position of the six columns of the storage is at the address " 0 "

The third recording start position of the six columns of the storage is at the address " 2 "

The fourth recording start position of the sixth column of the storage is at the address " 3 "

The fifth recording start position of the sixth column of the storage is at the address " 7 "

The sixth of the sixth row of the storage recording start position is at the address " 7 "

To determine the data processing apparatus.

26. The method of paragraph 6, wherein

When the LDPC code is an LDPC code having a code length N of 16200 bits at each of the 10 code rates defined in the DVB-S.2 specification,

The m code bit is 6 code bits and the positive integer b is 2,

The six code bits of the LDPC code are mapped to one of 64 signal points determined according to a specific modulation method,

The reservoir comprises 12 columns for storing 6 × 2 bits in a row direction and stores 16200 / (6 × 2) bits in a column direction,

The substitution part,

When the address of the first location along the column direction of the reservoir is represented by "0", and the address of each location, besides the first location along the column direction of the reservoir, is represented by an sequentially increasing integer ,

The first recording start position of the 12 columns of the storage is at the address " 0 "

The second recording start position of the 12 columns of the storage is at the address " 0 "

The third recording start position of the 12 columns of the storage is at the address " 0 "

The fourth recording start position of the 12 columns of the storage is at the address " 2 "

The fifth recording start position of the 12 columns of the storage is at the address " 2 "

The sixth recording start position of the twelve columns of the reservoir is at address " 2 "

The seventh recording start position of the 12 columns of the storage is at the address " 3 "

The eighth recording start position of the 12 columns of the storage is at the address " 3 "

The ninth recording start position of the twelve columns of the storage is at the address " 3 "

The tenth recording start position of the 12 columns of the storage is at the address " 6 "

The eleventh recording start position of the twelve columns of the storage is at the address " 7 "

The recording start position of the second column of the 12 columns of the storage is at the address "7"

To determine the data processing apparatus.

27. The method of clause 6, wherein

When the LDPC code is an LDPC code having a code length N of 16200 bits at each of the 10 code rates defined in the DVB-S.2 specification,

The m code bit is 8 code bits and the positive integer b is 1,

The 8 code bits of the LDPC code are mapped to one of 256 signal points determined according to a specific modulation method,

The reservoir comprises eight columns for storing 8 × 1 bits in a row direction and stores 16200 / (8 × 1) bits in a column direction,

The substitution part,

When the address of the first location along the column direction of the reservoir is represented by "0", and the address of each location, besides the first location along the column direction of the reservoir, is represented by an sequentially increasing integer ,

The first recording start position of the eighth column of the storage is at the address " 0 "

The second recording start position of the eighth column of the storage is at the address " 0 "

The third recording start position of the eighth column of the storage is at the address " 0 "

The fourth recording start position of the eighth column of the storage is at the address " 1 "

The fifth recording start position of the eighth column of the storage is at the address " 7 "

The sixth recording start position of the eighth column of the storage is at the address " 20 "

The seventh recording start position of the eighth column of the storage is at the address "20",

The eighth recording start position of the eighth column of the storage is at the address " 21 "

To determine the data processing apparatus.

28. The method of paragraph 6, wherein

When the LDPC code is an LDPC code having a code length N of 16200 bits at each of the 10 code rates defined in the DVB-S.2 specification,

The m code bit is 10 code bits and the positive integer b is 1,

The 10 code bits of the LDPC code are mapped to one of 1024 signal points determined according to a specific modulation method,

The reservoir comprises 10 columns for storing 10 × 1 bits in a row direction and stores 16200 / (10 × 1) bits in a column direction,

The substitution part,

When the address of the first location along the column direction of the reservoir is represented by "0", and the address of each location, besides the first location along the column direction of the reservoir, is represented by an sequentially increasing integer ,

The first recording start position of the ten columns of the storage is at address " 0 "

The second recording start position of the ten columns of the storage is at the address " 1 "

The third recording start position of the ten columns of the storage is at the address " 2 "

The fourth recording start position of the tenth column of the storage is at the address " 2 "

The fifth recording start position of the tenth column of the storage is at the address " 3 "

The sixth recording start position of the tenth column of the reservoir is at address " 3 "

The seventh recording start position of the ten columns of the storage is at the address " 4 "

The eighth recording start position of the tenth column of the storage is at the address " 4 "

The ninth recording start position of the ten columns of the storage is at the address " 5 "

The tenth recording start position of the tenth column of the storage is at the address "7"

To determine the data processing apparatus.

29. The method of clause 6, wherein

When the LDPC code is an LDPC code having a code length N of 16200 bits at each of the 10 code rates defined in the DVB-S.2 specification,

The m code bit is 10 code bits and the positive integer b is 2,

The 10 code bits of the LDPC code are mapped to one of 1024 signal points determined according to a specific modulation method,

The reservoir comprises 20 columns for storing 10 × 2 bits in a row direction and stores 16200 / (20 × 1) bits in a column direction,

The substitution part,

When the address of the first location along the column direction of the reservoir is represented by "0", and the address of each location, besides the first location along the column direction of the reservoir, is represented by an sequentially increasing integer ,

The first recording start position of the 20 columns of the storage is at the address " 0 "

The second recording start position of the 20 columns of the storage is at the address " 0 "

The third recording start position of the 20 columns of the storage is at the address " 0 "

The fourth recording start position of the 20 columns of the storage is at the address " 2 "

The fifth recording start position of the twenty-column column of the storage is at address " 2 "

The sixth recording start position of the twenty-column of the reservoir is at address " 2 "

The seventh recording start position of the twenty-column of the reservoir is at address " 2 "

The eighth recording start position of the twenty-column of the reservoir is at address " 2 "

The ninth recording start position of the twenty-column column of the storage is at address " 5 "

The tenth recording start position of the twenty-column of the reservoir is at address " 5 "

The eleventh recording start position of the twenty-column of the reservoir is at address " 5 "

The recording start position of the second column of the 20 columns of the storage is at the address " 5 "

The third recording start position of the twenty-column column of the storage is at the address " 5 "

The recording start position of the fourth column of the twenty-column of the reservoir is at address " 7 ",

The fifteenth recording start position of the twenty-column of the reservoir is at address " 7 "

The sixteenth recording start position of the twenty-column column of the storage is at the address "7",

The seventeenth recording start position of the twenty-column column of the storage is at the address "7",

The eighteenth recording start position of the twenty-column column of the storage is at the address " 8 "

The ninth recording start position of the twenty-column column of the storage is at the address " 8 "

The twentieth recording start position of the twenty-column of the reservoir is at address " 10 "

To determine the data processing apparatus.

30. The method of paragraph 6, wherein

When the LDPC code is an LDPC code having a code length N of 16200 bits at each of the 10 code rates defined in the DVB-S.2 specification,

The m code bit is 12 code bits and the positive integer b is 1,

The 12 code bits of the LDPC code are mapped to one of 4096 signal points determined according to a specific modulation method,

The reservoir comprises 12 columns for storing 12 × 1 bits in a row direction and stores 16200 / (12 × 1) bits in a column direction,

The substitution part,

When the address of the first location along the column direction of the reservoir is represented by "0", and the address of each location, besides the first location along the column direction of the reservoir, is represented by an sequentially increasing integer ,

The first recording start position of the 12 columns of the storage is at the address " 0 "

The second recording start position of the 12 columns of the storage is at the address " 0 "

The third recording start position of the 12 columns of the storage is at the address " 0 "

The fourth recording start position of the 12 columns of the storage is at the address " 2 "

The fifth recording start position of the 12 columns of the storage is at the address " 2 "

The sixth recording start position of the twelve columns of the reservoir is at address " 2 "

The seventh recording start position of the 12 columns of the storage is at the address " 3 "

The eighth recording start position of the 12 columns of the storage is at the address " 3 "

The ninth recording start position of the twelve columns of the storage is at the address " 3 "

The tenth recording start position of the 12 columns of the storage is at the address " 6 "

The eleventh recording start position of the twelve columns of the storage is at the address " 7 "

The recording start position of the second column of the 12 columns of the storage is at the address "7"

To determine the data processing apparatus.

31. The method of clause 6, wherein

When the LDPC code is an LDPC code having a code length N of 16200 bits at each of the 10 code rates defined in the DVB-S.2 specification,

The m code bit is 12 code bits and the positive integer b is 2,

The 12 code bits of the LDPC code are mapped to one of 4096 signal points determined according to a specific modulation method,

The reservoir comprises 24 columns for storing 12 × 2 bits in a row direction and stores 16200 / (12 × 2) bits in a column direction,

The substitution part,

When the address of the first location along the column direction of the reservoir is represented by "0", and the address of each location, besides the first location along the column direction of the reservoir, is represented by an sequentially increasing integer ,

The first recording start position of the 24 columns of the storage is at the address " 0 "

The second recording start position of the 24 columns of the storage is at the address " 0 "

The third recording start position of the 24 columns of the storage is at the address " 0 "

The fourth recording start position of the 24 columns of the storage is at the address " 0 "

The fifth recording start position of the 24 columns of the storage is at the address " 0 "

The sixth recording start position of the 24 columns of the storage is at the address " 0 "

The seventh recording start position of the 24 columns of the storage is at the address " 0 "

The eighth recording start position of the 24 columns of the storage is at the address " 1 "

The ninth recording start position of the 24 columns of the storage is at the address " 1 "

The tenth recording start position of the 24 columns of the storage is at the address " 1 "

The recording start position of the eleventh of the 24 columns of the storage is at the address " 2 "

The recording start position of the second column of the 24 columns of the storage is at the address " 2 "

The recording start position of the third column of the 24 columns of the storage is at the address " 2 "

The recording start position of the fourth column of the 24 columns of the storage is at the address " 3 "

The fifteenth recording start position of the 24 columns of the storage is at the address " 7 "

The sixteenth recording start position of the 24 columns of the storage is at the address " 9 "

The seventeenth recording start position of the 24 columns of the storage is at the address " 9 "

The eighteenth recording start position of the 24 columns of the storage is at the address " 9 "

The ninth recording start position of the 24 columns of the storage is at the address " 10 "

The twentieth recording start position of the 24 columns of the storage is at the address " 10 "

The twenty first recording start position of the 24 columns of the reservoir is at the address " 10 "

The twenty second recording start position of the 24 columns of the reservoir is at the address " 10 "

The twenty-third recording start position of the 24 columns of the reservoir is at the address " 10 "

Twenty-fourth recording start position of the 24 columns of the reservoir is at address " 11 "

To determine the data processing apparatus.

32. The method of clause 5,

The LDPC code is transmitted through Quadrature Phase Shift Keying (QPSK), 16 Quadrature Amplitude Modulation (QAM), 64QAM, 256QAM, 1024QAM, or 4096QAM modulation.

33. The method of paragraph 2, wherein

The LDPC code is a QC (Quasi-Cyclic) -LDPC code,

When the code bits of the LDPC code are written in the column direction to the storage where the code bits of each LDPC code are stored in the row and column direction, and then read from the storage to the row direction to construct a symbol, And the substituting unit performs thermal twist interleaving as the substituting process to change a recording start position at which a code bit of the LDPC code begins to be recorded in each column of the storage in the column direction.

34. The data processing apparatus of claim 7, wherein the parity interleaver and the replacement portion are integrally formed.

35. A data processing method for a data processing apparatus for interleaving data, wherein the method causes the data processing apparatus to correspond to information bits of the LDPC code when two or more code bits of an LDPC code are transmitted as one symbol. And performing a substitution process on the LDCP code to replace the code bits of the LDPC code such that a plurality of code bits corresponding to the value 1 of any row of the information matrix are not combined into the same symbol. Way.

36. A data processing apparatus for receiving an interleaved and transmitted LDPC code such that two or more code bits of an LDPC code constitute one symbol, the apparatus comprising:

Substituting the LDCP code to replace the code bits of the LDPC code so that a plurality of code bits corresponding to the value 1 of any row of the information matrix corresponding to the information bits of the LDPC code is not combined in the same symbol An inverse substitution portion for performing an inverse substitution process, which is an inversion of the substitution process, on the obtained LDPC code,

And an LDPC decoder for performing LDPC decoding on the LDPC code on which the inverse substitution process has been performed.

37. The method of clause 36,

The inverse replacement unit may include a parity matrix corresponding to a parity bit of the LDPC code, wherein the parity matrix has a stepwise structure such that the parity bits of the LDPC code are interleaved with different parity bit positions. After performing inverse permutation processing on the LDPC code obtained by performing parity interleaving on the LDPC code obtained by performing LDPC encoding according to the matrix, a value 1 of any row of the information matrix corresponding to the information bit of the LDPC code is performed. Perform a substitution process on the LDCP code to replace the code bits of the LDPC code such that a plurality of code bits of a corresponding LDPC code are not combined in the same symbol,

The LDPC decoder uses the transformed parity check matrix obtained by performing at least column substitution corresponding to the parity interleaving for the parity check matrix, wherein the inverse substitution process has been performed and parity deinterleaving corresponding to the parity interleaving. Performs LDPC decoding of the LDPC code that has not been performed.

38. A data processing method for a data processing apparatus for receiving an interleaved and transmitted LDPC code such that two or more code bits of an LDPC code constitute one symbol, the method comprising:

Substituting the LDCP code for substituting code bits of the LDPC code such that a plurality of code bits of the LDPC code corresponding to the value 1 of any row of the information matrix corresponding to the information bits of the LDPC code are not combined into the same symbol. Performing, by the data processing apparatus, an inverse substitution process that is an inversion of the substitution process to the LDPC code obtained by performing the process;

And performing LDPC decoding on the LDPC code on which the reverse substitution process has been performed.

1 is a schematic block diagram of a coded OFDM transmitter, for example, in which the DVB-T2 standard may be used.

2 illustrates an exemplary parity check matrix H of LDPC codes.

3 is a flowchart illustrating a procedure for decoding an LDPC code.

4 illustrates an exemplary parity check matrix of an LDPC code.

FIG. 5 shows a Tanner graph of the parity check matrix. FIG.

6 illustrates a variable node.

7 illustrates an inspection node.

8 is a schematic block diagram illustrating an exemplary configuration of a transmitter.

9 illustrates a parity check matrix.

10 illustrates a parity matrix.

11A and 11B show a parity check matrix of an LDPC code and column weights defined in the DVB-S.2 specification.

12A and 12B show the configuration of signal points of 16QAM.

Fig. 13 is a diagram showing the configuration of signal points of 64QAM.

Fig. 14 is a diagram showing the configuration of signal points of 64QAM.

15 is a diagram illustrating a configuration of a signal point of 64QAM.

16A to 16D show the operation of the demultiplexer 25. FIG.

17A and 17B illustrate the operation of the demultiplexer 25.

18 shows a Tanner graph for decoding of LDPC codes.

19A and 19B show a Tanner graph corresponding to parity matrix H _T and parity matrix H _T having a stepped structure.

20 illustrates the parity matrix H _T of the parity check matrix H corresponding to the LDPC code after parity interleaving is performed in the LDPC code.

21A and 21B show the transformed parity check matrix.

FIG. 22 is a diagram showing the operation of the thermal twist interleaver 24. FIG.

Fig. 23 is a diagram showing the number of columns of the memory 31 required for column twist interleaving and the address of the write start position.

Fig. 24 is a diagram showing the number of columns of the memory 31 required for column twist interleaving and the address of the write start position.

25 is a flowchart showing a transmission procedure.

26A and 26B show models of communication paths used in the simulation.

FIG. 27 is a diagram showing a relationship between an error rate obtained from a simulation and the Doppler frequency f _d; FIG.

FIG. 28 is a diagram showing a relationship between an error rate obtained from a simulation and the Doppler frequency f _d; FIG.

29 is a schematic block diagram of a coded OFDM receiver in which the DVB-T2 standard may be used, for example.

30 is a flowchart showing a receiving procedure.

FIG. 31 illustrates an exemplary parity check matrix of an LDPC code. FIG.

FIG. 32 is a diagram showing a matrix (transformed parity check matrix) obtained by performing row substitution and column substitution in a parity check matrix. FIG.

FIG. 33 is a diagram showing a transformed parity check matrix divided into units of a 5x5 matrix. FIG.

34 is a block diagram showing an exemplary configuration of a decoding apparatus for simultaneously performing P-node calculations.

35 shows an exemplary configuration of an LDPC decoder 56. FIG.

36 is a block diagram showing an exemplary configuration of a computer embodiment to which the present invention is applied.

FIG. 37 is a schematic block diagram of portions of the transmitter shown in FIG. 1 in which a symbol mapper and a frame builder illustrate the operation of an interleaver; FIG.

FIG. 38 is a schematic block diagram of the symbol interleaver shown in FIG. 37; FIG.

FIG. 39 is a schematic block diagram of a corresponding symbol deinterleaver of the interleaver memory and receiver shown in FIG. 38;

40 is a schematic block diagram of the address generator shown in FIG. 38 for a 32k mode.

FIG. 41A is a diagram showing the results of an interleaver using the address generator shown in FIG. 40 for even symbols, FIG. 41B is a diagram showing the design simulation results for odd symbols, and FIG. 41C is for an even number. Fig. 41D shows a comparison result for an odd symbol using an address generator using different substitution codes.

FIG. 42 is a schematic block diagram of the symbol deinterleaver shown in FIG. 29; FIG.

FIG. 43A is a diagram showing the results of an interleaver using the address generator shown in FIG. 40 for an even OFDM symbol, and FIG. 43B is a diagram showing the results for an odd OFDM symbol. 43A and 43B are graphs showing the distance at the interleaver output of adjacent subcarriers at the interleaver input.

FIG. 44 is a schematic block diagram of the symbol interleaver shown in FIG. 38, illustrating an operation mode in which interleaving is performed only in accordance with an odd interleaving mode; FIG.

FIG. 45 is a schematic block diagram of the symbol deinterleaver shown in FIG. 42, showing an operation mode in which interleaving is performed only in accordance with an odd interleaving mode. FIG.

<Explanation of symbols for the main parts of the drawings>

1: source coding and multiplexing

2: video coder

4: audio coder

6: data coder

20: Adaptation and Energy Diffusion

21: LDPC BCH Encoder

22: bit interleaver

26: bit array mapper

30: time interleaver

32: Frame Builder

33: symbol interleaver

36: pilot + embedded signaling

37: OFDM Symbol Builder

38: OFDM modulator

40: Insert guard gap

44: shear

Claims (18)

A data processing apparatus for communicating data bits via a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol, Obtained by LDPC encoding the data bits according to a parity check matrix of an LDPC code that includes a parity matrix corresponding to the parity bits of the LDPC code such that the parity bits of the LDPC encoded data bits are interleaved to different parity bit positions. A parity interleaver operable to perform parity interleaving on the LDPC encoded data bits, wherein the parity matrix has a stepwise structure; A mapping unit for mapping parity interleaved bits into data symbols corresponding to modulation symbols of a modulation scheme of OFDM subcarrier signals; Read-in a predetermined number of data symbols for mapping to OFDM subcarrier signals into symbol interleaver memory, and read out data symbols for OFDM subcarrier signals from interleaver memory to achieve mapping. A symbol interleaver configured to operate, wherein the read is in a different order than the input, the order is determined from an address set, and the data symbols are interleaved in a subcarrier signal of an OFDM symbol; An address generator operable to generate an address set, the address being generated for each of the input symbols to represent one of the subcarrier signals to which the data symbol is mapped; The address generator, A linear feedback shift register comprising a predetermined number of register stages and operable to generate a pseudo-random bit sequence in accordance with a generator polynomial; A substitution circuit operable to receive the contents of the shift register stages and permute the bits present in the register stages according to a substitution code to form an address of one of the OFDM subcarriers; A control unit operable in combination with the address checking circuit to regenerate the address if the generated address exceeds a predetermined maximum valid address, The selected maximum valid address is approximately 32000, The linear fitback shift register is a generated polynomial for the linear feedback shift register.

14 register stages with the substitution code, with additional bits, R ' _i bit position 13 12 11 10 9 8 7 6 5 4 3 2 One 0 R _i bit position 6 5 0 10 8 One 11 12 2 9 4 3 13 7 According to the nth register stage

A 15-bit address for the i th data symbol from the bit present in the

Forming, Data processing unit. The method of claim 1, The parity bit number M of the LDPC code is a non-prime value, P and q are two divisors of the parity bit number M except 1 and M, and the product of the two divisors P and q is the parity Is the same as the number of bits M, K is the number of information bits of the LDPC code, x is an integer greater than 0 and less than P, and y is an integer greater than 0 and less than q, The parity interleaver interleaves a K + qx + y + 1st code bit to a K + Py + x + 1st code bit position among parity bits including K + 1 to K + M th code bits of the LDPC code. Data processing unit. The method of claim 1, When two or more code bits of an LDPC are transmitted as one of the data symbols, the parity interleaving such that a plurality of code bits corresponding to value 1 of any row of the parity check matrix are not combined into the same data symbol. And a permuter for performing a substitution process on the parity interleaved LDCP encoded data bits to replace the LDPC encoded data bits. The method of claim 3, The parity check matrix of the LDPC code includes an information matrix corresponding to the information bits of the LDPC code, the information matrix has a cyclic structure, and the LDPC encoded data bits are written to the bit interleaver memory in the column direction. And, when the symbols are read from the bit interleaver memory in the row direction to construct a symbol, wherein encoding bits of each LDPC code are stored in the row direction and the column direction, and the substituting unit is configured to determine that the encoding bits of the LDPC code A data processing apparatus that performs column twist interleaving as a substitution process to change the recording start position where recording starts to be recorded in the column direction of the column. The method of claim 4, wherein Through column substitution corresponding to parity interleaving, the parity matrix of the parity check matrix of the LDPC code is converted into a pseudo-cyclic structure, so that a part of the parity matrix except for a specific part of the parity matrix is converted into a cyclic structure. Having a data processing device. The method of claim 5, When m bits of the LDPC encoded data constitute one symbol, the LDPC code has a code length of N bits, and b is a positive integer, The bit interleaver memory stores mb bits in the row direction and N / mb bits in the column direction; The LDPC encoded data bits are written in the column direction to the bit interleaver memory and then read from the bit interleaver memory in the row direction; And mb encoded bits read in the row direction from the bit interleaver memory constitute b symbols. The method of claim 1, The OFDM symbol comprises a pilot subcarrier configured to carry known symbols, and the predetermined maximum valid address depends on the number of pilot subcarrier symbols present in the OFDM symbol. A transmitter for transmitting data bits using a predetermined number of subcarriers of an OFDM symbol, An LDPC encoder configured to perform LDPC encoding of data bits according to a parity check matrix of an LDPC code comprising a parity matrix corresponding to a parity bit of an LDPC code, wherein the parity matrix has a stepped structure; A parity interleaver operable to perform parity interleaving on LDPC encoded data bits such that parity bits of the LDPC code are interleaved to different parity bit positions; A mapping unit operable to map the parity interleaved data bits to data symbols corresponding to modulation symbols of the modulation scheme of the OFDM subcarrier signals; A symbol interleaver configured to input a predetermined number of data symbols for mapping to OFDM subcarrier signals into a symbol interleaver memory and to read data symbols for an OFDM subcarrier from an interleaver memory to achieve mapping; Is a different order from, wherein the order is determined from a set of addresses and the data symbols are interleaved in a subcarrier signal of an OFDM symbol; An address generator operable to generate an address set, the address being generated for each of the data symbols to represent one of the subcarrier signals to which the data symbol is mapped; The address generator, A linear feedback shift register comprising a predetermined number of register stages and operable to generate a pseudo-random bit sequence in accordance with a generation polynomial; A substitution circuit operable to receive the contents of the shift register stages and replace the bits present in the register stages according to a substitution code to form an address of one of the OFDM subcarriers; A control unit operable in combination with the address checking circuit to regenerate the address if the generated address exceeds a predetermined maximum valid address, The selected maximum valid address is approximately 32000, The linear fitback shift register is a generated polynomial for the linear feedback shift register.

14 register stages with the substitution code, with additional bits, R ' _i bit position 13 12 11 10 9 8 7 6 5 4 3 2 One 0 R _i bit position 6 5 0 10 8 One 11 12 2 9 4 3 13 7 According to the nth register stage

A 15-bit address for the i th data symbol from the bit present in the

Transmitter to form. The method of claim 8, The transmitter is a digital video broadcasting-terrestrial (DVB-T), digital video broadcasting-handheld (DVB-H), digital video broadcasting-terrestrial2 (DVB-T2) standard, or digital video broadcasting cable2 (DVB-C2) standard. Transmitter configured to transmit data according to the DVB standard (Digital Video Broadcasting standard). A method of communicating data bits over a predetermined number of subcarrier signals of an OFDM symbol, the method comprising: Parity the LDPC encoded data bits obtained by LDPC encoding the data bits according to a parity check matrix of the LDPC code including a parity matrix corresponding to the parity bits of the LDPC code so that the parity bits of the LDPC code are interleaved to different parity bit positions. Interleaving, wherein the parity matrix has a stepped structure; Mapping the parity interleaved bits into data symbols corresponding to modulation symbols of the modulation scheme of OFDM subcarrier signals; Inputting a predetermined number of data symbols into a symbol interleaver memory for mapping to OFDM subcarrier signals; Reading data symbols for OFDM subcarriers from interleaver memory to achieve mapping, wherein the reading is in a different order than the input, the order is determined from an address set, and the data symbols are interleaved in a subcarrier signal -Wow, Generating an address set, the address being generated for each of the input symbols to represent one of the subcarrier signals to which the data symbol is mapped; Generating the address set, Using a linear feedback shift register comprising a predetermined number of register stages to generate a pseudorandom bit sequence in accordance with a generation polynomial; Using a substitution circuit operable to receive content of the shift register stages and replace the bits present in the register stages to form an address; Regenerating the address if the generated address exceeds a predetermined maximum valid address; The selected maximum valid address is approximately 32000, The linear fitback shift register is a generated polynomial for the linear feedback shift register.

With 14 register stages, and the substitution code, with additional bits, R ' _i bit position 13 12 11 10 9 8 7 6 5 4 3 2 One 0 R _i bit position 6 5 0 10 8 One 11 12 2 9 4 3 13 7 According to the nth register stage

A 15-bit address for the i th data symbol from the bit present in the

How to form. The method of claim 10, The parity bit number M of the LDPC code is a non-fractional value, P and q are two divisors of the parity bit number M except 1 and M, and the product of the two divisors P and q is equal to the parity bit number M When K is the number of information bits of the LDPC code, x is an integer greater than or equal to 0 and less than P, and y is an integer greater than or equal to 0 and less than q, In the parity interleaving step, the K + qx + y + 1st code bits of the parity bits including the K + 1st to K + Mth code bits of the LDPC code are set to the K + Py + x + 1st code bit positions. Interleaving. The method of claim 11, When two or more encoding bits of LDPC encoded data bits are transmitted as one of the data symbols, a plurality of encoded data bits corresponding to value 1 of any row of the parity check matrix are not combined into the same data symbol. Substituting encoding bits of the parity interleaved LDPC encoded data bits such that the encoded bits of the parity interleaved LDPC encoded data bits are not substituted. The method of claim 12, The parity check matrix of the LDPC code includes an information matrix corresponding to the information bits of the LDPC code, and the information matrix has a cyclic structure; When the encoded data bits of the LDPC code are written to the bit interleaver memory in the column direction, and read from the bit interleaver memory in the row direction to construct a symbol-the encoding bits of each LDPC code are stored in the row direction and the column direction. And the substituting step includes thermal twist interleaving as a substitution process to change a write start position at which the encoded data bits of the LDPC code begin to be written in the column direction of each column of the bit interleaver memory. The method of claim 13, In the column twist interleaving step, the parity matrix of the parity check matrix of the LDPC code is a pseudo-cyclic structure such that a part of the parity matrix except a specific part of the parity matrix has a cyclic structure. Replacing with a method. The method of claim 14, When m encoded data bits of the LDPC code constitute one symbol, the LDPC code has a code length of N bits, and b is a positive integer, Storing in the bit interleaver memory includes storing mb bits in the row direction and N / mb bits in the column direction; Writing the LDPC encoded data bits to the bit interleaver memory in the column direction; Reading in the row direction from the bit interleaver memory; Reading mb encoded bits from the bit interleaver memory in the row direction to construct b symbols. The method of claim 10, The OFDM symbol comprises a pilot subcarrier configured to carry known symbols, wherein the predetermined maximum valid address depends on the number of pilot subcarrier symbols present in the OFDM symbol. A method of transmitting data bits on a predetermined number of subcarrier signals of an OFDM symbol, the method comprising: LDPC encoding the data bits according to a parity check matrix of an LDPC code including a parity matrix corresponding to a parity bit of an LDPC code, wherein the parity matrix has a stepped structure; Parity interleaving the LDPC encoded data bits such that the parity bits of the LDPC code are interleaved to different parity bit positions; Mapping parity interleaved encoding bits to data symbols corresponding to modulation symbols of a modulation scheme of OFDM subcarrier signals; Inputting a predetermined number of data symbols into a symbol interleaver memory for mapping to OFDM subcarrier signals; Reading data symbols for OFDM subcarrier signals from a symbol interleaver memory to achieve mapping, wherein the read is in a different order than the input, the order is determined from an address set, and the data symbols are interleaved in the subcarrier signal Wow, Generating an address set, the address being generated for each of the input symbols to represent one of the subcarrier signals to which the data symbol is mapped; Generating the address set, Using a linear feedback shift register comprising a predetermined number of register stages to generate a pseudorandom bit sequence in accordance with a generation polynomial; Using a substitution circuit operable to receive content of the shift register stages and replace the bits present in the register stages to form an address; Regenerating the address if the generated address exceeds a predetermined maximum valid address; The selected maximum valid address is approximately 32000, The linear fitback shift register is a generated polynomial for the linear feedback shift register.

With 14 register stages, and the substitution code, with additional bits, R ' _i bit position 13 12 11 10 9 8 7 6 5 4 3 2 One 0 R _i bit position 6 5 0 10 8 One 11 12 2 9 4 3 13 7 According to the nth register stage

A 15-bit address for the i th data symbol from the bit present in the

How to form. The method of claim 17, Transmitting a data symbol of an OFDM symbol modulated according to a DVB standard such as the DVB-T, DVB-H, DVB-T2 standard, or DVB-C2 standard.

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