KR20090031103A - Semiconductor device and method for fabricating metal gate of the semiconductor device - Google Patents

Semiconductor device and method for fabricating metal gate of the semiconductor device Download PDF

Info

Publication number
KR20090031103A
KR20090031103A KR1020070096945A KR20070096945A KR20090031103A KR 20090031103 A KR20090031103 A KR 20090031103A KR 1020070096945 A KR1020070096945 A KR 1020070096945A KR 20070096945 A KR20070096945 A KR 20070096945A KR 20090031103 A KR20090031103 A KR 20090031103A
Authority
KR
South Korea
Prior art keywords
layer
forming
gate
well region
mon
Prior art date
Application number
KR1020070096945A
Other languages
Korean (ko)
Inventor
노진서
박성호
전중석
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020070096945A priority Critical patent/KR20090031103A/en
Publication of KR20090031103A publication Critical patent/KR20090031103A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2

Abstract

A semiconductor device and a method for forming a metal gate of the semiconductor device are disclosed. A semiconductor device according to one type of the present invention includes a semiconductor substrate having a P well region and an N well region formed therein; A gate insulating film formed on the semiconductor substrate; And an NMOS metal gate formed of metal nitride including Mo and Al on the gate insulating film of the P well region, and a PMOS metal gate formed of MoN on the gate insulating film of the N well region.

Description

Semiconductor device and method for fabricating metal gate of the semiconductor device

The present invention relates to a semiconductor device and a method of forming a metal gate of the semiconductor device, and more particularly, to a CMOS device having a MoN-based metal gate and a method of forming a metal gate of the CMOS device.

The logic circuit is composed of logic gates such as AND, OR, NAND, NOR, and XOR gate, as well as an inverter that performs a NOT function depending on the function. Logic gates can be configured in various ways such as Resistor Transistor Logic (RTL), Transistor Transistor Logic (TTL), and Emulator-Coupled Logic (ECL). Complementary Metal Oxide Semiconductor (CMOS) is the most commonly used. A CMOS device is a semiconductor device in which a p-channel metal oxide semiconductor (PMOS) transistor and an n-channel metal oxide semiconductor (NMOS) transistor are formed together in one semiconductor device to perform complementary operations. .

In the conventional case, a gate of a CMOS device is fabricated by forming doped polysilicon in the same form as each channel on a gate insulating film made of, for example, a silicon oxide film (SiO 2 ). For example, the gate of the PMOS transistor is formed of polysilicon doped with P-type, and the gate of the NMOS transistor is formed of polysilicon doped with N-type. However, as the thickness of the thin films in the semiconductor device becomes thinner due to the integration of the semiconductor device, the thickness of the existing SiO 2 thin film used as the gate insulating film decreases and the power consumption exceeds the reference value due to the increase of leakage current due to tunneling. Occurred. In order to improve such a problem, attention has been paid to a high-k oxide film capable of realizing a thicker gate insulating film having the same equivalent oxide film thickness but not physically tunneling. As a result, high dielectric materials such as HfO 2 , Al 2 O 3, etc. have replaced SiO 2 .

However, as the high dielectric material is used as the gate insulating film, the doped polysilicon gate has two fatal disadvantages in spite of process ease and accumulated know-how, and thus it is difficult to use at an ultrafine scale of 50 nm or less. The first reason is gate depletion, which is almost depleted of charge at the bottom of the gate due to the limit of doping concentration (~ 1x10 21 / cm 3 ) and lower dopant concentration at the gate dielectric interface. The area is formed. This gate depletion region reduces oxide capacitance by increasing the oxide thickness in the inversion state, thereby reducing the amount of driving current. . The second is dopant penetraion, which is particularly problematic when dopants penetrate downward during PMOS fabrication. These penetrated dopants act as leakage paths, and they also act as trapped charges, reducing the reliability of the gate, and when penetrating into the channel, causes instability of the operating voltage. do.

In order to remedy this problem, recent research into using a metal as a gate instead of doped polysilicon continues. In the case where the metal is used as the gate, two metals having different work functions for each NMOS transistor and the PMOS transistor are used as the gate electrode in order to satisfy the threshold voltages of the NMOS transistor and the PMOS transistor at a desired value. It is necessary to use, which makes the manufacturing process complicated and difficult.

SUMMARY OF THE INVENTION The present invention is directed to improving the above-mentioned conventional problems, and an object of the present invention is to form a gate by using a combination of semiconductor devices, particularly metals having an appropriate work function, without complicating the manufacturing process of the semiconductor devices, thereby reducing gate depletion. The present invention provides a semiconductor device, particularly a CMOS device, and a method of forming a metal gate of the semiconductor device having a metal gate that is removed, blocks dopant infiltration, and lowers the resistance of the gate.

According to one aspect of the present invention, there is provided a semiconductor device including: a semiconductor substrate having a P well region formed therein; A gate insulating film formed on the semiconductor substrate; And an NMOS metal gate formed of a metal nitride including Mo and Al on the gate insulating layer of the P well region.

According to another aspect of the present invention, there is provided a semiconductor device including: a semiconductor substrate having an N well region formed therein; A gate insulating film formed on the semiconductor substrate; And a metal gate for PMOS formed of MoN having a content of N in the range of 28 to 45% on the gate insulating film of the N well region.

According to another aspect of the present invention, there is provided a semiconductor device including: a semiconductor substrate having a P well region and an N well region; A gate insulating film formed on the semiconductor substrate; A NMOS metal gate formed of a metal nitride containing Mo and Al on the gate insulating film of the P well region and an NMOS metal gate formed of a metal nitride containing Mo on the gate insulating film of the N well region; do.

On the other hand, a method of forming a metal gate of a semiconductor device according to one type of the present invention, forming a gate insulating film on a semiconductor substrate; And forming a metal gate on the gate insulating film, wherein forming the metal gate includes forming a metal gate for NMOS including metal nitride including Mo and Al. .

According to another aspect of the present invention, a method of forming a metal gate of a semiconductor device includes forming a gate insulating film on a semiconductor substrate; And forming a metal gate on the gate insulating film, wherein forming the metal gate includes forming a metal gate for NMOS with MoN having an N content in a range of 28 to 45%. It is characterized by.

According to another aspect of the present invention, there is provided a method of forming a metal gate of a semiconductor device, comprising: preparing a semiconductor substrate having a P well region and an N well region; Forming a gate insulating film on the semiconductor substrate; And forming a metal gate on the gate insulating film, wherein the forming of the metal gate comprises: forming a metal gate for NMOS with metal nitride including Mo and Al on the gate insulating film in the P well region, The metal gate for PMOS is formed of a metal nitride containing Mo on the gate insulating film of the N well region.

According to the present invention, the semiconductor device of the present invention and the metal gate forming method of the semiconductor device have the following effects.

First, dual gates can be implemented based on a single metal nitride, and a method of forming dual gates is relatively simple.

Second, the composition ratio of the metal gate may be adjusted to have a work function suitable for PMOS and NMOS and to have a low specific resistance.

Third, it is excellent in thermal stability and low in reactivity with the high dielectric constant insulating film, which is suitable for the combination of the high dielectric constant gate insulating film and the metal gate.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the examples exemplified below are not intended to limit the scope of the present invention, but are provided to fully explain the present invention to those skilled in the art. In the drawings, the same reference numerals refer to the same components, and the size of each component in the drawings may be exaggerated for convenience of explanation.

1 is a cross-sectional view schematically illustrating a structure of a semiconductor device according to an embodiment of the present invention. Referring to FIG. 1, the semiconductor device 10 is a CMOS device including a PMOS transistor and an NMOS transistor formed on the P-type substrate 11, respectively. In FIG. 1 the PMOS transistor is shown on the left and the NMOS transistor is shown on the right.

The P-type substrate 11 is electrically divided into an N well region 13 and a P well region 14 at the boundary of the device isolation layer 12. Instead of the P-type substrate 11, an N-type substrate or an undoped substrate can be used, which does not limit the invention. PMOS transistors are formed on the N well region 13, and NMOS transistors are formed on the P well region 14. The PMOS transistor includes an N well region 13, a gate insulating layer 19 formed at an upper surface center of the N well region 13, a PMOS metal gate 20 formed on the gate insulating layer 19, and a PMOS metal gate ( A capping layer 21 covering the 20, and a P + doped drain 15 and a source 16, respectively, on the N well region 13 on both sides of the gate insulating layer 19. In addition, the NMOS transistor includes a P well region 14, a gate insulating layer 22 formed at an upper surface center of the P well region 14, an NMOS metal gate 23 formed on the gate insulating layer 22, and the NMOS metal. A capping layer 27 covering the gate 23 and an N + doped drain 17 and a source 18 are respectively disposed on the P well region 14 on both sides of the gate insulating layer 22. The gate insulating layers 19 and 22 may be made of a high dielectric material such as SiO 2 or Al 2 O 3 . Alternatively, the gate insulating layers 19 and 22 may have a multilayer structure including a high dielectric material layer and a SiO 2 layer. Meanwhile, the capping layers 21 and 27 are formed on the PMOS metal gate 20 and the NMOS metal gate 23, respectively, to protect the PMOS metal gate 20 and the NMOS metal gate 23. For example, it may be formed of an oxide such as TiO X , ZrO, MgO, Al 2 O 3 . Since the structure of the gate insulating layers 19 and 22, the capping layers 21 and 27, and the N well region 13 and the P well region 14 itself is well known in the art, a detailed description thereof will be omitted.

The PMOS metal gate 20 and the NMOS metal gate 23 of the present embodiment are formed of a metal nitride based on Mo. In particular, the PMOS metal gate 20 is formed of MoN, and the NMOS metal gate 23 is formed of MoN. ) Is formed of MoAlN. In general, the PMOS metal gate 20 and the NMOS metal gate 23 should be selected to have different work functions. In this embodiment, the work function is appropriately selected by adjusting the contents of N and Al.

2 shows the work function of pure metals. Based on the band structure of the material used as the channel of the MOS device, an appropriate value of the work function of the MOS gate can be selected, for example in the case of Si, the conduction band edge and the valence band edge. band edges) are 4.1 eV and 5.2 eV, respectively, and the work function of p + polysilicon used as a conventional PMOS gate and the n + polysilicon used as a conventional NMOS gate are close to the edge of the CE band and the conduction band. Has a value. As shown in FIG. 2, when using a metal gate as a PMOS gate and an NMOS gate, a pure metal having a work function required for each of the PMOS gate and the NMOS gate can be easily found. However, when two different pure metals are used as the PMOS gate and the NMOS gate, the manufacturing process of the CMOS device is complicated. In addition, pure metals are generally highly reactive with the gate insulating film, which may cause diffusion problems. Therefore, in order to achieve the above object, the present invention, by adding the N and Al to Mo in the mid gap region of silicon, the work function of the PMOS gate and the NMOS gate by controlling the content of the added elements, respectively We want to get the value of work function appropriate for. Such metal nitrides have low reactivity with the gate insulating films 19 and 22, so that diffusion is suppressed.

3 is a graph showing a change in the work function and the specific resistance of MoN according to the N content. Referring to FIG. 3, it can be seen that as the N content increases in MoN, the work function of MoN generally increases linearly. However, as shown in Fig. 3, when the N content is increased, the specific resistance gradually increases, and the conductivity deteriorates. Therefore, if MoN is to be used as the PMOS metal gate 20, it is necessary to appropriately select the work function and the specific resistance. Therefore, the PMOS metal gate 20 of the present embodiment is formed of MoN, but the N content is approximately 28% to 45% so that the work function of MoN is between 4.84eV and 5.0eV, and the N content is 34 It is more preferable that the work function is in the range of 4.9 eV to 5.0 eV so as to be about% to 45%. At this time, by reducing the N content to 45% or less, the PMOS metal gate 20 of the present embodiment may have a specific resistance of less than 1.5 mΩcm of the resistivity of the conventional doped polysilicon. This N content is possible by adjusting the ratio of nitrogen gas supplied when depositing a MoN layer by a sputtering method as mentioned later.

4 is a graph showing a change in the work function of MoAlN according to the Al content. Referring to FIG. 4, it can be seen that the work function of MoAlN decreases linearly as the content of Al in MoAlN increases. For use as the NMOS metal gate 23, the Al content is preferably about 22% to 35%, so that the work function of MoAlN is within the range of 4.2eV to 4.4eV. On the other hand, the content ratio between Mo and N in MoAlN can maintain the content ratio of MoN used as the metal gate for PMOS in consideration of the manufacturing process. At this time, the N content of about 30% to 40%, Mo content is preferably adjusted within the range of about 30% to 50%.

5 is a cross-sectional view schematically illustrating a structure of a semiconductor device according to another embodiment of the present invention. Referring to FIG. 5, the semiconductor device 10 ′ is a CMOS device including a PMOS transistor and an NMOS transistor formed on the P-type substrate 11, respectively. In the present embodiment, the rest of the components except for the NMOS metal gate 26 are substantially the same as the above-described embodiment, and therefore, the same members as those of the semiconductor element shown in FIG. Is omitted. In the NMOS metal gate 26 of this embodiment, a MoAlN layer 24 and a MoN layer 25 are provided on the gate insulating film 22. At this time, the MoAlN layer 24 is a layer formed by first depositing an Al layer by using a heat treatment or the like and then diffusing Al under the MoN layer 25, as described later. The composition change due to Al occurs continuously at the bottom of, which is indicated as a single layer for convenience.

Next, a method of forming a metal gate of the semiconductor device of the above-described embodiments will be described.

6A to 6H illustrate a metal gate forming process of a semiconductor device according to an embodiment of the present invention. The manufacturing method of the present embodiment is a method of manufacturing the semiconductor device described with reference to FIG. 1, and since the previous steps of the gate manufacturing process are substantially the same as the manufacturing process of the conventional CMOS device, a detailed description thereof is omitted and the metal of the semiconductor device is omitted. A method of forming a gate will be described below. In addition, the same reference numerals are given to the same members in FIGS. 6A to 6H, and description thereof will be omitted.

Referring to FIG. 6A, a P-type substrate 11 having an N well region 13 and a P well region 14 is prepared first. In this case, the device isolation layer 12, the drain 15, and the source 18 described with reference to FIG. 1 may be formed on the P-type substrate 11 by a known method. For example, the device isolation layer 12 may be formed using a shallow trench isolation (STI) process or the like.

Referring to FIG. 6B, a dielectric layer 30 is formed by depositing a high-k dielectric material such as SiO 2 or Al 2 O 3 on the P-type substrate 11 having the N well region 13 and the P well region 14. .

Next, referring to FIG. 6C, while Mo is deposited on the dielectric layer 30 by reactive sputtering, N 2 is implanted with Ar and nitrided to form the MoN layer 31. At this time, the N content of the MoN layer is about 28% to 45%, preferably about 34% to 45%. 7 shows the relationship between the flow rate ratio of the injected N 2 / Ar gas and the N content in the deposited MoN layer. Referring to FIG. 7, when the flow rate of N 2 gas to Ar gas is increased from 5% to 60%, it can be seen that the N content in the MoN layer increases linearly from 28% to 61%. This means that the N content can be adjusted by appropriately adjusting the flow rate of the injected N 2 / Ar gas.

Next, referring to FIG. 6D, the remaining regions other than the MoN layer 31 ′ on the N well region 13 may be etched to expose the dielectric layer 30 of the P well region 14.

Next, referring to FIG. 6E, N 2 is injected with N and Ni is deposited on the MoN layer 31 ′ and the exposed dielectric layer 30 by reactive co-sputtering. (nitridation) to form the MoAlN layer 32, and then planarize the MoAlN layer 32 by a polishing process such as CMP (Chemical Mechanical Polishing). At this time, the MoAlN layer 32 has a difference in height between the portion where the lower MoN layer 30 'and the other portion is located. Thus, by polishing the MoAlN layer 32, the N well region where the MoN layer 30' is located ( 13, the MoN layer 30 'is exposed, and in the P well region 14 in which the MoN layer 30' is not located, the MoAlN layer 32 'remains. Al content in the MoAlN layer is approximately 22% to 35%. 8 shows the relationship between the DC power applied to the Al target and the Al content in the deposited MoAlN layer in the sputtering apparatus. Referring to FIG. 8, when the DC power applied to the Mo target is fixed at 100W and the DC power applied to the Al target is increased from 0W to 100W, the Al content in MoAlN increases linearly from 0% to 20%. can see. This means that the Al content can be adjusted by appropriately adjusting the power applied to the Al target of the sputtering apparatus.

Next, referring to FIG. 6G, a capping layer 33 is formed on the MoN layer 30 ′ and the MoAlN layer 32 ′. The capping layer 33 may be formed by depositing an oxide such as TiO X , ZrO, MgO, Al 2 O 3 , for example.

Next, referring to FIG. 6H, the layers including the dielectric layer 30 are patterned in the shape of the gate electrode to complete the electrode structure. That is, in the N well region 13, a dielectric layer 30 ′ of the gate insulating film, a MoN layer 31 ″ of the PMOS metal gate, and a capping layer 33 ′ are formed, and in the P well region 14, a gate insulating film is formed. The dielectric layer 30 ', the MoAlN layer 32 "of the NMOS metal gate, and the capping layer 33' are formed. In Fig. 6H, reference numerals written in parentheses next to reference numerals denote reference numerals of members corresponding to Fig. 1.

9A to 9H illustrate a metal gate forming process of a semiconductor device according to another embodiment of the present invention. The manufacturing method of the present embodiment is a method of manufacturing the semiconductor device described with reference to FIG. 5, and since the previous steps of the gate manufacturing process are substantially the same as the manufacturing process of the conventional CMOS device, a detailed description thereof is omitted and the metal of the semiconductor device is omitted. A method of forming a gate will be described below. In addition, the same reference numerals are given to the same members in FIGS. 9A to 9H, and description thereof will be omitted.

9A and 9B, first, a P-type substrate 11 having an N well region 13 and a P well region 14 is prepared, and SiO 2 , Al 2 O 3 , or the like is formed on the P-type substrate 11. The same high dielectric material is deposited to form the dielectric layer 40. This is the same as the steps described with reference to FIGS. 6A and 6B described above.

Next, referring to FIG. 9C, Al is deposited on the P-type substrate 11 having the N well region 13 and the P well region 14 by sputtering to form an Al layer 41. At this time, the Al layer 41 is formed to have a thickness of approximately 30 kPa to 150 kPa.

Next, referring to FIG. 9D, the remaining regions except for the Al layer 41 ′ on the N well region 13 are etched to expose the dielectric layer 40 of the P well region 14.

Next, referring to FIG. 9E, while Mo is deposited on the Al layer 41 and the exposed dielectric layer 40 by a reactive sputtering method, N 2 is implanted together with Ar to form a MoN layer 43. At this time, the thickness of the MoN layer 43 is formed to be approximately 5 to 8 times the thickness of the Al layer 41. On the other hand, the flow rate ratio of the injected N 2 / Ar gas is appropriately adjusted so that the N content of the MoN layer is about 28% to 45%, preferably about 34% to 45%.

Next, referring to FIG. 9F, a capping layer 44 is formed on the MoN layer.

Next, referring to FIG. 9G, a high temperature annealing process is performed in an N 2 atmosphere to induce diffusion of Al into the interface between the Al layer (41 ′ in FIG. 9F) and the MoN layer 43, thereby causing the MoAlN layer 42 to be dispersed. ). As a result, the Al layer 41 ′ diffuses into the MoN layer 43, and the lower portion of the MoN layer 43 changes to the MoAlN layer 42. For example, after forming an Al layer with a thickness of 50 μs, stacking a 300 μm thick MoN layer and annealing at 500 ° C., the Al content was approximately 11% near the interface between the Al layer and the MoN layer. .

Next, referring to FIG. 9H, the MoN layer 40 and the MoAlN layer 42 are patterned in the shape of the gate electrode to complete the electrode structure. That is, the dielectric layer 40 'of the gate insulating film, the MoN layer 43' of the PMOS metal gate, and the capping layer 44 'are formed in the N well region 13, and the gate insulating film is formed in the P well region 14. A dielectric layer 40 ', MoAlN / MoN layers 42', 43 'of the NMOS metal gate, and a capping layer 44' are formed. In Fig. 6H, reference numerals written in parentheses next to reference numerals denote reference numerals of members corresponding to Fig. 5.

Such a semiconductor device and a method of forming a metal gate of the semiconductor device of the present invention have been described with reference to the embodiments shown in the drawings for clarity, but this is merely an example, and those skilled in the art will appreciate It will be understood that various modifications and other equivalent embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the appended claims.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal gate, and can be applied to a MOS transistor to which a metal gate is applied, a CMOS device composed of a PMOS transistor and an NMOS transistor, and various logic gate devices using a CMOS device. In particular, by using a metal gate based on Mo in place of a doped polysilicon gate that is difficult to use at very small scales of 50 nm or less, the present invention can be applied to highly integrated semiconductor devices based on MOS devices.

1 is a cross-sectional view schematically illustrating a structure of a semiconductor device according to an embodiment of the present invention.

2 is a graph showing the distribution of work functions of pure metals.

3 is a graph showing a change in the work function and the specific resistance of MoN according to the N content.

4 is a graph showing a change in the work function of MoAlN according to the Al content.

5 is a cross-sectional view schematically illustrating a structure of a semiconductor device according to another embodiment of the present invention.

6A through 6H are cross-sectional views schematically illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

7 is a graph showing the change of N content in MoN according to the Ar / N 2 gas ratio.

8 is a graph showing a change in Al content in MoAlN according to the power applied to Al.

9A to 9H are cross-sectional views schematically illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

※ Explanation of code about main part of drawing ※

10, 10 ′ ... CMOS device 11 ... substrate

12 ... Device Separator 13 ... N Well

14 ... Pwell 15,17 ... Source

16,18 Drain 19,22 Gate Insulation

20,22,26 ... Metal gate 21,27 ... Capping layer

Claims (23)

A semiconductor substrate on which a P well region is formed; A gate insulating film formed on the semiconductor substrate; And an NMOS metal gate formed of a metal nitride including Mo and Al on the gate insulating layer of the P well region. The method of claim 1, The metal nitride containing Mo and Al is a semiconductor device, characterized in that MoAlN. The method of claim 2, The content of Al is a semiconductor device, characterized in that in the range of 22% to 32%. The method of claim 2, And the Al content is controlled such that the work function of the NMOS metal gate is within the range of 4.25 eV to 4.35 eV. The method of claim 1, The NMOS metal gate includes a MoAlN layer formed on the gate insulating film and a MoN layer formed on the MoAlN layer. The method according to any one of claims 1 to 5, The semiconductor substrate further includes an N well region. And the semiconductor device is a CMOS device including an NMOS transistor formed in the P well region and a PMOS transistor formed in the N well region. The method of claim 6, The metal gate for NMOS is the metal gate for NMOS, And the metal gate for PMOS is a metal gate for PMOS formed of metal nitride containing Mo on a gate insulating film formed on a semiconductor substrate in the N well region. The method of claim 7, wherein The metal nitride including Mo is MoN, wherein the content of N is a semiconductor device, characterized in that in the range of 28 ~ 45%. The method of claim 8, In the metal nitride containing Mo, the content of N is a semiconductor device, characterized in that in the range of 34 ~ 45%. A semiconductor substrate having an N well region formed thereon; A gate insulating film formed on the semiconductor substrate; And a PMOS metal gate formed of MoN having a content of N in the range of 28 to 45% on the gate insulating film of the N well region. Forming a gate insulating film on the semiconductor substrate; And Forming a metal gate on the gate insulating film; Forming the metal gate, A metal gate forming method of a semiconductor device comprising the step of forming a metal gate for NMOS consisting of a metal nitride containing Mo and Al. The method of claim 11, The NMOS metal gate is formed by forming a MoAlN layer by nitriding Mo and Al by reactive co-sputtering to form a MoAlN layer. The method of claim 12, The composition ratio of Mo and Al in the MoAlN layer is controlled by controlling the power applied to each of Mo and Al. The method of claim 13, The method of forming a metal gate of the semiconductor device, characterized in that to form a MoAlN layer so that the Al content in the MoAlN layer in the range of 22% to 32%. The method of claim 11, Forming the metal gate for the NMOS, Forming an Al layer on the gate insulating film; Forming a MoN layer on the Al layer; And Diffusing Al of the Al layer on the lower side of the MoN layer to form a MoAlN layer on the lower portion of the MoN layer. The method of claim 15, The Al layer is formed to a thickness of 30 kHz to 150 kHz metal gate forming method of a semiconductor device. The method of claim 15, And diffusing Al of the Al layer to the lower side of the MoN layer through annealing at a temperature of 300 to 800 degrees in an N 2 atmosphere. Forming a gate insulating film on the semiconductor substrate; And Forming a metal gate on the gate insulating film; Forming the metal gate, Forming a metal gate for PMOS with MoN content of N in the range of 28 to 45%. Providing a semiconductor substrate having a P well region and an N well region formed thereon; Forming a gate insulating film on the semiconductor substrate; And Forming a metal gate on the gate insulating film; Forming the metal gate, Forming an NMOS metal gate with a metal nitride containing Mo and Al on the gate insulating film in the P well region, and forming a PMOS metal gate with a metal nitride containing Mo on the gate insulating film in the N well region A metal gate forming method of a semiconductor device. The method of claim 19, Forming the metal gate, Forming a MoN layer on the gate insulating film; Etching a portion of the MoN layer to expose the gate insulating layer over the p well region; Forming a MoAlN layer on the MoN layer from which the portion is removed and the gate insulating layer in the p well region; Removing the MoAlN layer on the MoN layer, and planarizing the MoAlN layer to expose the MoN layer in the n well region; And Patterning each of the MoAlN layers in the p-well region and the MoN layers in the n-well region in the shape of metal gates for NMOS and PMOS. The method of claim 20, And forming a capping layer after planarizing the MoAlN layer. The method of claim 19, Forming the metal gate, Forming an Al layer on the gate insulating film; Etching a portion of the Al layer to expose a gate insulating layer on the n well region; Forming a MoN layer on the Al layer from which the portion is removed and the gate insulating layer in the n well region; Diffusing Al of the Al layer below the MoN layer to form a MoAlN layer below the MoN layer; And Patterning each of the MoAlN / MoN layers in the p-well region and the MoN layers in the n-well region in the shape of metal gates for NMOS and PMOS. The method of claim 21, And forming a capping layer after the MoN layer is formed.
KR1020070096945A 2007-09-21 2007-09-21 Semiconductor device and method for fabricating metal gate of the semiconductor device KR20090031103A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070096945A KR20090031103A (en) 2007-09-21 2007-09-21 Semiconductor device and method for fabricating metal gate of the semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070096945A KR20090031103A (en) 2007-09-21 2007-09-21 Semiconductor device and method for fabricating metal gate of the semiconductor device

Publications (1)

Publication Number Publication Date
KR20090031103A true KR20090031103A (en) 2009-03-25

Family

ID=40697282

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070096945A KR20090031103A (en) 2007-09-21 2007-09-21 Semiconductor device and method for fabricating metal gate of the semiconductor device

Country Status (1)

Country Link
KR (1) KR20090031103A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101348010B1 (en) * 2012-03-20 2014-01-08 한국산업기술대학교산학협력단 Manufacturing method for electrode wire and substrate using the same
US11552177B2 (en) 2020-09-04 2023-01-10 Applied Materials, Inc. PMOS high-K metal gates

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101348010B1 (en) * 2012-03-20 2014-01-08 한국산업기술대학교산학협력단 Manufacturing method for electrode wire and substrate using the same
US11552177B2 (en) 2020-09-04 2023-01-10 Applied Materials, Inc. PMOS high-K metal gates

Similar Documents

Publication Publication Date Title
CN101421839B (en) Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled cmos devices
US9190409B2 (en) Replacement metal gate transistor with controlled threshold voltage
US7344934B2 (en) CMOS transistor and method of manufacture thereof
US7531400B2 (en) Methods for fabricating MOS transistor gates with doped silicide
CN101675513B (en) Threshold adjustment for high-k gate dielectric cmos
US8420486B2 (en) Method for manufacturing semiconductor device
US9466600B2 (en) Semiconductor device and method of manufacturing the same
CN101304031B (en) Ciucuit structure and manufacturing method thereof
US20060208320A1 (en) MIS-type semiconductor device
EP1538674A2 (en) Semiconductor device
KR101036771B1 (en) Semiconductor device and method for manufacturing same
TW201320166A (en) High-k metal gate structure fabrication method including hard mask
JP2006332179A (en) Semiconductor device and its manufacturing method
US7956413B2 (en) Semiconductor device having a field effect transistor using a high dielectric constant gate insulating film and manufacturing method of the same
CN101364599B (en) CMOS structure, method for processing cmos structure and processer containing at least cmos circuit
US20070257320A1 (en) Semiconductor device and manufacturing method thereof
KR20090031103A (en) Semiconductor device and method for fabricating metal gate of the semiconductor device
US20080224223A1 (en) Semiconductor device and method for fabricating the same
US20070026596A1 (en) Gate electrode structure and method of forming the same, and semiconductor transistor having the gate electrode structure and method of manufacturing the same
US7800186B2 (en) Semiconductor device and method of fabricating metal gate of the same
KR100668507B1 (en) Semiconductor device with dual metal gate and method for manufacturing the same
JP5149936B2 (en) SEMICONDUCTOR DEVICE HAVING FIELD EFFECT TRANSISTOR HAVING HIGH DIELECTRIC GATE INSULATION FILM AND METHOD FOR MANUFACTURING SAME

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application