KR20090009461A - Electrostatic discharge device - Google Patents

Electrostatic discharge device Download PDF

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Publication number
KR20090009461A
KR20090009461A KR1020070072749A KR20070072749A KR20090009461A KR 20090009461 A KR20090009461 A KR 20090009461A KR 1020070072749 A KR1020070072749 A KR 1020070072749A KR 20070072749 A KR20070072749 A KR 20070072749A KR 20090009461 A KR20090009461 A KR 20090009461A
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South Korea
Prior art keywords
electrostatic discharge
driving voltage
voltage
unit
pad
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KR1020070072749A
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Korean (ko)
Inventor
손희정
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주식회사 하이닉스반도체
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Priority to KR1020070072749A priority Critical patent/KR20090009461A/en
Publication of KR20090009461A publication Critical patent/KR20090009461A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/08104—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

An electrostatic discharge device is provided to install a plurality of electrostatic discharge parts including a plurality of diodes and including an NMOS transistor which can be discharged and turned on even in lower static electricity, thereby preventing that a transistor gate insulating layer of an input buffer is destroyed. An electrostatic discharge device comprises the followings. A first electrostatic discharge part(20) discharges static electricity to a first electric discharge line(VDD) when the static electricity is generated in a pad(10). A second electrostatic discharge part(30) is applied with bias voltage and driving voltage from the first electrostatic discharge part, and discharges the static electricity generated in pad to a second electric discharge line(VSS). A third electrostatic discharge part(40) is applied with the driving voltage from the first electrostatic discharge part, discharges the static electricity generated in pad to the second electric discharge line, and is connected to an input buffer of an internal circuit. The first electrostatic discharge part comprises the followings. A bias confirmation part(22) applies the bias voltage to the second electrostatic discharge part through two nodes. A driving voltage applying part(24) applies the driving voltage to the second and third electrostatic discharge parts. An electrostatic discharge route(26) discharges static electrostatic voltage corresponding to the driving voltage to a power voltage line.

Description

Electrostatic Discharge Device

1 is a block diagram showing an embodiment of the electrostatic discharge device of the present invention.

2 is a circuit diagram showing a first embodiment of the electrostatic discharge device according to FIG.

3 is a circuit diagram showing a second embodiment of the electrostatic discharge device according to FIG. 2;

4 is a block diagram showing another embodiment of the electrostatic discharge device of the present invention.

5 is a circuit diagram showing a first embodiment of the electrostatic discharge device according to FIG. 5;

6 is a circuit diagram showing a second embodiment of the electrostatic discharge device according to FIG.

7 is a graph measuring the gate voltage according to the present invention.

<Description of Main Parts of Drawing>

10: input and output pad 20: first electrostatic discharge unit

22: bias applying unit 24: driving voltage applying unit

26: electrostatic discharge path 30: second electrostatic discharge portion

40: third electrostatic discharge portion 50: input buffer

60: internal circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to electrostatic discharge (ESD) devices that protect semiconductor devices from static electricity.

In general, when a semiconductor integrated circuit is in contact with a charged human body or a machine, the static electricity charged in the human body or the machine is discharged into the semiconductor through an input / output pad through an external pin of the integrated circuit, and thus has a large energy transient current wave. Can seriously damage the semiconductor internal circuit. In addition, the static electricity that has been charged inside the semiconductor circuit flows through the machine due to the contact of the machine to damage the external circuit.

Thus, most semiconductor integrated circuits have circuits that discharge static electricity between the input / output pads and the semiconductor internal circuitry to protect the main circuit from such damage.

The electrostatic discharge circuit may be composed of various elements. In particular, when an NMOS transistor is used as an electrostatic discharge element, a grounded-gate NMOS having a structure in which a gate and a source are connected is mainly used.

At this time, the input / output pad is connected to the drain of the NMOS transistor, and when the voltage level of the drain rises due to static electricity, an avalanche breakdown occurs between the drain of the NMOS transistor and the substrate so that an electrostatic current flows to the substrate. do.

When the level of the substrate voltage rises above the source voltage level of the NMOS transistor by the electrostatic current flowing to the substrate, the electrostatic current is discharged from the drain to the source of the NMOS transistor by the BJT characteristic of the NMOS transistor.

At this time, when the turn-on voltage of the NMOS transistor is high, there is a possibility that the transistor gate insulating film inside the input buffer is destroyed. That is, when the turn-on voltage is higher than the breakdown voltage of the gate insulating film of the input buffer, the gate insulating film of the transistor of the input buffer is destroyed before the MOS transistor for discharging static electricity.

In particular, as the recent technology advances, the thickness of the gate insulating film of the transistor constituting the input / output buffer rapidly decreases, and the gate insulating film breakdown voltage is rapidly decreasing. Therefore, there is an urgent need to reduce the turn-on voltage of the electrostatic discharge unit.

An object of the present invention is to provide an electrostatic discharge device having excellent electrostatic discharge performance of electrostatic discharge elements in each path while providing various discharge paths.

Another object of the present invention is to lower the turn-on voltage of an electrostatic discharge device.

An electrostatic discharge device according to an embodiment of the present invention for achieving the above object comprises a first electrostatic discharge unit for discharging the static electricity to the first discharge line when the static electricity in the pad; A second electrostatic discharge unit configured to receive a bias voltage and a driving voltage from the first electrostatic discharge unit to discharge static electricity generated from the pad to a second discharge line; And a third electrostatic discharge unit configured to receive the driving voltage from the first electrostatic discharge unit to discharge static electricity generated from the pad to a second discharge line, and to be connected to an input buffer of an internal circuit.

Preferably, the first discharge line is a power supply voltage line, and the second discharge line is a ground voltage line.

The first electrostatic discharge unit is a bias applying unit for applying a bias voltage to the second electrostatic discharge unit in response to the static electricity generated in the pad; A driving voltage applying unit applying a driving voltage to the second electrostatic discharge unit and a third electrostatic discharge unit in response to the bias voltage; And an electrostatic discharge path configured to discharge the static electricity corresponding to the driving voltage to the first discharge line in response to the driving voltage.

The driving voltage applying unit may be connected to an output terminal of the bias applying unit.

The bias applying unit may include one or more diodes connected between the pad and the driving voltage applying unit.

The bias applying unit may include at least one MOS transistor connected between the pad and the driving voltage applying unit, and a gate of the MOS transistor may be connected to the first discharge line.

The bias applying unit may include a plurality of MOS transistors connected in series between the pad and the driving voltage applying unit, and gates of the plurality of MOS transistors may be commonly connected to the first discharge line.

The driving voltage applying unit includes one or more diodes formed between the bias applying unit and the electrostatic discharge path.

The driving voltage applying unit may include at least one MOS transistor connected between the bias applying unit and the electrostatic discharge path, and the gate of the MOS transistor may be connected to the first discharge line.

The electrostatic discharge path may include one or more diodes connected between the first electrostatic discharge unit and the first discharge line.

The electrostatic discharge path may include at least one MOS transistor connected between the first electrostatic discharge unit and the first discharge line, and the gate of the MOS transistor may be connected to the first discharge line.

The first electrostatic discharge unit may further include a resistor connected between the first discharge line and the electrostatic discharge path.

The second electrostatic discharge unit may include a MOS transistor forming a current path between the pad and the second discharge line in response to the bias voltage and the driving voltage.

The bias voltage may be applied to the substrate of the MOS transistor, and the driving voltage may be applied to the gate of the MOS transistor.

The second electrostatic discharge unit may further include a resistor connected between the gate of the MOS transistor and the second discharge line.

The third electrostatic discharge unit may receive the driving voltage and the bias voltage from the first electrostatic discharge unit to discharge static electricity generated from the pad to the second discharge line.

The first electrostatic discharge unit is a bias applying unit for applying a bias voltage to the second electrostatic discharge unit and the third electrostatic discharge unit in response to the static electricity generated in the pad; A driving voltage applying unit applying a driving voltage to the second electrostatic discharge unit and a third electrostatic discharge unit in response to the bias voltage; And an electrostatic discharge path configured to discharge the static electricity corresponding to the driving voltage to the first discharge line in response to the driving voltage.

The third electrostatic discharge unit may include a MOS transistor forming a current path between the second discharge lines in response to a driving voltage applied from the first electrostatic discharge unit.

Static electricity may be applied to the drain terminal of the MOS transistor from the pad, and the driving voltage may be applied to the gate terminal of the MOS transistor.

The bias voltage may be applied to the substrate of the MOS transistor.

A resistance element may be formed between the drain terminal of the MOS transistor and the pad.

In addition, the electrostatic discharge device according to the present invention includes a diode chain connected to the external input and output pad; A first NMOS transistor having a drain connected simultaneously to the input / output pad and an anode of a diode chain; And a second NMOS transistor whose drain is simultaneously connected to the input / output pad and an anode of the diode chain, wherein a bias voltage is applied to a substrate of the first NMOS transistor from a first node of the diode chain. A driving voltage is applied to a gate of the first NMOS transistor and the gate of the second NMOS transistor from a second node.

The first node of the diode chain may further apply a bias voltage to the substrate of the second NMOS transistor.

Preferably, the voltage of the second node is lower than the voltage of the first node.

A first resistance element may be connected to the anode side of the diode chain.

Electrostatic characterized in that the second resistance element is connected to the gate terminal of the first NMOS transistor

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing an embodiment of an electrostatic discharge device according to the present invention.

As shown, the electrostatic discharge device according to the present invention includes a first electrostatic discharge unit 20 for receiving static electricity from an input / output pad and discharging it to a power supply voltage (VDD) line, and receiving a static electricity from the input / output pad and a ground voltage ( And a second electrostatic discharge unit 30 and a third electrostatic discharge unit 40 for discharging to the VSS) line.

In the first electrostatic discharge unit, a driving voltage is provided to the second electrostatic discharge unit and the third electrostatic discharge unit so that the second electrostatic discharge unit and the third electrostatic discharge unit are turned on at a lower voltage.

A detailed configuration of the electrostatic discharge unit will be described with reference to FIG. 2.

Referring to FIG. 2, the first electrostatic discharge unit 20 includes a plurality of diodes (hereinafter referred to as diode chains) connected in series to discharge to the power supply voltage VDD in response to static electricity generated from the pad 10. .

The diode chain includes a bias applying unit 22 for applying a bias voltage to the substrate of the NMOS transistor N1 through the two nodes (node A and node B) to the second electrostatic discharge unit 30 as shown, A driving voltage applying unit 24 for applying a driving voltage to the second electrostatic discharge unit 30 and the third electrostatic discharge unit 40 and a static voltage corresponding to the driving voltage are discharged to a power supply voltage VDD line. Which includes an electrostatic discharge path 26. The cathode of the diode is connected in the direction of the power supply voltage VDD, and the anode of the diode is connected in the direction of the pad 10. The electrostatic discharge path 26 corresponds to an electrostatic discharge unit which finally discharges static electricity to a power supply voltage line, but is a component of the first electrostatic discharge unit 20 and there is a risk of confusion when using the name of the electrostatic discharge unit. The electrostatic discharge path 26 will be referred to.

The bias applying unit 22 applies a bias voltage to the substrate of the NMOS transistor N1 of the second electrostatic discharge unit 30 through the node A, and the driving voltage applying unit 24 supplies the second electrostatic discharge unit ( 30) applies a driving voltage to the node B. The bias voltage is a voltage dropped by the diode of the bias applying unit 22 in the static electricity input through the input / output pad and the driving voltage is a diode of the bias applying unit 22 and the driving voltage applying unit 24 in the input static electricity. Is the voltage dropped across the diode.

The second electrostatic discharge unit 30 includes an NMOS transistor N1 which forms a current path path between the pad 10 and the ground voltage VSS in response to the driving voltage, and the NMOS transistor N2 is driven faster. The resistor R1 may be further connected between the gate of the NMOS transistor N1 and the ground voltage VSS.

Here, the gate of the NMOS transistor N1 is connected between the driving voltage applying unit 24 and the electrostatic discharge path 26, the drain (or source) of the NMOS transistor N2 is connected to the pad 10, and the NMOS The source (or drain) of the transistor N1 is connected to the ground voltage VSS.

The third electrostatic discharge part 40 includes an NMOS transistor N2 that is turned on when static electricity is applied to form an electrostatic discharge path. In addition, a resistance element R2 may be formed between the input / output pad 10 and the drain terminal for current regulation and circuit protection.

The gate of the NMOS transistor N2 is connected to the node B of the first electrostatic discharge part 20 to apply a driving voltage, and the source is connected to the ground voltage VSS line. The drain is directly connected to the input / output pad to apply static electricity.

Looking at the operation of the electrostatic discharge device, the positive static electricity generated in the pad 10 is discharged to the power supply voltage (VDD) through the diode chain (22, 24, 26). The electrostatic voltage dropped through the bias applying unit 22 of the diode chain is applied as a bias voltage to the substrate of the NMOS transistor N1 through the node A, and the electrostatic voltage dropped through the driving voltage applying unit 24. Is transferred to the gate of the second electrostatic discharge unit 30 through the node B. At this time, a voltage drop occurs in the ESD current by the resistor R1. Accordingly, the transistor N1 is turned on by being applied to the gate of the NMOS transistor N1 formed between the pad 10 and the ground voltage VSS.

At this time, since the bias is applied to the substrate of the NMOS transistor through the node A, the trigger voltage is lowered. In this embodiment, since node B passes through one or more diodes more than node A, the voltage of node A is approximately 0.7 volts higher than that of node B. In other words, by applying a higher bias voltage to the substrate, the threshold voltage of the NMOS transistor N1 can be lowered, and as a result, the NMOS transistor can be easily turned on and discharge static electricity even with low static electricity. As the NMOS transistor N1 is turned on, the static electricity generated in the pad 10 is transferred to the ground voltage VSS.

As described above, the static electricity applied through the input / output pad 10 is discharged to the power supply voltage VDD line and the ground voltage VSS line through the first electrostatic discharge unit 20 and the second electrostatic discharge unit 30.

In addition, since the input / output pad is also connected to the third electrostatic discharge unit 40, the input / output pad is discharged to the ground voltage VSS line through the third electrostatic discharge unit 40.

At this time, an electrostatic voltage is applied to the drain terminal of the NMOS transistor N2 of the third electrostatic discharge unit 40, and a voltage dropped through the diode chains 22 and 24 is input to the gate terminal of the NMOS transistor N2. The threshold voltage of is lower than using a GGNMOS transistor.

Therefore, since the NMOS transistor N2 is turned on and discharged even at lower static electricity, the gate insulating layer of the input buffer 50 NMOS transistor N3 can be prevented from being destroyed.

As shown in FIG. 3, the first electrostatic discharge unit 20 includes a bias applying unit 22, a driving voltage applying unit 24, and an electrostatic discharge path 26 each consisting of one or a plurality of PMOS transistors instead of diodes. It may be configured as.

That is, the bias applying unit 22 and the driving voltage applying unit 24 may be composed of at least one PMOS transistor. At this time, the gate of the PMOS transistor is connected to the power supply voltage VDD.

In addition, the electrostatic discharge path 26 may include at least one PMOS transistor connected between the driving voltage applying unit 24 and the power supply voltage VDD, or between the driving voltage applying unit 24 and the power supply voltage VDD. It may be composed of a plurality of PMOS transistors connected in series. At this time, the gate of the PMOS transistor is connected to the power supply voltage VDD.

4 is a block diagram of another embodiment of the present invention.

In this embodiment, a bias voltage is also applied to the substrate of the transistor of the third electrostatic discharge part 40.

Although the configurations of the first electrostatic discharge unit 20 and the second electrostatic discharge unit 30 are the same, a turn-on voltage of the NMOS transistor can be lowered by applying a bias voltage to the NMOS transistor substrate of the third electrostatic discharge unit 40. have.

FIG. 5 shows a detailed circuit configuration of FIG. 4.

The first electrostatic discharge unit 20 is composed of a diode chain and is divided into a bias applying unit 22, a driving voltage applying unit 24, and an electrostatic discharge path 26 by two nodes (nodes A and B). do. In this case, the cathode of the diode is connected to the power supply voltage VDD, and the anode of the diode is connected to the pad 10 as described above.

That is, the bias applying unit 22, the driving voltage applying unit 24 and the electrostatic discharge path 26 are all made of a diode, the cathode of the diode is connected to the power supply voltage (VDD), the anode of the diode pad 10 Connected to the

The second electrostatic discharge unit 30 includes an NMOS transistor N1 and a resistor R1, and a bias voltage is applied from the first electrostatic discharge unit 20 to the substrate of the NMOS transistor, and the gate terminal is disposed at the gate end. The driving voltage is applied from the first electrostatic discharge unit 20 as described above.

According to the present exemplary embodiment, the drain terminal of the third electrostatic discharge unit 30 is connected to the input / output pad so that an electrostatic voltage is input, and the gate end is connected to the node B of the first electrostatic discharge unit 10 to supply the driving voltage. The driving voltage is applied through the same as in the embodiment of FIG. 3.

The difference is that a bias voltage is applied to the substrate of the NMOS transistor N2 through the node A of the first electrostatic discharge unit 20.

As described above, by applying a bias voltage to the substrate of the NMOS transistor N2, the turn-on voltage of the transistor N2 may be further lowered. That is, since the NMOS transistor N2 may be turned on faster, the electrostatic discharge performance may be further improved by the electrostatic discharge unit 30.

As shown in FIG. 6, the first electrostatic discharge unit 20 includes a bias applying unit 22, a driving voltage applying unit 24, and an electrostatic discharge path 26, each consisting of one or more PMOS transistors instead of a diode. It may be configured as.

7 is a graph simulating the effect of the electrostatic discharge device according to the present invention.

In order to confirm that the turn-on voltage is lowered, a case of using a GGNMOS transistor in which a conventional gate is grounded and applying a driving voltage to the gate through the first electrostatic discharge unit 20 as described in the previous embodiment of the present invention. The turn-on voltage of is measured.

In the graph, V1 measures the gate voltage of the NMOS transistor N2 of the third electrostatic discharge part 40, and V2 measures the gate voltage of the NMOS transistor N3 of the input buffer 50.

V1_GGNMOS measures the gate voltage of the NMOS transistor N3 of the third electrostatic discharge part 4 when the GGNMOS transistor is used as in FIG. 1 according to the prior art, and V2_GGNMOS is the GGNMOS transistor N4 of the input buffer 5. The gate voltage of is measured.

As can be seen from the simulation results, it can be seen that the gate voltage of the input buffer 50 is lower in the case of the present invention than in the case of GGNMOS. Therefore, it is possible to prevent the gate insulating layer from being destroyed before the transistor is turned on.

As described above, according to the present invention, the turn-on voltage of the transistor can be reduced without increasing the layout area of the electrostatic discharge device.

In addition, according to the present invention, the transistor gate insulating film of the input buffer can be prevented from being destroyed.

In addition, the present invention can provide an electrostatic discharge device having excellent electrostatic discharge performance by lowering the trigger voltage by applying a bias to the substrate of the transistor.

While the invention has been shown and described with reference to specific embodiments, the invention is not limited thereto, and the invention is not limited to the scope of the invention as defined by the following claims. Those skilled in the art will readily appreciate that modifications and variations can be made.

Claims (28)

A first electrostatic discharge unit configured to discharge the static electricity to the first discharge line when static electricity is generated in the pad; A second electrostatic discharge unit configured to receive a bias voltage and a driving voltage from the first electrostatic discharge unit to discharge static electricity generated from the pad to a second discharge line; And And a third electrostatic discharge unit configured to receive the driving voltage from the first electrostatic discharge unit to discharge static electricity generated from the pad to a second discharge line and to be connected to an input buffer of an internal circuit. Device. The method of claim 1, And wherein the first discharge line is a power supply voltage line and the second discharge line is a ground voltage line. The method of claim 1, The first electrostatic discharge unit is a bias applying unit for applying a bias voltage to the second electrostatic discharge unit in response to the static electricity generated in the pad; A driving voltage applying unit applying a driving voltage to the second electrostatic discharge unit and a third electrostatic discharge unit in response to the bias voltage; And And an electrostatic discharge path for discharging static electricity corresponding to the driving voltage to the first discharge line in response to the driving voltage. The method of claim 3, wherein And the driving voltage applying unit is connected to an output terminal of the bias applying unit. The method of claim 3, wherein And the bias applying unit includes at least one diode connected between the pad and the driving voltage applying unit. The method of claim 3, wherein And the bias applying unit includes at least one MOS transistor connected between the pad and the driving voltage applying unit, and a gate of the MOS transistor is connected to the first discharge line. The method of claim 3, wherein The bias applying unit includes a plurality of MOS transistors connected in series between the pad and the driving voltage applying unit, and the gates of the plurality of MOS transistors are connected in common to the first discharge line. . The method of claim 3, wherein The driving voltage applying unit includes at least one diode formed between the bias applying unit and the electrostatic discharge path. The method of claim 3, wherein The driving voltage applying unit includes at least one MOS transistor connected between the bias applying unit and the electrostatic discharge path, and the gate of the MOS transistor is connected to the first discharge line. The method of claim 3, wherein And the electrostatic discharge path comprises at least one diode connected between the first electrostatic discharge and the first discharge line. The method of claim 3, wherein The electrostatic discharge path includes at least one MOS transistor connected between the first electrostatic discharge unit and the first discharge line, wherein the gate of the MOS transistor is connected to the first discharge line. . The method of claim 3, wherein The first electrostatic discharge unit further comprises a resistor connected between the first discharge line and the electrostatic discharge path. The method of claim 1, And the second electrostatic discharge unit includes a MOS transistor forming a current path between the pad and the second discharge line in response to the bias voltage and the driving voltage. The method of claim 13, The bias voltage is applied to the substrate of the MOS transistor, and the driving voltage is applied to the gate of the MOS transistor. The method of claim 13, The second electrostatic discharge unit further comprises a resistor connected between the gate of the MOS transistor and the second discharge line. The method of claim 1, And the third electrostatic discharge unit receives the driving voltage and the bias voltage from the first electrostatic discharge unit to discharge the static electricity generated from the pad to the second discharge line. The method of claim 16, The first electrostatic discharge unit is a bias applying unit for applying a bias voltage to the second electrostatic discharge unit and the third electrostatic discharge unit in response to the static electricity generated in the pad; A driving voltage applying unit applying a driving voltage to the second electrostatic discharge unit and a third electrostatic discharge unit in response to the bias voltage; And And an electrostatic discharge path for discharging static electricity corresponding to the driving voltage to the first discharge line in response to the driving voltage. The method of claim 16, And the third electrostatic discharge unit includes a MOS transistor forming a current path between the second discharge lines in response to a driving voltage applied from the first electrostatic discharge unit. The method of claim 16, Electrostatic discharge is applied to the drain terminal of the MOS transistor from the pad, the driving voltage is applied to the gate terminal of the MOS transistor. The method of claim 16, And the bias voltage is applied to a substrate of the MOS transistor. The method of claim 16, And a resistance element is formed between the drain terminal of the MOS transistor and the pad. A diode chain connected to an external input / output pad; A first NMOS transistor having a drain connected simultaneously to the input / output pad and an anode of a diode chain; And And a second NMOS transistor whose drain is simultaneously connected to the input / output pad and the anode of the diode chain. Applying a bias voltage from the first node of the diode chain to the substrate of the first NMOS transistor and applying a driving voltage from the second node of the diode chain to the gate of the first NMOS transistor and the gate of the second NMOS transistor; Electrostatic discharge device characterized in that. The method of claim 22, And the first node of the diode chain further applies a bias voltage to the substrate of the second NMOS transistor. The method of claim 22 or 23, And the voltage of the second node is lower than the voltage of the first node. The method of claim 22 or 23, Electrostatic discharge device, characterized in that the first resistance element is connected to the anode side of the diode chain. The method of claim 22 or 23, And a second resistance element is connected to the gate terminal of the first NMOS transistor. The method of claim 22 or 23, And a third resistance element is connected to the drain terminal and the input / output pad of the second NMOS transistor. The method of claim 22 or 23, And a PMOS transistor chain in place of the diode chain.
KR1020070072749A 2007-07-20 2007-07-20 Electrostatic discharge device KR20090009461A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200001535A (en) * 2018-06-26 2020-01-06 비쉐이-실리코닉스 Protection circuits with negative gate swing capability

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200001535A (en) * 2018-06-26 2020-01-06 비쉐이-실리코닉스 Protection circuits with negative gate swing capability

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