KR20080100808A - Master electrode and method of forming it - Google Patents

Abstract

A system and method comprising a master electrode arranged on substrate, said master electrode comprising a pattern layer, least partly of an insulating material and having a first surface provided with a plurality of cavities in which a conducting material is arranged, said electrode conducting material being electrically connected to at least one electrode current supply contact; said substrate comprising a top surface in contact with or arranged adjacent said first surface and having conducting material and/or structures of a conducting material arranged thereon, said substrate conducting material being electrically connected to at least one current supply contact; whereby a plurality of electrochemical cells are formed delimited by said cavities, said substrate conducting material and said electrode conducting material, said cells comprising an electrolyte; herein an electrode resistance between said electrode conducting material and said electrode current supply contact and a substrate resistance between said substrate conducting material and said substrate current supply contact are adapted for providing a predetermined current density in each electrochemical cell.

Description

Master electrode and its formation method {MASTER ELECTRODE AND METHOD OF FORMING IT}

The present invention relates to a master electrode and a method of forming the master electrode. The master electrode is usable in an etching and plating method as described in co-pending Swedish patent application No. 0502538-2, filed November 28, 2005 and entitled "METHOD OF FORMING A MULTILAYER STRUCTURE". The contents of this specification are incorporated herein by reference. The master electrode is similar to the master electrode described in co-pending Swedish patent application No. 0502539-2, entitled “ELECTRODE AND METHOD OF FORMING THE ELECTRODE”. The contents of this specification are incorporated herein by reference. Master electrodes are suitable for enabling the manufacture of applications comprising micro or nano structures in single or multiple layers. Master electrodes include printed wiring boards (PWBs), printed circuit boards (PCBs), microelectromechanical systems (MEMS), integrated circuits (ICs) interconnects, upper IC interconnects, sensors, flat panel displays, magnetic and optical storage devices, solar It is useful for batteries and other electronic devices. Different types of structures in conductive polymers, structures in semiconductors, structures in metals, and others are possible using this master electrode.

WO 02/103085 relates to the construction of a conductive master electrode for the production of an appliance comprising an electrochemical pattern replication method (ECPR) and micro and nano structures. The etching and plating pattern defined by the master electrode is replicated on the electrically conductive material, the substrate. The master electrode is in close contact with the substrate and the etching / plating pattern is transferred directly onto the substrate by using a contact etching / plating process. The contact etch / plating process is performed in a local electrochemical cell formed in a closed or open cavity between the master electrode and the substrate.

The master electrode is used in cooperation with the substrate on which the structure is to be constructed. The master electrode forms at least one, typically a plurality of electrochemical cells, to which etching or plating is performed.

The master electrode may be constructed of a durable material because the master electrode must be used in multiple etching or plating processes.

The problem is that the etch rate or plating rate may be higher in electrochemical cells located closer to the contact area of the seed layer, such as in a perimeter than in other areas.

This problem occurs when etching and / or plating is performed on a substrate provided with a seed layer that conducts current in the substrate. In the case where the seed layer is thin such that a substantial potential difference occurs across the seed layer, the current density in the electrochemical cell is varied over the surface of the substrate, such that the etching depth or plating height is varied. This problem is exacerbated by the fact that the current density exponentially follows the cell voltage.

It is an object of the present invention to provide a master electrode in which the aforementioned problems are at least partially eliminated or alleviated.

According to an aspect of the invention, a system is provided comprising a master electrode arranged on a substrate, said master electrode having a first surface provided with a plurality of cavities in which a conductive material is arranged, a pattern layer of at least partially insulating material. Wherein the electrode conductive material is electrically connected to at least one electrode current supply contact; The substrate comprises a top surface arranged in contact with or adjacent to the first surface and having a structure and / or conductive material of conductive material arranged thereon, the substrate conductive material electrically connected to at least one current supply contact. Become; A plurality of electrochemical cells are formed to be delimited by the cavity, the substrate conductive material and the electrode conductive material, the cell comprising an electrolyte, the electrode resistance between the electrode conductive material and the electrode current supply contact and The substrate resistance between the substrate conductive material and the substrate current supply contact is adapted to provide a predetermined current density in each electrochemical cell.

In an embodiment, each of the electrode resistance and the substrate resistance may be formed by at least one electrically conductive material having a certain specific conductivity defined as the thickness of the material divided by the resistivity of the material. The specific conductivity can be arranged to vary over the surface of the master electrode. The specific conductivity can be arranged to vary by varying the thickness of the material. The specific conductivity can also be arranged to vary by changing the resistivity of the material. The material may be a doped semiconductor material with doping arranged to vary to provide the resistivity.

In an embodiment, the electrode conductive material can include a disk having a range substantially the same as the first surface. The disk may be made of a conductive and / or semiconductive material. The electrode conductive material may comprise a cavity conductive material arranged within the bottom of each cavity. The cavity conductive material may be a material arranged under the cavity and made of an inert material. The cavity conductive material may be an additional material that is pre-deposited in the cavity and at least partially consumed during the plating process. The cavity conductive material may be in electrical contact with the disk.

In an embodiment, the disk can have a substantially constant thickness. The disk may comprise a plurality of disk members having different specific conductivity, which disk members are arranged on top of each other.

In an embodiment, an electrode supply contact can be arranged in the center of the disk. The electrode supply contact may comprise several discrete contacts. Discrete contacts may include at least one ring contact or ring segment contact arranged radially from the center of the disk. Each discrete contact may be provided with a specific potential during the plating or etching process.

In an embodiment, the disc may be substantially circular. The thickness of at least one of the disk members may vary depending on the distance to the center of the disk.

In an embodiment, the substrate resistance can be provided at least in part by a seed layer arranged on at least a portion of the substrate top surface. Substrate electrode contacts may be arranged in at least a portion of the perimeter of the substrate seed layer. Substrate electrode contacts may be arranged along the perimeter of the substrate seed layer. The substrate electrode contact may comprise several discrete contacts. Each discrete contact may be supplied with a specific potential during the plating and etching process. The master electrode may include at least one contact area in contact with the seed layer to provide current to the seed layer.

In an embodiment, a patterned layer is arranged in the first surface at the portion between the cavities that contacts the substrate conductive material during a plating or etching process to increase the specific conductivity of the substrate conductive material over the area. It may include at least one area of material.

In an embodiment, the potential difference across the surface of the electrode conductive material and / or the surface of the substrate conductive material is significant such that the current density difference of the electrochemical cell between the surfaces is at least 1%, such as at least 2%, Adaptation can be performed. The adaptation may be such that the specific conductivity of the electrode conductive material is on average between 0.1 and 100 times, such as between 0.5 and 20 times the specific conductivity of the substrate conductive material, for example between 1 and 10, such as 1 to 7 times. Can be. Each cavity may be provided with a material having a thickness thicknessed in each cavity.

In another aspect, there is provided a master electrode intended to be arranged on a substrate, the master electrode comprising a pattern layer of at least partially insulating material having a first surface provided with a plurality of cavities in which the conductive material is arranged, The electrode conductive material is electrically connected to at least one electrode current supply contact; A plurality of electrochemical cells are formed to be delimited by the cavity, the electrode conductive material and the substrate; The electrode resistance between the electrode conductive material and the electrode current supply contact is adapted to relate to the substrate conductive material intended to provide a predetermined current in each electrochemical cell to be formed.

In an embodiment, each of the electrode resistance and the substrate resistance may be formed by at least one electrically conductive material having a certain specific conductivity defined as the thickness of the material divided by the resistivity of the material. The specific conductivity can be arranged to vary over the surface of the master electrode. The specific conductivity can be arranged to vary by varying the thickness of the material. The specific conductivity can be arranged to vary by varying the resistivity of the material. The material may be a doped semiconductor material with doping arranged to vary to provide the variable resistivity.

In an embodiment, the electrode conductive material can include a disk having a range substantially the same as the first surface. The disk may be made of a conductive and / or semiconductive material. The electrode conductive material may comprise a cavity conductive material arranged under each cavity. The cavity conductive material may be a material arranged under the cavity and made of an inert material. The cavity conductive material may be an additional material that is pre-deposited in the cavity and at least partially consumed during the plating process. The cavity conductive material may be in electrical contact with the disk.

In an embodiment, the disk has a substantially constant thickness. The disk may comprise a plurality of disk members having different specific conductivity, which disk members are arranged on top of each other. An electrode supply contact can be arranged in the center of the disk. The electrode supply contact may comprise several discrete contacts. The discrete contacts may include at least one ring contact or ring segment contact arranged radially from the center of the disk. The discrete contacts may be provided with a specific potential during the plating or etching process.

In an embodiment, the disc may be substantially circular. The thickness of at least one of the disk members may vary depending on the distance to the center of the disk. Each cavity may be provided with a material having a thickness specific to each cavity.

In an additional aspect, a material layer in the cavity of the master electrode has a patterned layer comprising an insulating material from which the cavity is formed, and a conductive electrode layer having a bottom portion of the cavity and contact portions for external connection to a power source. A deposition method is provided, the method comprising: arranging a conductive member on a support; Arranging the master electrode on the contact member to achieve electrical contact between the conductive electrode layer and the contact member in at least two contact portions; Arranging an electroplating anode of material to be deposited in the cavity on the master electrode, wherein the electrochemical cell is formed to be delimited by the cavity, the substrate conductive electrode layer and the electroplating anode, An electroplating anode arrangement, wherein the cell comprises an electrolyte; The conductive electrode layer being a cathode from the anode by connecting a power source to the electroplating anode and the contact member to deposit the material in the cavity on top of the conductive electrode layer and passing current through the electrochemical cell. To deliver the material to the device.

In an additional aspect, a method of performing etching or plating of a substrate by a master electrode is provided, wherein the master electrode has a first surface provided with a plurality of cavities in which a conductive material is arranged, the pattern layer of at least partially insulating material Wherein the electrode conductive material is electrically connected to at least one electrode current supply contact, the method comprising: arranging the master electrode on a support; Supplying an electrolyte to the cavity; Arranging a substrate on said master electrode, said substrate comprising a top surface having a structure of conductive material and / or conductive material arranged thereon, said substrate conductive material electrically contacting at least one current supply contact; Connected, wherein an electrochemical cell is formed to be delimited by the cavity, the substrate conductive electrode layer and the electrode conductive material, the cell comprising an electrolyte; Connecting a power source to the electrode current supply contact and the substrate current supply contact to pass a current through the electrochemical cell to allow a current to pass between the master electrode and the substrate, the method comprising: Selecting a master electrode, wherein the specific resistivity of the master electrode is adapted to the substrate conductive material.

Additional objects, features and advantages of the invention will appear from the following detailed description of several embodiments with reference to the drawings.

1 (a) to 1 (d) are schematic cross-sectional views of various method steps when forming a master electrode from a conductive or semiconductive carrier.

2 (a) to 2 (d) are schematic cross-sectional views of various method steps in forming a master electrode from a non-conductive carrier.

3 (a) to 3 (e) are schematic cross-sectional views of various method steps in forming a master electrode from a conductive carrier having a conductive layer added in a pattern.

4 (a) to 4 (e) are schematic cross-sectional views of various method steps in forming a master electrode having a pattern arranged in a carrier.

5 is a schematic cross-sectional view of a master electrode with a deep patterned cell;

6 (a) to 6 (c) are schematic cross-sectional views of various method steps in forming a master electrode having an insulating pattern layer bonded to an adhesive layer.

Fig. 7 (a) and a schematic cross sectional view of a master electrode applied on a large substrate, and Fig. 7 (b) is a top view thereof.

Fig. 7 (c) is a schematic cross sectional view of a master electrode provided with one or several recesses, and Figs. 7 (d) and 7 (e) are top views thereof.

7 (f) to 7 (i) are schematic cross sectional views of a master electrode provided with a contact area to a substrate;

8 (a) to 8 (b) show the potential distribution in the master electrode and seed layer in one embodiment, and FIG. 8 (c) shows the current distribution.

9 (a) and 9 (b) show potential distributions in the master electrode and seed layer in another embodiment, and Fig. 9 (c) shows the current distribution.

10 (a) and 10 (b) show the potential and current distributions in the seed layer in another embodiment.

11 (a) and 11 (b) show a potential distribution of the master electrode and seed layer in another embodiment, and FIG. 11 (c) shows a current distribution.

12 is an enlarged cross sectional view of a conductive pathway in various electrochemical cells.

13 (a) and 13 (b) are sectional views in which the substrate is concave from the beginning;

Figures 14 (a) and 14 (b) are cross sectional views similar to Figures 13 (a) and 13 (b), with the substrate convex from the beginning;

15A to 15E are schematic cross-sectional views of an embodiment of a master electrode provided with a three-dimensional cavity in a pattern layer.

16 (a) to 16 (c) are schematic cross-sectional views of another embodiment of a master electrode provided with a three-dimensional cavity in a pattern layer.

17 (a) and 17 (b) are schematic cross-sectional views of embodiments of master electrodes having cavities of different depths with non-uniform distribution of pre-deposited material.

18 (a) and 18 (b) are schematic cross-sectional views of another embodiment of a master electrode having a cavity having a non-uniform distribution of pre-deposited material.

Fig. 19 (a) is a schematic cross sectional view showing a master electrode having various contact portions, and Fig. 19 (b) is a plan view of the master electrode of Fig. 19 (a).

20 (a) and 20 (b) and 21 (a) and 21 (b) are schematic cross-sectional views showing electrochemical cell and current distributions in polar and linear models, respectively.

In the following, several embodiments of the present invention will be described with reference to the drawings. These embodiments are described for the purpose of description to enable those skilled in the art to practice the invention and to initiate the best mode. However, such embodiments do not limit the invention, and other combinations of different features are possible within the scope of the invention.

When etching and / or plating is performed on a substrate provided with a seed layer that conducts current in the substrate, a significant potential difference occurs across the seed layer. This is especially true when the seed layer is thin and the etch / plating current is high. If there is at least about 1% potential difference across the electrochemical cell as a result of the potential difference across the surface of the seed layer, the current density of the electrochemical cell varies to such an extent that a height difference can be observed in the etched / plated structure formed. Will be. This problem is compounded by the fact that the current density in the electrochemical cell exponentially follows the cell voltage. A 1% change in cell voltage results in a larger change in the height of the structure.

This problem is compounded by the thin seed layer on the substrate. In this specification, the concept of a specific conductance, which is the thickness h of the conductive layer divided by its resistivity ρ, will be used. In the case of a copper layer with a thickness of less than 1 μm, this problem may exist. Such thin layers have a specific conductivity of about 58 Ω ⁻¹ .

This phenomenon was observed when the specific conductivity was 1000 Ω ^{- 1} or less, such as about 100 Ω ^-1 or less, for example 20 Ω ^{- 1} or less.

This observation was made at current densities between about 0.1 A / dm ² and 100 A / dm ² .

The problem is also different for different contact geometries. In a substrate, the seed layer can often be contacted only at the perimeter of the substrate. If the substrate can be contacted elsewhere, for example through vias, the potential difference can be eliminated or reduced.

Often, conductive structures in the substrate help to increase the specific conductivity, thereby reducing this problem.

In the following, some embodiments are provided to reduce this problem. Thus, the master electrode used to form the electrochemical cell is designed to mimic to some extent the potential difference across the electrochemical cell.

This can be done by various means in the master electrode.

The specific conductivity of the master electrode can be adapted to the conductivity of the conductive layer of the substrate. Thus, the specific conductivity of the master electrode should be from about 0.1 to 100 times, such as between 0.5 and 20 times and between 1 and 10 times the specific conductivity of the conductive layer of the substrate.

In polar geometries where the thin seed layer of the substrate is contacted over the perimeter of the seed layer and the master electrode is contacted at the center, the specific conductivity of the master electrode is about 3 to 8 times the specific conductivity of the conductive layer of the substrate, eg For example, it should be about 1 to 10 times, such as about 5 to 7 times.

In a linear geometry in which the thin seed layer of the substrate is contacted over one side of the seed layer and the master electrode is contacted over the other side, the specific conductivity of the master electrode is from 0.5 to 5 times the specific conductivity of the conductive layer of the substrate, for example For example, from about 0.2 to 10 times, such as from about 0.8 to 1.2 times.

The specific conductivity of the master electrode can vary over the substrate, which can be achieved by varying the thickness of the conductive material or varying the resistivity of the material. The resistivity can be varied, for example, by having a semiconductive material, such as silicon, which is doped to varying degrees across the substrate. The doping rate determines the resistivity.

In a substantially central or polar layout where the master electrode is contacted at the center, the specific conductivity can be high at the center and reduced towards the perimeter.

Another means to solve the problem is to provide a master electrode having several contact portions across the substrate and to supply the contact portions with voltages of different potentials that mimic the current density distribution in the substrate. In this way, the potential difference across the electrochemical cell can be less than the variation across the surface of the substrate.

By combining the varying specific conductivity of the master electrode and the use of several contact portions, the current density in each cell can be controlled.

In some embodiments, it is desirable to have a variable current density over the surface of the substrate. In this situation, the variable or adapted specific conductivity of the master electrode conductive material and the use of various contact portions can be combined to achieve the desired current distribution.

The master electrode is adapted to the expected substrate conditions. However, during plating with predeposited anode material in the cavity, predeposition can occur by electrochemical deposition from an electroplating anode, such as an anode plate, an anode disc or an anode ball. In the case where the electrode conductive material has low conductivity, especially if the anode is thick and very conductive, there is a risk of less predeposition in the cavity away from the central contact portion of the master electrode. To neutralize this phenomenon, the master electrode can be provided with several contacts or the master electrode can be made contactable over a larger area, thereby reducing the difference in predeposition rate. Thus, certain contact portions can be used for predeposition and other contact portions can be used for the plating process.

The current density of each electrochemical cell depends on the difference between the anode and the cathode. This is especially the case when the conductivity of the electrolyte used in the electrochemical cell is low or the current density is high, such as close to the limiting current. Thus, the current density distribution between the electrochemical cells can be controlled by the thickness of the material in each cell.

The aforementioned principle can be implemented in the above-described master electrode. In the following, some general precautions regarding the master electrode and the method of forming the master electrode are provided. Several methods of forming a master electrode that can be used to create one or multiple layers of a structure of one or multiple materials, including using the electrochemical pattern replication (ECPR) technique described below, are described. The method generally comprises forming a master electrode in at least a portion comprising a carrier that is conductive / semiconductive; Forming a conductive electrode layer that functions as an anode in ECPR plating and a cathode in ECPR etching; And forming an insulating pattern layer defining a cavity in which ECPR etching or plating can occur in the ECPR process, in a manner that enables electrical contact from the external power source to the conductive portion and / or conductive electrode layer of the carrier. .

The master electrode includes at least one cavity that forms an electrochemical cell. Although there may be a single cell, typically a large number of cells are used. Thus, the surface of the master electrode can be considered to have a cell density of, for example, 1% to 50%, which means that the cavity occupies 1% to 50% of the total surface of the master electrode. The master electrode can have lateral dimensions of tens or hundreds of millimeters, up to thousands of millimeters, and the cavity can be micrometer or nanometer size.

The master electrode has three steps, namely

a) contacting the master electrode with a substrate, such as a seed layer, to form a multielectrochemical cell;

b) forming a structure in the seed layer by etching or forming a structure on the seed layer by plating; And

c) will be used to create one or multiple structural layers using electrochemical pattern replication (ECPR) techniques comprising separating the master electrode from the substrate.

In a first step (a), a master electrode comprising an electrically conductive electrode layer and an insulating pattern layer of at least one material of a pre-deposited anode material, typically inert, such as platinum or gold, is formed of an electrolyte When present, it is in physical proximity with the conductive top layer or seed layer of the substrate. In this way, an electrochemical cell is formed and filled with electrolyte. The cell is defined by a cavity of an insulating structure on the master electrode, a conductive electrode layer of the master electrode or a pre-deposited anode material and a conductive top layer of the substrate.

The seed layer may comprise Ru, Os, Hf, Re, Rh, Cr, Au, Ag, Cu, Pd, Pt, Sn, Ta, Ti, Ni, Al, alloys of these materials, Si, W, TiN, TiW, NiB, NiP, NiCo, NiBW, NiM-P, W, TaN, Wo, Co, CoReP, CoP, CoWP, other materials such as CoWB, conductive polymers such as polyaniline, Monel, SnPb, SnAg, Solder materials such as SnAgCu, SnCu, and / or combinations thereof. The seed layer of the substrate is cleaned and activated prior to use in the ECPR process. Cleaning methods include organic solvents such as acetone or alcohols; And / or the use of inorganic solvents such as nitric acid, sulfonic acid, phosphoric acid, hydrochloric acid, acetic acid, hydrofluoric acid, strong oxidizing agents such as peroxide, persulfate, ferric chloride, and / or deionized water. It may include. Cleaning may also be performed by applying oxygen plasma, argon plasma and / or hydrogen plasma or mechanically removing impurities. Activation of the seed layer surface can be achieved by removing oxides, for example sulfonic acid, nitric acid, hydrochloric acid, hydrofluoric acid, phosphoric acid and etchant, for example sodium-persulfate, ammonium-persulfate, hydrogen -Peroxides, ferric chloride and / or other solutions containing oxidants.

Intimate the master electrode with the top layer on the substrate includes aligning the master electrode insulation pattern with the patterned layer on the substrate. This step can include using an alignment mark on the front side or the back side of the master electrode that can be aligned with the corresponding alignment mark on the substrate. The alignment procedure can be performed before or after applying the electrolyte. The pre-deposited anode material may be prearranged on the conductive electrode layer in the cavity of the insulating pattern layer before bringing the master into contact with the substrate. The predeposited anode material in the master electrode cavity may be pre-cleaned and activated in the same manner as described for the substrate seed layer before bringing the master electrode into contact with the substrate.

The electrolyte comprises a solution of cations and anions suitable for electrochemical etching and / or plating, such as conventional electroplating baths. For example, when the ECPR etching or plating structure is copper, a copper sulphate bath can be used, such as an acidic copper sulphate bath. The acidity may be pH <4, such as between pH = 2 and pH = 4. In some embodiments, additives such as inhibitors, levelers and / or promoters such as PEG (poly-ethylene glycol) and chloride ions and / or SPS (bis (3-sulfopropyl disulfide) may be used. In another embodiment, Watt's bath may be used when the ECPR etch or plating structure is Ni. Suitable electrolyte systems for different materials of the ECPR etch or plating structure are described in Electroplating Engineering Handbook, et al., Lawrence J. Durney, et al. 4th ed. (1984).

In a second step (b), the structure of the conductive material is the seed layer on the master electrode and the substrate to simultaneously produce an electrochemical cell inside each of the electrochemical cells defined by the upper layer on the substrate and the cavity of the master electrode. It is formed using ECPR etching or plating by applying a voltage using an external power source.

When a voltage is applied in such a manner that the seed layer on the substrate is the anode and the conductive electrode layer in the master electrode is the cathode, the seed layer material is dissolved and at the same time the material is deposited inside the cavity of the master electrode. Grooves produced by dissolving the seed layer separate the remaining structure of the seed layer. The structure formed from the remaining seed layer is a negative image of the cavity of the insulating pattern layer of the master electrode; Such a structure is referred to hereinafter as an "ECPR etch structure".

When a voltage is applied in such a way that the conductive electrode layer in the master electrode is an anode and the seed layer of the substrate is a cathode, the pre-deposited anode material inside the cavity of the master electrode dissolves, while the material is filled with an electrolyte on the substrate in the cavity Deposited on the conductive layer. The material deposited on the conductive layer on the substrate forms a structure that is a positive image of the cavity of the insulating pattern layer of the master electrode; This structure is referred to herein as "ECPR plating structure".

The ECPR etch or ECPR plating structure may be made of a metal or alloy, for example Au, Ag, Ni, Cu, Sn, Pb and SnAg, SnAgCu, AgCu and / or a combination thereof, for example Cu.

In one embodiment, the anode material is pre-deposited in the cavity of the master electrode by using ECPR etching of the anode material and depositing the material on the cathode conductive electrode in the cavity of the insulating pattern layer of the master electrode. In another embodiment, the anode material selectively electroplats, electroless plating, immersion plating, CVD, MOCVD, (charged) powder on the conductive electrode layer selectively in the cavity of the insulating pattern layer of the master electrode. Predeposited by coating, chemical grafting and / or electrografting.

The voltage can be applied in a manner that improves the uniformity and / or properties of the etch and / or plating structure. The applied voltage may be a DC voltage, a pulsed voltage, a square pulsed voltage, a pulse inversion voltage and / or a combination thereof.

Uniformity of the etch and / or plating structure may be increased by selecting an optimized combination of applied voltage waveforms, amplitudes and frequencies. Etch depth or plating height can be controlled by monitoring the current and time passing through the master electrode. If the total electrode area is known, the current density can be estimated from the current passing through the electrode area. Since the current density corresponds to the etching or plating rate, the etching depth and plating height can be predicted from the etching or plating rate and time.

In some embodiments, the etching or plating process is stopped by blocking the applied voltage before reaching the underlying surface of the dissolving anode material. In the case of an etching process, this means that the process still remains underneath the etched grooves in the seed layer, stopping when it covers the underlying substrate layer. Otherwise, there is a risk that the electrical connection with any part of the seed layer may be broken. In the case of a plating process, this means that the process is still interrupted when the layer of predeposited anode material still remains, such as 5% to 50%, covering the conductive electrode layer. Otherwise, a nonuniform current distribution can occur in each electrochemical cell.

In some embodiments, the desired height of the plating structure is significantly less than the thickness of the predeposited anode material. This means that several structural layers can be plated on one or several substrates before depositing a new anode material. In some examples, the height of the pre-deposited material may be at least twice as thick as the height of the plated structure.

In some embodiments, multiple layers of ECPR plating structures are deposited directly on each other.

In a third step (c), after the ECPR etching or plating structure is formed, the master is separated from the substrate in a manner that minimizes damage on the ECPR etching or plating structure or the master on the substrate. The method can be performed by holding the substrate in a fixed position and moving the master electrode in a direction perpendicular to the substrate surface, or by holding the master electrode in a fixed position and moving the substrate in a direction perpendicular to the master electrode surface. . In other embodiments, separation may be performed in a less parallel manner to facilitate the separation. After the ECPR etch or plating step, the remaining material deposited inside the cavity of the master electrode can be removed using a removal method that includes applying a wet etch chemical suitable to dissolve the remaining material. Anisotropic etching methods may also be used with dry etching methods such as, for example, ion-sputtering, reactive-ion etching (RIE), plasma-assisted-etching, laser-ablation, ion-milling. In some embodiments, the removal method comprises a combination of dry etching and wet etching methods. The remaining material may in some embodiments also be removed by regular plating and / or ECPR plating, respectively, on any cathode and / or dummy substrate. In some embodiments, this is done before using the master electrode in another ECPR etch step, or prior to predeposition of new material into the cavity of the master used for the ECPR plating step. Alternatively, in the case of multiple procedures, during plating, only a portion of the pre-deposited material may be used in a single procedure and another portion of the pre-deposited material may be used in the next procedure. Alternatively, during etching, the material deposited on the cathode, ie, the master electrode, need not be removed between each procedure, but may be removed between each second, third, etc. procedure.

Three embodiments of a method of forming a master electrode include the following steps:

1. Supplying an Insulated or Conductive / Semiconductive Carrier

2. applying a conductive electrode layer on at least a portion of the carrier

3. applying an insulating pattern layer on at least a portion of the conductive electrode layer

or

1. Supplying an Insulated or Conductive / Semiconductive Carrier

2. applying an insulating pattern layer on at least a portion of the carrier

3. Applying a conductive electrode layer on selected portions of the carrier not covered by the insulating pattern layer

or

1. Supplying or patterning conductive / semiconductive carriers

2. applying an insulating pattern layer on at least a portion of the patterned carrier

3. applying a conductive electrode layer into a selected portion of the patterned carrier not covered by the insulating pattern layer.

Materials used for the portion of the master electrode exposed to the chemical and / or electrochemical environment during ECPR etching, ECPR plating, predeposition, cleaning and / or removal methods are generally resistant to dissolution and oxidation in the chemical and / or electrochemical environment. Tolerant

In one embodiment, the conductive electrode layer is applied onto the carrier and the insulating pattern layer is applied onto the conductive electrode layer.

In another embodiment, the insulating pattern layer is applied onto the carrier, and the conductive electrode layer is applied onto at least a portion of the carrier inside the cavity of the insulating pattern layer.

In another embodiment, a recess is created in the carrier and the insulating pattern layer is applied in an area of the carrier where no recess is provided, while the conductive electrode layer is formed of a recess not covered by the insulating pattern layer. Applied on a wall or on a carrier below it.

The carrier comprises at least one conductive / semiconductive material; Or one or several layers of at least one conductive / semiconductive material and at least one insulating material layer.

The layer of the carrier may be flexible and / or rigid and / or may be a combination of flexible or rigid layers. In some embodiments, the carrier does not bend significantly down into the cavity of the insulating pattern when applying the force required to bring the master electrode into contact with the substrate, thereby allowing the carrier and substrate to intersect during ECPR etching and / or ECPR plating. It is rigid enough to avoid shorting contacts. For example, the distance at which the carrier bends downward when applying the required pressure should be less than 50% of the height of the cavity, such as less than 10%, such as less than 1%, such as 25%. In one embodiment, the carrier is flexible enough to compensate for bending and non-uniformity of the substrate when a force is applied to bring the master into contact with the substrate during ECPR etching and / or ECPR plating. In some cases, the carrier is at least as flexible as the substrate. For example, the substrate can be a glass, quartz or silicon wafer. In this example, the master electrode carrier may have the same or higher flexibility than glass, quartz or silicon wafers, respectively.

Conductive / semiconductive materials include conductive polymers, conductive pastes, metals, Fe, Cu, Au, Ag, Pt, Si, SiC, Sn, Pd, Pt, Co, Ti, Ni, Cr, Al, indium-tin-oxides ( ITO), SiGe, GaAs, InP, Ru, Ir, Re, Hf, Os, Rh, Alloy, Phosphorus Alloy, SnAg, PbAg, SnAgCu, NiP, AuCu, Silicide, Stainless Steel, Brass, Conductive Polymer, Solder Material and its It can be made of the same material as the combination. Insulation layers are oxides such as SiO ₂ , Al ₂ O ₃ , TiO ₂ , quartz, glass, nitrides such as SiN, polymers, polyimides, polyurethanes, epoxy polymers, acrylate polymers, PDMS, (natural) rubber, silicone, Lacquers, elastomers, nitrile rubber, EPDM, neoprene, PFTE, parylene, and / or other materials used in the insulating patterns described below.

In one embodiment, the carrier comprises a conductive / semiconductive disk covered by at least a portion of the coating of insulating material. An insulating material coating can be applied to cover all portions of the conductive / semiconductive disc except for the central portion on the front side and the back side. Insulation material coding includes thermal-oxidation, plasma-enhanced-chemical-vapor deposition (PECVD), physical vapor deposition (PVD), chemical-vapor-deposition (CVD), frame hydrolysis deposition (FHD), electrical anodization, atomic- It may be applied by methods such as layer-deposition (ALD), spin-coating, spray-coating, roller-coating, powder-coating, adhesive taping, pyrolysis, bonding by other suitable coating techniques and / or combinations thereof. An insulating material coating may optionally be applied by applying to the intended portion of the conductive / semiconductive disk or to the entire conductive / semiconductive disk prior to removing the portion of the insulating material coating in the selected area. For example, the insulating material coating may be removed by an etching method such as using an etch-mask to protect an area where the insulating material coating should not be damaged and / or using a mechanical removal method.

The etching method may be a wet etching and / or dry etching method. Wet etching is performed by adding a liquid chemical that dissolves the material to be etched, which often includes a strong oxidizing chemical such as a strong acid. For example, buffered, diluted or concentrated hydrofluoric acid can be used to etch SiO ₂ . The dry etching method may include a method such as ion-sputtering, reactive-ion-etching (RIE), plasma-assisted-etching, laser-ablation, ion-milling. The pattern of etch-masks may be produced by lithographic methods such as photolithography, laser lithography, E-beam lithography, nanoimprinting and / or other lithography processes suitable for patterning etch-masks. The etch-mask may be a polymer material, for example, a resistor used in the lithographic method such as thin film photoresist, polyimide, BCB, and / or thick film resistor. The etch-mask may also be a hard-mask including materials such as SiN, SiC, SiO ₂ , Pt, Ti, TiW, TiN, Al, Cr, Au, Ni, other hard materials, and combinations thereof. The hard-mask is patterned by the lithographic method prior to etching the hard-mask selectively in areas not covered by the patterned lithographic mask. The mechanical removal method may include grinding, grinding, drilling, ablation, (sand or fluid) blasting and / or combinations thereof.

In yet another embodiment, the carrier comprises an insulating disk at least in part of which is a conductive / semiconductive material. In this case, the conductive / semiconductive portion can be applied to the center of the insulating disk. In one embodiment, the carrier is formed by creating a cavity in the disk of insulating material in the selected area and applying conductive / semiconductive material to the cavity. The cavity in the insulating disk may be formed by the wet etching method, the dry etching method and / or the mechanical removal method. The etch-mask may be used in a method of creating a cavity and may be patterned by the lithographic method. The method of applying the conductive / semiconductive material in the cavity may be PVD, CVD, sputtering, electroless deposition, immersion deposition, electrodeposition, mechanical placement, soldering, gluing, other suitable deposition methods and / or combinations thereof. Can be. In some embodiments, a planarization step may be performed on the carrier to increase flatness and reduce surface roughness.

The conductive electrode layer may consist of one or several layers of conductive / semiconductive material. For example, the conductive electrode layer may include Fe, Cu, Sn, Ag, Au, Pd, Co, Ti, Ta, Ni, Pt, Cr, Al, W, ITO, Si, Ru, Rh, Re, Os, Hf, Other metals, alloys, phosphorus-alloys, SnAg, SnAgCu, CoWP, CoWB, CoWBP, NiP, AuCu, silicides, graphite, stainless steel, conductive polymers, solder materials and / or combinations thereof. The conductive electrode layer may be, for example, ALD, metalorganic-chemical-vapor-deposition (MOCVD), PVD, CVD, sputtering, electroless deposition, immersion deposition, electrodeposition, electro-grafting, other suitable deposition methods and / or combinations thereof. It can be applied to the carrier by the method. In some embodiments, the conductive electrode layer is selectively onto a conductive / semiconductive surface using methods such as electroless deposition, electrodeposition, immersion deposition, electrografting, chemical grafting, selective CVD, and / or selective MOCVD. Can be deposited.

In some embodiments, the conductive electrode layer is processed by a thermal method. The thermal method may be performed in a gas environment with high vacuum, forming gas, hydrogen gas, nitrogen gas, low oxygen content, and / or combinations thereof. The thermal method may be annealing (eg, high speed-heat-annealing (RTA)), furnace treatment, hot-plate treatment and / or combinations thereof. The thermal method in some embodiments improves the adhesion between the conductive electrode layer and the carrier by reducing contact resistance and / or internal stress to the carrier, and / or the electrical properties of the master electrode (such as hardness and / or wear resistance). And / or improve mechanical properties. In some embodiments, the conductive electrode layer is formed by applying at least one layer of at least one material and treating the at least one layer by the thermal method before applying the next layer.

In one embodiment, an adhesive layer is applied onto at least a portion of the carrier prior to applying the conductive electrode layer. The adhesive layer may be made of a material or various materials that increase the adhesion of the conductive electrode layer to the carrier. The adhesive layer may be a conductive material such as Pt, Al, Ni, Pd, Cr, Ti, TiW or AP-3000 (Dow Chemicals), AP-100 (Silicon Resources), AP-200 (Silicon Resources), or AP-300 (Silicon). Insulating material such as Resources, silane such as HMDS, and / or combinations thereof. If necessary, the adhesive layer does not cover all areas of the carrier to enable electrical connection to the carrier, such as when the adhesive layer is insulating. Alternatively, the adhesive layer is applied to cover the entire carrier, and then a portion is removed from the area, for example, the center of the front side, in which an electrical connection between the conductive electrode layer and the carrier is required. The adhesive layer may in some embodiments also function as a catalyst layer to facilitate or improve the deposition of the conductive electrode layer. The adhesive layer may be electrodeposited, spin-coated, spray-coated, dip-coated, molecular-vapor-deposition (MVD), ALD, MOCVD, CVD, PVD, sputtering, electroless deposition, immersion deposition, electrografting, chemical It can be applied by using other deposition methods suitable for rafting and / or adhesive materials.

The insulating pattern layer may be made of one or several layers of patterned electrically insulating material. The insulating pattern layer may be applied in a manner that provides a layer of low surface roughness and high thickness uniformity of the layer. In some embodiments, the insulating pattern layer may be thermally oxidized, thermally nitrided, PECVD, PVD, CVD, flame hydrolysis deposition (FHD), MOCVD, electrochemical anodization, ALD, spin-coating, spray-coating, dip-coating, And may be applied using methods such as curtain-coating, roller-coating, powder-coating, pyrolysis, adhesive taping, bonding, other deposition techniques, and / or combinations thereof.

In one embodiment, an adhesive layer is applied before applying the insulating pattern layer onto the carrier. The adhesive layer may include at least one layer of at least one material that improves adhesive properties between the insulating pattern layer and the surface of the carrier. The adhesive layer may be made of an insulating or conductive material. The adhesive layer may include, for example, PT, Ni, Al, Cr, Ti, TiW, Dow Chemicals (AP-3000), Silicon Resources (AP-100), Silicon Resources (AP-200), and Silicon Resources (AP-300). ), A silane such as HMDS, a bottom anti-reflective-coating (BARC) material, and / or combinations thereof. The adhesive layer can be applied using methods such as PECVD, PVD, CVD, MOCVD, ALD, spin-coating, spray-coating, roller-coating, powder-coating and / or combinations thereof.

In some embodiments, a planarization step may be performed on the applied insulating pattern layer to achieve a flatter surface. The planarization step may be performed before patterning the insulating pattern layer. The planarization method may be an etching and / or polishing method such as chemical-mechanical-polishing (CMP), lapping, contact planarization (CP) and / or ion-sputtering, reactive-ion-etching (RIE), plasma-assisted-etching Dry etching methods such as laser-ablation, ion-milling, and / or other planarization methods and / or combinations thereof.

The insulating pattern layer may consist of organic compounds such as polymers, as well as insulating inorganic compounds such as oxides and / or nitrides. The polymeric materials used are, for example, polyimides, siloxane modified polyimides, BCB, SU-8, polytetrafluoroethylene (PTFE), silicones, elastomeric polymers, E-beam resists (such as ZEP (Sumitomo)) E-beam resist), photoresist, thin film resist, thick film resist, polycyclic olefin, polynovorene, polyethene, polycarbonate, PMMA, BARC material, lift-off-layer (LOL) Materials, PDMS, Polyurethanes, Epoxy Polymers, Fluoroelastomers, Acrylate Polymers, (Natural) Rubbers, Silicones, Lacquers, Nitrile Rubbers, EPDM, Neroprene, PFTE, Parylene, Fluoromethylene, Cyanate Ester, Inorganic- Organic hybrid polymers, (fluorinated or hydrated) amorphous carbon, other polymers, and / or combinations thereof. The inorganic compounds used are, for example, organic doped silicon glass (OSG), fluorine doped silicon glass (FSG), PFTE / silicon compounds, tetraethylorthosilicate (TEOS), SiN, SiO ₂ , SiON, SiOC, SiCN : H, SiOCH material, SiCH material, silicate, slica-based material, silsesquioxane (SSQ) -based material, methyl-silsesquioxane (MSQ), hydrogen-silsesquioxane (HSQ), TiO ₂ , Al ₂ O ₃ , TiN and combinations thereof. The insulating pattern layer material facilitates the patterning process (lithography and / or etching), adheres well to the underlying layer, has good mechanical durability, and / or has an ECPR process and / or intermediate cleaning and / or removal It may have inert properties during the step.

In some embodiments, the pattern (cavity) of the insulating pattern layer is manufactured using methods such as lithography and / or etching. The lithographic method may include photolithography, UV-lithography, laser-lithography, electron-beam (E-beam) lithography, nanoimprint, other lithographic methods, and / or combinations thereof.

The insulating pattern layer may have a different height depending on the desired size and height of the ECPR etched or plated structure. In some embodiments, the insulating pattern layer can have a thickness of up to several hundred microns. In other embodiments, the insulating pattern layer may be thin down to 20 nm. In some embodiments, the height / width ratio of the cavity is less than 10, such as less than about 5, for example less than about 2, such as less than about 1. In some embodiments, such as top-IC applications, the insulating pattern layer is less than about 15 μm, such as less than about 50 μm, for example less than about 5 μm, and the aspect ratio is less than about 5, eg, about 1 Less than 2, such as less than. In some embodiments, such as IC interconnect applications, the insulating pattern layer is less than about 2 μm, such as for IP interconnect global wiring, such as less than 500 nm, such as for IC interconnect intermediate wiring, for example, IC Less than about 100 nm, such as for interconnect "metal 1" wiring, eg, less than 200 nm, such as less than about 50 nm, such as for IC interconnect "metal 1" wiring. Since there is no forced convection inside the electrochemical cell, the limiting maximum current and thus the maximum plating / etching rate is determined by the distance between the electrodes, ie the height of the insulating pattern layer and the properties of the electrolyte. Higher limiting currents are achieved using electrolytes that contain higher ion concentrations of materials that are electrochemically etched or deposited. Moreover, the shorter the distance between the seed layer of the substrate and the conductive electrode layer, the higher the limit current. However, short distances, ie thin insulating pattern layers, increase the risk of short circuits. The thickness of the structural layer to be formed may be less than about 90%, for example less than about 10%, of the insulating layer thickness, such as less than about 50%.

The etching method includes using an etch-mask and / or using a mechanical removal method to protect an area where the insulating pattern layer should not be damaged. Etching methods may include dry etching and / or wet etching, such as ion-sputtering, reactive-ion-etching (RIE), plasma-assisted-etching, laser-ablation, ion-milling. The pattern of etch-masks can be generated by the lithographic method. The etch-mask may be a polymer resist used in the lithographic method, such as thin film photoresist, polyimide, BCB, thick film resist, and / or other polymers. The etch-mask also includes materials such as SiN, SiO ₂ , SiC, Pt, Ti, TiW, TiN, Al, Cr, Au, Cu, Ni, Ag, NiP, other hard materials, alloys thereof and / or combinations thereof. Can be a hard-mask. The hard-mask may be applied by methods such as PVD, CVD, MOCVD, sputtering, electroless deposition, immersion deposition, electrodeposition, PECVD, ALD, other suitable deposition methods, and / or combinations thereof. The hard-mask is patterned by the lithographic method prior to etching the hard-mask selectively in an area not covered by the patterned lithography mask, using the wet and / or dry etching method in some embodiments.

In some embodiments, the hard-mask is, for example, when the material used for the hard-mask is Cu, Ni, NiFe, NiP, Au, Ag, Sn, Pb, SnAg, SnAgCu, SnPb and / or combinations thereof. At least one layer of an ECPR etch or plating structure. In this case, the insulating pattern layer of the master electrode can be patterned by using another master electrode in conjunction with the above etching method, and no other lithography method may be required.

In some embodiments, the etch-stop layer is applied before applying the insulating pattern layer. The etch-stop layer stops or slows down the etch process by including at least one layer of one or several materials that are less affected by the etching process than the insulating pattern layer, so that when etching passes through the insulating pattern layer, Protect the layers laid on it. The etch-stop layer comprises Ti, Pt, Au, Ag, Cr, Tiw, SiN, Ni, Si, SiC, SiO ₂ , Al, InGaP, CoP, CoWP, NiP, NiPCo, AuCo, BLOk ^™ (Applied Materials) and Other materials and / or combinations thereof which are less affected by the same etching method.

In one embodiment, the patterning method may be modified to affect the inclination angle of the sidewalls of the pattern cavity of the insulating pattern layer. The angle of inclination depends on the application of the ECPR etch or plating structure. In some embodiments, near vertical sidewalls (close to a 90 degree angle of inclination between the carrier surface and the sidewalls of the insulating pattern layer, vertical means that this relates to the normal position of the horizontal structure) to achieve certain electrical properties To be used. This means that the sidewall has an angle (inclined angle) to the normal of the electrode surface of less than about 1 °, such as less than about 0.1 °. In another embodiment, a larger tilt angle is used to improve the method of separating the master electrode from the ECPR plated structure without causing damage to either the insulating pattern layer or the ECPR plated structure. Such an angle may be up to about 45, for example up to about 5 °, such as up to 20 °. The separation method can be improved by changing the angle of inclination to be greater than 0 degrees, which means that the cavity of the insulating pattern layer has a larger open area at the top than at the bottom (generally, a "positive slope Is called the angle "). The angle should not be substantially negative.

In some embodiments, by using the lithographic method, the photoresist used to create the insulating pattern layer can have chemical and physical properties that provide vertical sidewalls or positive tilt angles. For example, a negative photoresist such as SU-8 (Microchem), THB (JSR Micro) or an E-beam resist such as ZEP (Sumitomo) can be used to achieve an angle of inclination close to zero. Other positive photoresists and / or other positive photoresists such as AZ ^® AX ^TM , AZ ^® P9200, AZ ^® P4000 (AZ Electronic Materials), ARF resist (JSR Micro), SPR resist (Rohm & Hass Electronic Materials) It can be used to create an insulating pattern layer having an angle. The tilt angle can also be adjusted by changing the parameters of the photolithography method. For example, the inclination angle of the sidewalls can be varied by changing the length of the focal point when exposing the photoresist through the projection lens. In addition, the inclination angle can be varied by changing parameters in the photography patterning method, for example, using a wavelength filter, using an antireflective coating, changing the exposure dose, changing the development time, and using a heat treatment. And / or combinations thereof.

In another embodiment, the etching method used to pattern the insulating pattern layer can be modified to achieve vertical sidewalls or positive tilt angles. For example, certain tilt angles may be referred to as gas composition, platen power (RF power) and / or plasma power (also referred to as coil power) for dry-etch methods such as reactive-ion-etching (RIE). Can be achieved by optimizing The gas composition may include, for example, carbon fluoride, oxygen, hydrogen, chlorine and / or argon. The inclination angle can be controlled by changing the level of polymerization of the passivating substance on the sidewalls. For example, by increasing or decreasing the level of carbon fluoride in the gas composition, the level of polymerization is increased or decreased respectively, so that the angle of inclination is reduced (less vertical) or decreased (more vertical), respectively. In addition, the degree of polymerization can be achieved by increasing the oxygen level which reduces the polymerization and provides a smaller tilt angle and vice versa; And / or by altering the oxygen and / or hydrogen content by increasing the polymerization and increasing the hydrogen level giving a greater tilt angle (less vertical) and vice versa. In some embodiments, the inclination angle is reduced (becomes more vertical) by reducing the coil power while keeping the platen power constant. This increases the sputtering effect, making the sidewalls more vertical when etching the insulating pattern layer. By increasing the coil power instead, the opposite effect can be achieved, whereby the tilt angle becomes larger (less vertical). In another embodiment, the inclination angle is reduced (becomes more vertical) by increasing the platen power while keeping the coil power constant. A larger tilt angle (less vertical) when etching the insulating pattern layer can be achieved by reducing the platen power while keeping the coil power constant.

In yet another embodiment, a damascene process may be used to create a cavity (pattern) of the insulating pattern layer; The damascene process may include applying a sacrificial pattern layer onto a carrier for the first time; Then applying an insulating material to cover the sacrificial pattern layer as well as to fill the cavity of the sacrificial pattern by using the application method described above for the insulating pattern layer; Planarizing the insulating material using the planarization method described above until the sacrificial pattern layer is not covered; And removing the sacrificial pattern layer to form an insulating pattern layer. The sacrificial pattern layer can be formed, for example, by ECPR etching or plating the structural layer or using known lithography and / or etching / plating methods. This alternative patterning method can be used for embodiments that include an insulating pattern layer material that is difficult to pattern directly, for example, by lithography and / or etching methods.

In an embodiment, the insulating pattern layer surface can be treated to improve better separation from the ECPR plating structure. For example, the insulating pattern layer surface may be treated in a manner that provides an anti-sticking effect between the sidewall of the ECPR plating structure and the sidewall of the cavity. This may include coating the insulating pattern layer surface with a release layer that reduces mechanical and chemical bonds to the ECPR plating structure. Such release layers can be applied using spin-coating, spray-coating, CVD, MOCVD, MVD, PVD, and / or combinations thereof. The release layer may be methoxy-silane, chloro-silane, silane such as fluoro-silane, poly-di-methyl-siloxane, poly-ethylene-glycol-siloxane, siloxane such as dimethyl-siloxane oligomer (DMS) and / or Other polymers such as amorphous fluoro-polymers, fluoro-carbons, poly-tetra-fluoro-ethylene (PTFE), cyto-fluoro-polymers and / or combinations thereof.

In one embodiment, the material used for the insulating pattern layer is treated in a manner that has and / or improves the ability of the electrolyte to wet and fill the cavity of the insulating pattern. In one embodiment, at least a portion of the insulating pattern layer material has low surface energy properties and is hydrophilic, ie, has a low contact angle with an aqueous solution. Moreover, some of the insulating pattern layer material can be treated by lowering surface energy and producing hydrophilic surfaces. Such surface treatment methods include, for example, surface treatment with heat treatment, oxygen / nitrogen / argon plasma treatment, surface conversion for anti-sticking (SIRCAS) and / or strong oxidizing agents such as peroxides, persulfates, concentrated acids / bases. Processing and / or combinations thereof. In another embodiment, at least a portion of the insulating pattern layer has a high surface energy and can be treated in a manner to increase the surface energy to make the surface hydrophobic. Such a method may include treatment with a hydrogen plasma. In an embodiment, the insulating pattern layer comprises one or several layers of at least one material having the property that the sidewalls of the cavity of the natural pattern layer become hydrophilic and the insulating pattern layer is hydrophobic on top. The hydrophilic material can be, for example, a polymer (such as photoresist and / or elastomer) and / or combinations thereof that have been treated with SiN, SiO ₂ , oxygen plasma and / or other materials having polar functional molecular groups at the surface. . The hydrophobic material may be a material having non-polar functional molecular groups such as hydrogen terminated polymers, Teflon, fluoro- and chloro-silanes, siloxanes, fluoro-elastomers and / or combinations thereof.

In another embodiment, the insulating pattern layer is one or several layers of at least one material that improves mechanical contact between the seed layer surface of the substrate and the top of the insulating pattern layer surface when a master electrode is pressed against the seed layer. Can have As mentioned above, the insulating pattern layer may be made of at least one layer of flexible material, such as an elastomer. In one embodiment, the insulating pattern layer comprises at least one layer of rigid material and at least one layer of the elastomeric material. The layer of elastomeric material may be applied on top of the layer of rigid material. The elastomer layer has high compressibility and / or elastic properties; Is electrically insulating and / or has low dielectric properties; Have good chemical resistance to the environment used in the ECPR process and / or intermediate cleaning and / or removal steps, for example to the electrolyte; Applied by methods such as PECVD, PVD, CVD, MOCVD, ALD, spin-coating, spray-coating, roller-coating, powder-coating, pyrolysis and / or combinations thereof; Has strong adhesion to underlying layers such as metals, silicon, glass, oxides, nitrides and / or polymers; Have a high resistance to the environment used in the ECPR process, for example shrinkage and swelling in the electrolyte and / or over time; Non-bleeding, ie without releasing contaminating organic compounds; Sensitive to UV-light; Patterned by lithographic method; Transparent; Patterning may be performed using the etching method, for example the dry-etching method. In some embodiments, the elastomer is poly-di-methyl-siloxane (PDMS), silicone, epoxy-silicone, fluoro-silicone, fluoro-elastomer, (natural) rubber, neoprene, EPDM, nitrile, acrylate elastomer, Polyurethane and combinations thereof. In some embodiments, the elastomeric layer may have a stretch modulus (Young's modulus) of less than 0.1 GPa, such as less than about 0.05 MPa, such as less than 1 MPa. In some embodiments, the elastomer layer may have a hardness of less than 90 Shore-A, such as less than about 30 Shore-A, for example less than about 5 Shore-A.

In another embodiment, the insulating layer is applied onto an already patterned surface, for example at least a portion of the patterned carrier. In an embodiment, the insulating patterning layer is applied in a manner in which the applied material follows the structure of the underlying patterned carrier, for example by using methods such as thermal oxidation, thermal nitriding, sputtering, PECVD and / or ALD. The insulating layer is patterned to uncover at least a portion of the underlying patterned carrier. The patterning method may uncover at least a portion of the cavity of the underlying patterned carrier from the insulating pattern layer. Useful patterning methods include an insulating pattern layer covering the top and sidewalls of the structure of the patterned carrier, with the bottom of the cavity of the patterned carrier uncovered in at least some area. The patterning method may be a method such as the lithography and / or etching method described above. In some embodiments, the patterned carrier has at least one layer of insulating material on top of the patterned structure prior to applying the insulating pattern layer. For example, the carrier is patterned by using the etching method wherein the etch-mask comprises at least one layer of insulating material and does not peel off before applying the insulating pattern layer. This results in a thicker layer of insulating material on top of the structure compared to the bottom of the patterned carrier. In this embodiment, using an etching method such as the dry etching method may uncover the bottom of the cavity of the patterned carrier before uncovering the top. The dry-etching method has a higher etching rate in a direction perpendicular to the plane of the patterned carrier than in the lateral direction and is known as anisotropic etching, while allowing the sidewalls to be still covered by an insulating material, the cavity of the patterned carrier Undercover the insulating pattern material. In another embodiment, an insulating pattern layer is patterned to uncover at least a portion that can be used for electrical connection to the carrier and / or the conductive electrode layer.

Various embodiments of the master electrode will be described below with reference to the drawings.

Embodiments include supplying a carrier 1 comprising a conductive / semiconductive disk 2 and an insulating coating layer 3. The insulating coating layer 3 may cover all areas of the conductive / semiconductive disc 2 except for the area in the center on the rear side and the front side, as shown in Fig. 1 (a). A conductive electrode layer 4 is applied onto the front side of the carrier 1, covering at least part of the conductive / semiconductive disc 2 and making electrical contact with the at least part. In one embodiment, the conductive electrode layer 4 also covers at least part of the insulating coating layer 3. In some embodiments, a connection layer 5 is applied onto at least a portion of the conductive / semiconductive disc on the back side of the carrier to enable good electrical connection from the external power source to the master electrode. A cross section of one embodiment of a carrier comprising a conductive / semiconductive disk 2 and an insulating coating layer 3 together with a conductive electrode layer 4 and a connection layer 5 is shown in FIG. 1 (b). In an embodiment, an insulating material 6 is applied onto the carrier 1 and the conductive electrode layer 4 as shown in Fig. 1 (c). The insulating material can be patterned using the lithography and / or nicking method to form the insulating pattern layer 7. A cross section of an embodiment of a master electrode 8 comprising a carrier 1, a conductive electrode layer 4, a connection layer 5, and an insulating pattern layer 7 is shown in FIG. 1 (d).

In an embodiment, the carrier 1 comprises an insulating disk 9 having a conductive via 11 at the center which is at least partially filled with conductive / semiconductive material 10, as shown in FIG. 2 (a). do. The insulating disk 9 may be transparent to enable alignment capability between the master electrode and the substrate. In one embodiment, the conductive electrode layer 4 is applied onto the front side of the carrier 1. In addition, the connection layer 5 can be applied on the rear side to enable good electrical connection from the external power source to the master electrode. Electrical connection between the conductive electrode layer 4 and the connection layer 5 is made possible via the via 11. A cross section of one embodiment of the carrier 1, including an insulating disk 9, a conductive via 11, a conductive electrode layer 4 and a connecting layer 5, is shown in FIG. 2 (b). An insulating material 6 may be applied onto the carrier 1 and the conductive electrode layer 4 as shown in FIG. 2 (c). The insulating material can be patterned using the lithography and / or etching method to form the insulating pattern layer 7. FIG. 2D shows a master electrode comprising a carrier 1 comprising an insulating disk 9, a conductive via 11, a conductive electrode layer 4, a connecting layer 5 and an insulating pattern layer 7. A cross section of one embodiment is shown.

Yet another embodiment includes supplying a carrier 1 comprising a conductive / semiconductive disk 2 covered by an insulating coating layer 3 on at least a portion, such as the front side of the carrier. In some embodiments, an insulating coating layer is first applied to completely cover the conductive / semiconductive disc as shown in Figure 3 (a). In an embodiment, the insulating coating layer is patterned using the lithography and / or etching method to produce the insulating pattern layer 7. Thus, in the formed cavity, at least part of the conductive / semiconductive disk 2 is uncovered, as shown in Fig. 3B. The conductive electrode layer 4 may be selectively applied onto the conductive / semiconductive disc at the bottom of the cavity in the insulating pattern layer as shown in FIG. 3 (c). In order to enable electrical connection with the master electrode, a portion, such as the center of the rear side of the insulating pattern layer 7, is removed, whereby the conductive / semiconductive disk 2 can be uncovered. In order to enable good electrical connection from the external power source to the master electrode, a connection layer 5 can be applied on the uncovered area of the conductive / semiconductive disc, such as the rear side of the master electrode. In some embodiments, at least part of the insulating pattern layer 7 at the rear side is removed before applying the conductive electrode layer 4. Thereafter, the connecting layer 5 can be applied in the same step as applying the conductive electrode layer and in the same manner. However, in some embodiments, the connecting layer 5 may consist of at least one layer applied in the same step as applying the conductive electrode layer 4 and at least another conductive layer applied in a subsequent step. 3 (d) shows a cross section of a master electrode 8 comprising a conductive / semiconductive disk 2, an insulating pattern layer 7, a conductive electrode layer 4 and a connection layer 5. 3 (e) shows a cross section of another embodiment of a master electrode 8 comprising a conductive / semiconductive disk 2, an insulating pattern layer 7, a conductive electrode layer 4 and a connecting layer 5; Wherein the connection layer comprises several layers, at least one of which also covers at least part of the insulating pattern layer 7 at the rear side.

Additional embodiments include supplying a conductive / semiconductive carrier 1. The carrier is patterned on at least the front side using the lithography and / or etching method. In one embodiment, the etch-mask 12 used to pattern the carrier comprises an insulating material.

A cross section of the patterned conductive / semiconductive carrier 1, along with the insulating material as the etch-mask 12, is shown in Fig. 4 (a). An insulating pattern layer 7 may be applied onto the patterned carrier and the etch-mask 12. In some embodiments, insulating pattern layer 7 is applied in such a way as to follow the structure of the underlying pattern layer as shown in FIG. 4 (b). This causes the insulating layer to be thicker on top of the pattern than on the bottom of the cavity due to the combination with layer 12.

The etching method can be used to uncover the carrier 1 from the insulating pattern layer 7 at the bottom of the pattern, leaving the insulating pattern layer 7 on the sidewalls and the top. Dry-etching methods can be used which have a higher etch-rate at the bottom of the cavity than the sidewalls. In some embodiments, the same amount of insulating material as on the top is removed from the bottom of the cavity, leaving the top of the insulating material thickness corresponding to the thickness of the etch-mask 12 used to pattern the carrier. 4 (c) shows a master electrode 8 comprising a patterned carrier 1, an etch-mask 12 and an insulating pattern layer 7 which has been etched to uncover the bottom of the cavity of the patterned carrier. do.

In some embodiments, the conductive electrode layer is selectively applied in an area on the patterned carrier 1 that is not covered by the etch-mask 12 or the insulating pattern layer 7; As shown in Fig. 4D, a second etch-mask 12 may be applied on the rear side to uncover a part of the carrier 1 in a subsequent step by removing the insulating pattern layer.

Removing part of the insulating pattern layer 7 at the back side can be done by using the lithography and / or etching method. The connection layer 5 can be applied on the uncovered part of the carrier to enable good electrical connection from the external power source to the master electrode. In some embodiments, the electrical connection at the master electrode is at the center of the back side of the master electrode. In some embodiments, the connecting layer 5 is applied in the same step as applying the conductive electrode layer 4. In this case, uncovering of the carrier 1 in the connection area is performed before applying the conductive electrode layer 4. In some embodiments, the connection layer 5 is only applied to the uncovered part of the carrier 1. In another embodiment, the connection layer is applied on the uncovered part of the carrier or part of the insulating pattern layer 7.

4 (e) shows a patterned conductive / semiconductive carrier 1 having an insulating etch-mask 12 on top of the carrier structure, an insulating pattern layer 7, a conductive electrode layer applied in the cavity of the patterned carrier ( 4) and a cross section of one embodiment of a master electrode comprising a part of said insulating pattern layer and a connecting layer 5 applied on the rear side onto the uncovered part of the carrier.

In some embodiments, the cavity of the master electrode 8 may be formed by removing the material from the carrier 1 at the bottom of the cavity of the insulating pattern layer 7, for example by using the etching method. Can be deeper before application. In some embodiments, a dry etching method can be used. In some embodiments, the insulating pattern layer 7 can be used as an etch-mask. Creating a deeper cavity allows the master electrode cavity to be filled with a large amount of pre-deposited material used during ECPR plating and / or etched material during ECPR etching.

5 shows a cross section of the master electrode 8 covered by a selectively deposited conductive electrode layer 4 after the cavity of the insulating pattern layer 7 is etched deeper into the carrier 1.

One embodiment includes forming the insulating pattern layer 7 on the carrier 1 by bonding and patterning the insulating bond-layer 13. In some embodiments, the carrier 1 comprises a conductive / semiconductive disc 2 covered with an insulating coating layer 3 except for the center of its front and back sides. In another embodiment, the carrier comprises an insulating disk 9 having a conductive via 11 at the center of itself 1.

In some embodiments, the conductive electrode layer 4 was applied onto the carrier before applying the insulating bond-layer 13. In some embodiments, an insulating bond-layer is bonded to a bond-carrier 14 that can be removed after the insulating bond-layer 13 has been applied onto the carrier 1. For example, insulating bond-layer 13 may be SiO ₂ on Si bond-carrier 14, or glass, such as quartz, on any removable bond-carrier 14, or a polymer film. In some embodiments, an adhesive bond-layer 15 may be applied onto the insulating bond-layer before bonding the insulating bond-layer to the carrier 1 to improve bonding properties such as adhesive strength. The adhesive bond-layer 15 may be made of a material that provides good bond-characteristics with the carrier 1 and / or the conductive electrode layer 4 on the carrier 1 and should be made of a conductive material. Alternatively, the adhesive bond-layer 15 is made of a non-conductive material and can be selectively removed by etching. For example, the adhesive bond-layer 15 may comprise metals and / or alloys that are well bonded with the conductive electrode layer 4. The adhesive bond-layer may comprise a material as described above for the conductive electrode layer 4.

The cross section of the carrier 1 is shown in Fig. 6 (a) together with the insulating bonding-layer 13 and the adhesive bonding-layer 15, the bond carrier 14 and the conductive electrode layer 4 before bonding.

6 (b) shows how the insulating bond-layer 13 on the bond-carrier 14 is bonded to the carrier 1 with the conductive electrode layer 4 and the adhesive bond-layer 15 in the middle. do. In some embodiments, the layer between the insulating bonding layer 13 and the carrier 1 may be changed (eg, mixed) during the bonding process, and the bond-middle layer 16 is formed. The bond-carrier 14 may be removed mechanically and / or by using such an etching method such as dry etching or wet etching. After the bond-carrier 14 is removed, the insulating bond-layer 13 can be patterned using the lithography and / or etching method. 6 (c) shows a patterned insulating bond-layer 13 bonded to the carrier 1 with a bond-intermediate layer 16 comprising a conductive electrode layer 4 and an adhesive bond-layer 15 therebetween. A cross-section of one embodiment of a master electrode 8 including) is shown. In some embodiments, the conductive electrode layer 4 is on the intermediate layer 16, or when no bond-intermediate layer 16 is present (ie, the insulating bond-layer 13 is on the carrier 1). May be selectively applied within the cavity of the insulating bond-layer 13 patterned onto the carrier 1.

In an embodiment, the master electrode enables electrical connection from an external power source to at least a portion of the conductive electrode layer.

In some embodiments, the electrical connection is made with a conductive / semiconductive material of the carrier that is connected to at least a portion of the conductive electrode layer from an external power source.

In an embodiment, the electrical connection is made with a connection layer connected to at least a portion of the conductive / semiconductive portion of the carrier which is connected to the conductive electrode layer from an external power source.

The electrical connection can for example be located on the back side of the carrier, ie on the opposite side of the insulating structure of the master electrode. In some embodiments, an electrical connection can be used at the center of the carrier. In another embodiment, the electrical connection is made from the front side, such as with a perimeter of the carrier.

In some embodiments, the insulating pattern layer and / or the insulating portion of the carrier are directly and / or through the electrolyte, except in a cavity filled with the electrolyte defined by the substrate and the insulating pattern layer during ECPR etching or ECPR plating. The application was made in such a way that there were no short circuits and / or significant electrical connections between the electrical connection to the conductive electrode layer and the electrical connection to the substrate. For example, the insulating material covers all of the conductive / semiconductive portions of the carrier except in the cavity and electrical connection area of the insulating pattern layer.

In some embodiments, the master electrode is characterized in that when the master electrode comes into contact with the substrate during ECPR etching or plating, it creates an electrical connection from an external power source to the substrate seed layer.

In some embodiments, at least some areas of the seed layer that may be used for electrical contact are not covered by the master electrode during physical contact with the substrate.

In some embodiments, electrical contact with the substrate seed layer may be supplied by having a master electrode having an area entering physical contact with a larger substrate seed layer area.

FIG. 7A shows a cross section of a master electrode 8 having a smaller area entering contact with a large substrate 17 seed layer 18 area.

Figure 7 (b) shows a top view of one embodiment of a master electrode having a smaller area entering contact with a larger substrate seed layer 18 area.

In some embodiments, the master electrode and the substrate have the same dimensions, and material has been removed from the master electrode in at least some areas to provide a place for electrical connection to the seed layer on the substrate. In one embodiment, a recess is arranged in the perimeter of the master electrode that allows connection with the seed layer of the substrate.

Figure 7 (c) shows a cross section of a master electrode 8 with a recess 19 allowing electrical connection to the substrate seed layer. The recess may be present at a few specific connection sites or over the circumference of the master electrode.

Figure 7 (c) shows a cross section of a master electrode 8 with a recess 19 allowing electrical connection to the substrate seed layer. The recess may be present at a few specific connection sites or over the circumference of the master electrode.

In some embodiments, connection holes 20 can be made through the master electrode 8 to allow electrical connection of the substrate 17 to the seed layer 17. In one embodiment, the connection hole 20 is made adjacent to the perimeter of the master electrode 8.

Fig. 7 (d) shows the upper surface of the front side of the master electrode 8 including the insulating pattern layer 7 and the conductive electrode layer 4 together with the connection hole 20 in the perimeter. In one embodiment, the connecting holes 20 are made inside the master electrode 8 area, as shown in the top view in Fig. 7E. The recesses and / or connection sites may be prepared by methods such as the lithography and / or etching methods, and / or by polishing, grinding, drilling, ablation, CNC-machining, ultrasonic machining, diamond machining, waterjet machining, laser machining, (sand or Fluid), such as blasting, and / or combinations thereof. The recess and / or connection site can be dimensioned to fit the electrical contact. The electrical contacts can be, for example, thin foils, springs, pins, and / or other suitable electrical contacts and / or combinations thereof. Electrical contacts are materials that do not corrode or oxidize in the electrolyte used during and / or according to the ECPR etching and / or plating processes, such as stainless steel, Au, Ag, Cu, Pd, Pt, planarized titanium and / or It may comprise at least one layer of combinations thereof.

In some embodiments, the connection site to the seed layer provided by the master electrode design is positioned in a manner that allows for a uniform current distribution in the seed layer during ECPR etching and / or plating. For example, recesses may be located throughout the perimeter of the master electrode to allow continuous electrical connection to the seed layer perimeter. In another embodiment, multiple connection holes (such as at least three) may be evenly distributed along the perimeter of the master electrode, which may allow a well distributed electrical connection to the seed layer of the substrate to be achieved. .

In some embodiments, the portion of the master electrode that is conductive, connected to the conductive electrode layer, and / or in close contact with the electrical connection to the seed layer is from the conductive electrode layer of the master electrode during ECPR etching and / or ECPR plating. It is coated with an insulating material to prevent shorting to the substrate seed layer.

In some embodiments, the electrical seed layer connection is an integrated portion of the master electrode. In this case, the seed layer connection on the master electrode must be insulated from the conductive portion of the master electrode connected to the conductive electrode layer. Otherwise, when the master electrode is used for ECPR etching or plating, there may be a short circuit between the two electrodes. In some embodiments, the electrical connection of the master electrode to the conductive electrode layer is at the center of the back side of the carrier from which the insulating coating of the carrier is removed. In this case, the seed layer connection may be a conductive layer from the rear side perimeter to the front side and may be separated from the conductive portion of the carrier by insulating material. The seed layer connection may comprise the same material as used for the conductive electrode layer described above, and may be applied in the same manner.

7 (f) shows a master electrode 8 comprising a conductive carrier, an insulating pattern layer 7 and a conductive electrode layer 4. The insulating pattern layer covers all areas of the conductive carrier, except in the cavity on the center and the front side of the rear side, through which the electrical connection is made possible via the connecting layer 5. The seed layer connection 31 is provided on the perimeter on the rear side of the master electrode, the edge, and the perimeter on the front side. The seed layer connection 31 is separated from other conductive portions of the master electrode by the insulating pattern layer. The insulating layer may be arranged at the side of the seed layer connection.

7 (g) shows that the master electrode 8 including the insulating pattern layer 7, the conductive carrier 1, the conductive electrode layer 4, the connection layer 5 and the seed layer connection portion 31 is formed by the seed layer ( A method of contacting a substrate 17 having 18) is shown. The electrolyte 29 is enclosed in an electrochemical cell defined by the cavity between the seed layer and the insulating pattern layer. An external electrical voltage source is connected to the connection layer 5 (the connection layer is electrically connected to the conductive electrode layer 4 via the carrier 1) and to the seed layer connection 31 (the seed layer connection is the seed layer). Electrically connected), so that within the cavity of the insulating pattern layer, an anode material pre-deposited on the conductive electrode layer, which is an anode, is dissolved and transported through the electrolyte, and the plating structure 24 is electrochemically Inside the cell, it is formed onto a seed layer that is a cathode. By inverting the polarity of the electrical voltage source, electrochemical etching of the seed layer occurs.

FIG. 7 (h) shows how the seed layer connections 31 are arranged over the large surface of the pattern layer 7 and over the entire surface except for the edge substantially adjacent to the cavity of the pattern layer. The separate seed layer connections 31 shown in Fig. 7h are interconnected at other positions not shown in Fig. 7h, since the surface of the pattern layer may form a continuous surface.

If the surface of the pattern layer does not form a continuous surface, different portions 31 of the connection can be connected with the connection area at the rear side of the carrier via the carrier as shown in Fig. 7 (i). Otherwise, the seed layer contacted by the separate connections 31 may form a connection between the separate connection portions 31. The separate connections 31 can contribute to reducing the resistance of the seed layer, especially in thin seed layers. Less resistance may have advantages as described below.

In some embodiments of the invention, a master electrode comprising at least partially conductive / semiconductive carrier, conductive electrode layer, insulating pattern layer, and / or predeposited material comprises at least one electrical with a substrate comprising a conductive seed layer. Form chemical cells. The electrochemical cell is enclosed within a cavity of the insulating pattern layer and includes an electrolyte in contact with the conductive electrode layer or predeposited anode material and the seed layer. The thickness and resistivity of the conductive portion of the carrier, the conductive electrode layer, the seed layer and / or the predeposited anode material are arranged to provide a minimum current density difference between the electrochemical cells. For example, the thickness and resistivity can be arranged to provide a difference in current density that is less than 50%, such as less than 20%, for example, less than 10%, such as less than about 1%.

For example, due to the resistance in the thin seed layer, there may be a resistive voltage drop, i.e., a preposition, between any points located on the seed layer. The conductive material in the master electrode may be arranged to provide a similar or similar resistive voltage drop, ie, a potential difference, between corresponding points located on the master electrode.

In some embodiments, the conductive / semiconductive portion of the master electrode can include at least one layer of conductive / semiconductive material, wherein the at least one layer has different thicknesses and / or resistivities in different areas. In one example, the thickness of the at least one conductive / semiconductive layer is greater at points located at shorter radial distances from the center of the master electrode compared to points located at long radial distances from the center. In another example, the resistivity of the at least one layer is lower at points located at shorter radial distances from the center of the master electrode compared to points located at longer radial distances from the center. In another example, the specific conductivity of the at least one layer is greater at points located at shorter radial distances from the center of the master electrode compared to points located at longer radial distances from the center.

In some embodiments, the master electrode can include several points and / or areas that can be individually contacted with different external potentials. Different external potentials may be applied to points on the master electrode, where the difference in applied external potentials is the same or similar to the potential difference in the seed layer between the corresponding points due to the resistive voltage drop in the seed layer. Do.

In some embodiments, the potential difference and / or current density difference between electrochemical cells can be calculated using mathematical modeling and / or measured in an experiment.

In some embodiments, the specific conductivity of the conductive / semiconductive portion of the master electrode is equal to or greater than the specific conductivity of the seed layer. For example, the sum of the specific conductivity of the conductive / semiconductive carrier, the conductive electrode layer and / or the pre-deposited anode material is equal to, or more than two times, for example, seven times the specific conductivity of the seed layer. As above, at least 5 times, such as at least about 10 times, greater than the specific conductivity of the seed layer.

In some embodiments, the master electrode has a circular geometry. For example, the master electrode can have substantially the same dimensions as a silicon wafer, for example according to the SEMI ^™ -standard. For example, the master electrode can have dimensions of standard 100mm, 150mm, 200mm, 300mm or 450mm diameter silicon wafers. The substrate may have substantially the same circular shape and / or thickness as the master electrode.

In some embodiments, the master electrode is arranged to allow electrical connection from an external power source to the conductive electrode layer. An electrical connection area 33 (see FIG. 19) may be located, for example, on the rear side of the master electrode 8 in contact with the carrier 1, which may be in contact with the conductive electrode layer 4. . There may be several electrical connection areas 33 located on the master electrode 8, which may be separated from one another by an insulating material 32. The electrical connection area 33 can, for example, have the shape of a circle, square, rectangle, arc, ring and / or segment thereof. In one embodiment, the master electrode 8 is on the rear side at a distance between the center ring and the perimeter separated by the insulating material 32, as shown in Figs. 19 (a) and 19 (b). It is arranged with at least one ring / arc connection area 33 positioned and / or a circular connection area 33 arranged at the center of the rear side. In some embodiments, at least two ring- and / or arc-shaped connection areas may be uniformly spread over the distance between the center and the perimeter. In other embodiments, the radial space between different contact areas may be less at higher distances from the center. In some embodiments, the number of rings and / or calls located between the center and the perimeter is at least four, such as at least eight, such as at least three, for example at least five. The connection areas can be arranged independently of one another and different external potentials can be applied to each connection area individually. In some embodiments, different external potentials are applied at different locations within at least one connection area. A connection from an external power source can be supplied over several locations within one connection area, for example, to spread the current / potential evenly.

In other embodiments, the same external potential can be applied to at least some of the different connection areas on the master. In one embodiment, for example, all or almost all connecting areas on the rear side of the master electrode are the same or nearly the same when predepositing the anode material onto the master electrode, such as when predeposition is done by electroplating. It comes into contact with an external power source having a potential. The electroplating method can be done with the ECPR etching method from the seed layer, and / or by standard electroplating methods.

In one example, the master electrode forms at least one electrochemical cell with the substrate; The electrochemical cell is assumed to cover all areas between the master electrode and the substrate for simplicity; The seed layer comprises a thin conductive layer having a uniform thickness on a circular substrate having a radius of 200 mm; The specific conductivity of the seed layer is 5 Ω ⁻¹ ; The master electrode comprises a carrier, a conductive electrode layer and an insulating pattern layer; The master electrode has the shape of a disk having a radius of 200 mm; The sum of the specific conductivity of the carrier and the conductive electrode layer is 25 Ω ⁻¹ ; An external voltage is applied to the entire perimeter of the seed layer and the center point on the rear side of the master electrode; At least one point in the electrochemical cell is located at the radial center of the master electrode and seed layer; At least one point in the electrochemical cell is located in the radial perimeter of the seed layer and the master electrode; The potential across the conductive electrode layer has a maximum potential difference of 6 mV, as shown in Fig. 8 (a); The potential difference across the seed layer has a maximum potential difference of 5 mV, as shown in Fig. 8 (b); Due to this, as shown in Fig. 8C, the current density at the center is 13.7 mA / mm ² and the current density at the perimeter is 13.5 mA / mm ² . This particular example describes how the specific conductivity of the conductive portion of the master electrode is matched with the seed layer to provide substantially the same current density at different points.

In a further example, the specific conductivity of the seed layer is 5 Ω ⁻¹ and the sum of the specific conductivity of the carrier and conductive electrode layers is 30 Ω ⁻¹ ; The potential difference across the conductive electrode layers is as shown in Fig. 9A; The potential difference across the seed layer is as shown in Figure 9 (b); Thus, as shown in Fig. 9C, the current density at the center is 13.7 A / dm ² and the current density at the perimeter is 13.7 A / dm ² . This particular example illustrates how the specific conductivity of the conductive portion of the master electrode is matched with the seed layer to provide the same current density at different points.

In a further example, the specific conductivity of the seed layer is 5 Ω ⁻¹ , and the sum of the specific conductivity of the carrier and conductive electrode layers is 100 Ω ⁻¹ ; The potential difference across the seed layer is as shown in Fig. 10 (a); Thus, as shown in Fig. 10B, the current density at the center is about 13.7 A / dm ² and the current density at the perimeter is about 14.4 A / dm ² . This particular example describes the case where the specific conductivity of the conductive portion of the master electrode is no longer matched with the seed layer, resulting in a significant current density difference at different points.

In the example, it is assumed that the electrochemical cell is one cell covering the entire surface between the seed layer and the master electrode, but in many embodiments there are several electrochemical cells separated by the insulating pattern layer. For example, the cell area may cover between 5 and 50% of the entire seed layer and the master electrode area and may be uniformly spread across the master electrode and seed layer surfaces. Moreover, the results described in the above examples can be similar to the results by multiple electrochemical cells.

As described in the example, the geometry and resistivity of the conductive layer of the master electrically connected to the at least one electrochemical cell is to provide a potential drop across the conductive layer of the master electrode that is about the same or nearly the same as that across the seed layer. Can be selected in relation to the geometry and specific conductivity of the seed layer; The current density of the electrochemical cell is the same or nearly the same.

The potential drop and current density distribution can be described for any body (eg master electrode and / or seed layer) that can be described by x, y and z coordinates and any contact point for applying an external voltage. have. The dislocation distribution in the body can be determined by partial differential equations:

-σ ・ (∂ ² V / ∂x ² + ∂ ² V / ∂y ² + ∂ ² V / ∂z ² ) = 0

Where ∂ is electrical conductivity and V is potential; The boundary condition is set, for example, as either the potential V or the current density J.

1. in the contacting area: fixed potential V; Or fixed current density

J = -σ · (∂J / ∂x + ∂J / ∂y + ∂J / ∂z)

2. At the surface interfacing with the electrochemical cell: current density

J = -σ. (∂J / ∂x + ∂J / ∂y + ∂J / ∂z);

Wherein J at any point in the electrochemical cell can be described by the Butler-Volmer equation J = i ₀ * exp (C * (η), where i ₀ is the exchange current density and C is the above Constant according to the electrochemical properties of the electrochemical cell, η is the overpotential at a point located at the anode or cathode surface.

3. Electrically insulated surfaces: current density

J = -σ · (∂J / ∂x + ∂J / ∂y + ∂J / ∂z) = 0

In some embodiments, the differential equation is a method of solving an Ordinary-Differential-Equation (ODE), such as an Euler method, a Taylor series method, or a Runge-Kutta method; Or in computations involving numerical methods, such as the finite difference method, the Crank-Nicolson method, or the method of solving partial differential equations such as elliptical PDE. In some embodiments, this numerical method may be performed for a two-dimensional system, for example by using a sphere coordinate system. In other embodiments, such numerical methods may be performed on three-dimensional systems. In additional embodiments, such numerical methods may include using finite element methods.

In one embodiment, selecting the geometry and specific conductivity of the conductive layer of the master electrode to match the resist plating rate of the seed layer includes measuring the potential distribution of the conductive layer and / or the seed layer. do. Moreover, one embodiment may include measuring the current density (ie, plating / etching rate) distribution in the at least one electrochemical cell. For example, measuring the current distribution can include measuring the thickness distribution of the structural layer formed in the at least one electrochemical cell because the plating / etching speed linearly follows the current density. In a further embodiment, the geometry and thickness of the conductive layer of the master electrode is changed after measuring the current density distribution in the at least one electrochemical cell; Thereafter, an iterative method is used in which subsequent alteration and measurement of the current distribution is performed until the current density between any points in the at least one electrochemical cell is minimized.

20 (a) and 20 (b), the electrochemical cell has a polar distribution with the first contact portion of the central master electrode and the second contact portion of the seed layer along the perimeter, which may be circular. It can have In this case, the resistivity of the conductive layers will have an exponential relationship with the specific conductivity. Therefore, the potential distribution across the seed layer will be exponential as shown in Figure 8 (b). In order to obtain a relatively constant current density, the specific conductivity of the master electrode should be approximately 5-7 times the specific conductivity of the seed layer.

In another embodiment, the electrochemical cell may have a linear distribution with the first contact portion on one side of the perpendicular master electrode and the second contact portion on the opposite side of the seed layer at right angles. In this case, the potential distribution will be linear. In one embodiment, the specific conductivity of the master electrode may be substantially the same as the specific conductivity of the seed layer to obtain a substantially constant current density in the electrochemical cell.

The specific conductivity of the master electrode is affected by the number of factors, as shown in Figure 7 (h). The master electrode may comprise a disk 1 of conductive / semiconductive material. The disc may be constructed from several disc members of different materials. These materials together form the specific conductivity of the disk. For example, the disk may be composed of a semiconductive material such as silicon doped at a predetermined rate to determine resistivity. Doping may be constant or variable across the surface. The semiconductive material may be provided with an additional layer of conductive material such as platinum or gold to further adapt the specific conductivity. The disk may have a constant thickness or a variable thickness.

The conductive and / or semiconductive disk is provided with a conductive electrode 4 located only at the bottom of the cavity, as shown in FIG. 7 (h). Since this material is often thinner than the disk, it will only contribute a certain degree of conductivity to a small degree. Finally, the predeposited anode material can be arranged onto the conductive electrode layer 4. In addition, this anode material will contribute to a certain conductivity to some extent depending on thickness and cell density. The specific conductivity increases with thicker anode material and higher cell density. In one embodiment, these materials can be adjusted to provide different lengths of electrochemical cells to induce different current densities. For example, if the height of the cavity is 25 μm, the material 4 has a height of 1 μm in one cavity and 20 μm in another cavity, thereby affecting the current passing through the electrochemical cell. This is important when the electrochemical etching / plating process is limited in mass transport, such as when the conductivity of the electrolyte in an electrochemical cell is low or the current density is high to approach the limiting current.

As shown in Fig. 7 (h), the material 31 which will be in contact with the seed layer during etching / plating helps to increase the specific conductivity of the seed layer, thereby making the current distribution more uniform.

All these factors can be used in combination to provide the desired final result. In addition, different potentials can be added to other portions of the master electrode and to the substrate as described above.

In some embodiments, during fabrication of the master electrode 8, the electrical specific conductance of the conductive / semiconductive portions of the carrier 1 and the conductive electrode layer 4 may be the substrate 17 on which ECPR etching and / or plating is performed. Can be matched to a particular conductance of the seed layer 17. The specific conductances of the carrier 1 and / or the conductive electrode layer 4 are each selected by a material having a lower or higher resistivity, and / or the carrier 1 and / or the conductive electrode layer 4 respectively. Decrease or increase by making thicker or thinner. The total resistivity with respect to current during ECPR etching and / or plating is determined by the sum of the resistances of the following paths:

1.conductive / semiconductive part of the carrier 1,

2. conductive electrode layer 4,

3. an electrochemical cell 23 formed in ECPR etching and / or plating, and

4. Seed layer 18 of the substrate

For convenience, the resistance of the path through the conductive / semiconductive portion of the carrier (1) is called R ₁ ; The resistance of the path through the conductive electrode layer ₄ is called R ₄ ; The resistance of the path through the seed layer ₁₈ is called R ₁₈ ; The resistance of the path through the electrochemical cell 23 formed during ECPR etching and / or plating is called R ₂₃ .

In some embodiments, the carrier 1 and the conductive electrode layer 4 of the master electrode 8 are dependent upon which area the current supplied during ECPR etching and / or plating passes through the electrochemical cell 23 itself. Regardless, it is characterized by experiencing the same total resistance when passing through the carrier 1, the conductive electrode layer 4 and the seed layer 18. In some embodiments, this is done by providing electrical contact only from the external power source to the center of the back side of the carrier 1 and to the perimeter of the seed layer 18 on the substrate 17. In this case, the total electrical resistance to the current passing from the center on the rear side of the carrier 1 through the carrier, the conductive electrode layer 4 and the seed layer 18 to the electrical contacts of the perimeter is electrified in any area. If the same is true regardless of whether it passes through the chemical cell 23, the current density passing during ECPR etching and / or plating will be the same regardless of the position of the electrochemical cell relative to the seed layer electrical contact. As such, the etch and / or plating rate linearly proportional to the current density will be the same in all electrochemical cells 23 regardless of location. The master electrode / seed layer resistance matching described reduces the problem of non-uniform etch / plating rates along the radial direction resulting in non-uniform radial height distributions inherently associated with conventional electrodeposition / electrochemical etching methods; The problem is described as a terminal effect.

In some embodiments, such as in the thin seed layer, the total resistance of the carrier 1 and the conductive electrode layer 4 is lower than the resistance of the seed layer 18, such that the master electrode and when performing ECPR etching and / or plating. This results in higher current densities in the electrochemical cells located closer to the perimeter than at the center of the substrate. In other embodiments, such as in thick seed layers, the total resistance of the carrier 1 and conductive electrode layer 4 is higher than the resistance of the seed layer 18, such that the master electrode when performing ECPR etching and / or ECPR plating. (8) and lower current density in the electrochemical cell 23 located closer to the perimeter than at the center of the substrate 18.

For example, the resistance R 'of the path to and from the electrochemical cell 23 at the center and to the electrochemical cell at the center and to the electrochemical cell at the perimeter shown in FIG. Can be matched to the resistance R " of the path from the electrochemical cell of

1.R '= 1 / (1 / R ₁ ' + 1 / R ₄ ') + R ₁₈ ''equals R "= 1 / (1 / R ₁ " + 1 / R ₄ ") + R ₁₈ " , j '= j "; or

2. R '= 1 / (1 / R ₁ ' + 1 / R ₄ ') + R ₁₈ ' is greater than R "= 1 / (1 / R ₁ " + 1 / R ₄ ") + R ₁₈ " If j '<j "; or

3. R '= 1 / (1 / R ₁ ' + 1 / R ₄ ') + R ₁₈ ' is less than R "= 1 / (1 / R ₁ " + 1 / R ₄ ") + R ₁₈ " Where j '> j ", where j' is the current density of the electrochemical cell at the center and j" is the current density of the electrochemical cell at the perimeter.

By matching the resistors R ₁ and R ₄ to R ₁₈ in different ways, a specific height distribution of the ECPR etched or plated structure along the radial direction from the center of the master electrode to the perimeter can be achieved.

In some embodiments, the conductive portion of the carrier 1 (e.g., conductive / semiconductive disk 2) is at the center on the front side due to the insulating material coating 3 as shown in Figure 1 (d). It is connected only to the conductive electrode layer 4 of. In this case, only the resistivity and thickness of the conductive electrode layer 4 need to match the seed layer 18.

In some embodiments, the radial height distribution of the ECPR etched or plated structure may be used to compensate for different height distributions resulting from previous or subsequent process steps. In one embodiment, the resistance in the master is seed layer 18 applied to a uniform thickness (e.g., by PVD) onto substrate 17 having concave layer 25 shown in Figure 13 (a). To 1 / R ₁ + 1 / R ₄ <1 / R ₁₈ , and an ECPR etched or plated structure 24 is fabricated with a convex radial height distribution that compensates for the concave layer, such that the ECPR etched or plated The top of the structure 24 is finished at the same height h from the substrate, as shown in Figure 13 (b). In another embodiment, the resistance in the master is seed layer 18 that is applied to a uniform thickness (eg, by PVD) onto substrate 17 having convex layer 26 shown in FIG. 14 (a). ), Whereby 1 / R ₁ + 1 / R ₄ > 1 / R ₁₈ , an ECPR etched or plated structure 24 is made with a concave radial height distribution that compensates for the convex layer, so that the ECPR etch or The top of the plated structure 24 ends at the same height h from the substrate, as shown in Figure 14 (b).

In order to achieve any plating or etching effect, the master electrode can be arranged with disk and electrode layers having a thickness different from the center and / or with a material different from the center; The different materials have different conductivity. For example, at half of the radial distance from the center the thickness can be half, or alternatively, the resistivity can be doubled.

In some embodiments, the master electrodes are arranged using a method that produces a very uniform height distribution of the ECPR etched or plated structural layer. However, in some other embodiments, at least some of the carrier and / or conductive electrode layers may be modified in the cavity of the insulating pattern layer to provide a non-uniform pattern in some of the structural layers. In one embodiment, as shown in Fig. 21A, the carrier 1 of the master electrode 8 may have a recess in at least one cavity of the insulating pattern layer 7; The recess is coated on the wall with a conductive electrode layer (4); Predeposited anode material 28 may be arranged on the conductive electrode layer. During ECPR plating on the substrate 17 inside the cavity with the recess, as shown in Fig. 21 (b), an area located closer to the wall of the insulating pattern layer 7 has a higher current density ( Plating rate) to achieve a higher height of the ECPR plated structure 24.

In yet another embodiment, as shown in Fig. 22A, the carrier 1 and the conductive electrode layer 4 use the projecting structure in at least one cavity of the insulating pattern layer 7; Predeposited anode material 28 is arranged on the conductive electrode layer. During ECPR plating on the substrate 17 inside the cavity having the protruding structure, as shown in Fig. 22 (b), the area on the substrate located closer to the protruding structure achieves higher current density, so that the ECPR plating The height of the structure 24 is made higher. In some cases, embodiments that produce structural layers with non-uniform heights, such as in FIGS. 21 (b) and 22 (b), may be used for interlocking bump structures, solder ball placement. It can be used for applications such as foundation or mechanical alignment structure / fiducial.

In the foregoing application, various features and method steps have been described in different combinations and arrangements. However, it is emphasized that other combinations may be performed by those skilled in the art having read this specification, and such combinations are within the scope of the present invention. Moreover, various steps may be changed and changed within the scope of the present invention. The invention is only limited by the appended patent claims.

Claims (53)

In a system comprising a master electrode arranged on a substrate: The master electrode comprises a patterned layer of at least partially insulating material having a first surface provided with a plurality of cavities in which the conductive material is arranged, the electrode conductive material being electrically connected to at least one electrode current supply contact; The substrate comprises a top surface arranged in contact with or adjacent to the first surface and having a structure and / or conductive material of conductive material arranged thereon, the substrate conductive material electrically connected to at least one current supply contact. Become; A plurality of electrochemical cells are formed to be delimited by the cavity, the substrate conductive material and the electrode conductive material, the cells comprising an electrolyte; The electrode resistance between the electrode conductive material and the electrode current supply contact and the substrate resistance between the substrate conductive material and the substrate current supply contact comprise a master electrode adapted to provide a predetermined current density in each electrochemical cell. system. The method of claim 1, Wherein the electrode resistance and the substrate resistance are each formed by at least one electrically conductive material having a certain specific conductivity defined as the thickness of the material divided by the resistivity of the material. The method of claim 2, And the specific conductivity is arranged to vary over the surface of the master electrode. The method of claim 3, The specific conductivity is arranged to vary by varying the thickness of the material. The method according to claim 3 or 4, The specific conductivity is arranged to be varied by varying the resistivity of the material. The method of claim 5, And the material is a doped semiconductor material having a doping arranged to vary to provide the resistivity. The method according to any one of the preceding claims, And wherein the electrode conductive material comprises a disk having a range substantially the same as the first surface. The method of claim 7, wherein And the disk comprises a master electrode, wherein the disk is made of a conductive and / or semiconductive material. The method of claim 1, wherein And wherein the electrode conductive material comprises a cavity conductive material arranged within the bottom of each cavity. The method of claim 9, And the cavity conductive material is a material arranged under the cavity and made of an inert material. The method of claim 10, And the cavity conductive material is an additional material pre-deposited in the cavity and at least partially consumed during the plating process. The method according to any one of claims 9 to 11, And the cavity conductive material is in electrical contact with the disk. The method according to any one of claims 9 to 12, And the disk has a substantially constant thickness. The method of claim 13, And said disk comprises a plurality of disk members having different specific conductivity, said disk members being arranged on top of each other. The method according to any one of claims 7 to 14, The electrode supply contact is arranged in the center of the disk. The method according to any one of claims 7 to 15, And the electrode supply contact comprises a number of discrete contacts. The method according to claim 15 or 16, And the discrete contact comprises at least one ring contact or ring segment contact arranged radially from the center of the disk. The method according to claim 16 or 17, And wherein each discrete contact is provided with a specific potential during the plating or etching process. The method according to any one of claims 7 to 18, And the disk is substantially circular. The method of claim 19, And wherein the thickness of at least one of the disk members varies with distance to the center of the disk. The method according to any one of the preceding claims, And the substrate resistance is at least partially provided by a seed layer arranged on at least a portion of the top surface of the substrate. The method of claim 21, And the substrate electrode contact is arranged in at least a portion of the perimeter of the substrate seed layer. The method of claim 21, The substrate electrode contact is arranged along a perimeter of the substrate seed layer. The method according to any one of claims 21 to 23, wherein And the substrate electrode contact comprises a number of discrete contacts. The method of claim 24, Each discrete contact is supplied with a specific potential during the plating and etching process. The method according to any one of claims 21 to 25, And the master electrode includes at least one contact area in contact with the seed layer to provide current to the seed layer. The method according to any one of claims 21 to 26, The pattern layer is at least one of conductive material arranged within the first surface at a portion between the cavities that contact with the substrate conductive material during a plating or etching process to increase a specific conductivity of the substrate conductive material over the area A system comprising a master electrode, characterized in that it comprises an area of. The method according to any one of the preceding claims, If the potential difference across the surface of the electrode conductive material and / or the surface of the substrate conductive material is significant, adaptation is performed when the current density difference of the electrochemical cell between the surfaces is at least 1%, such as at least 2%. A system comprising a master electrode, characterized in that. The method of claim 28, The adaptation is such that the specific conductivity of the electrode conductive material is on average between 0.1 and 100 times, such as between 0.5 and 20 times the specific conductivity of the substrate conductive material, for example between 1 and 10, such as 1 to 7 times. A system comprising a master electrode, characterized in that. The method according to any one of the preceding claims, Wherein each cavity is provided with a material having a thickness specified for each cavity. In a master electrode intended to be arranged on a substrate: The master electrode comprises a patterned layer of at least partially insulating material having a first surface provided with a plurality of cavities in which the conductive material is arranged, the electrode conductive material being electrically connected to at least one electrode current supply contact; A plurality of electrochemical cells are formed to be delimited by the cavity, the electrode conductive material and the substrate; The electrode resistance between the electrode conductive material and the electrode current supply contact is adapted to be associated with a substrate conductive material intended to provide a predetermined current in each electrochemical cell to be formed. The method of claim 31, wherein Wherein the electrode resistance and the substrate resistance are each formed by at least one electrically conductive material having a certain specific conductivity defined as the thickness of the material divided by the resistivity of the material. 33. The method of claim 32, And said specific conductivity is arranged to vary over the surface of said master electrode. The method of claim 33, wherein The specific conductivity is arranged to be varied by varying the thickness of the material. The method of claim 33 or 34, And said specific conductivity is arranged to vary by varying the resistivity of said material. 36. The method of claim 35 wherein And the material is a doped semiconductor material having a doping arranged to vary to provide the variable resistivity. The method according to any one of claims 31 to 36, And wherein said electrode conductive material comprises a disk having substantially the same range as said first surface. The method of claim 37, And the disk is made of a conductive and / or semiconductive material. The method according to any one of claims 31 to 38, And the electrode conductive material comprises a cavity conductive material arranged under each cavity. The method of claim 39, And the cavity conductive material is a material arranged under the cavity and made of an inert material. The method of claim 40, And the cavity conductive material is an additional material that is pre-deposited in the cavity and at least partially consumed during the plating process. The method according to any one of claims 39 to 41, And the cavity conductive material is in electrical contact with the disk. The method according to any one of claims 39 to 42, And the disk has a substantially constant thickness. The method of claim 43, And said disk comprises a plurality of disk members having different specific conductivity, said disk members being arranged on top of each other. The method according to any one of claims 37 to 44, The electrode supply contact is arranged in the center of the disk. The method according to any one of claims 37 to 45, And wherein said electrode supply contact comprises several discrete contacts. 47. The method of claim 45 or 46, And the discrete contact comprises at least one ring contact or ring segment contact arranged radially from the center of the disk. 48. The method of claim 46 or 47, And wherein said discrete contact is provided with a specific potential during the plating or etching process. 49. The compound of any one of claims 37-48, And the disk is substantially circular. The method of claim 49, The thickness of at least one of the disk member is a master electrode, characterized in that varies with the distance to the center of the disk. The method according to any one of claims 31 to 50, And wherein each cavity is provided with a material having a thickness specific to each cavity. A method of pre-depositing a material in a cavity of a master electrode having a patterned layer comprising an insulating material on which a cavity is formed, and a conductive electrode layer forming a lower portion of the cavity and having contact portions for external connection to a power source: Arranging a conductive member on the support; Arranging the master electrode on the contact member to achieve electrical contact between the conductive electrode layer and the contact member in at least two contact portions; Arranging an electroplating anode of material to be deposited in the cavity on the master electrode, wherein the electrochemical cell is formed to be delimited by the cavity, the substrate conductive electrode layer and the electroplating anode, An electroplating anode arrangement, wherein the cell comprises an electrolyte; The conductive electrode layer being a cathode from the anode by connecting a power source to the electroplating anode and the contact member to deposit the material in the cavity on top of the conductive electrode layer and passing current through the electrochemical cell. Pre-depositing the material comprising the step of delivering the material to the product. A method of performing etching or plating of a substrate by a master electrode, the master electrode comprising a pattern layer of at least partially insulating material having a first surface provided with a plurality of cavities in which a conductive material is arranged, the electrode conductive A method of performing etching or plating of a substrate, wherein the material is electrically connected to at least one electrode current supply contact: Arranging the master electrode on a support; Supplying an electrolyte to the cavity; Arranging a substrate on the master electrode, the substrate comprising a top surface having a structure of conductive material and / or conductive material arranged thereon, wherein the substrate is electrically conductive to at least one current supply contact. And an electrochemical cell is defined to be delimited by the cavity, the substrate conductive electrode layer and the electrode conductive material, the cell comprising an electrolyte; Connecting a power source to the electrode current supply contact and the substrate current supply contact to pass a current through the electrochemical cell to allow a current to pass between the master electrode and the substrate, The method further includes selecting a master electrode, wherein a specific resistivity of the master electrode is adapted to the substrate conductive material.

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