KR20080080834A

KR20080080834A - Power gating circuit

Info

Publication number: KR20080080834A
Application number: KR1020070021076A
Authority: KR
Inventors: 김수환
Original assignee: 삼성전자주식회사
Priority date: 2007-03-02
Filing date: 2007-03-02
Publication date: 2008-09-05

Abstract

A power gating circuit is provided to increase an operation speed of a semiconductor integrated circuit device by suppressing a body effect when operating the semiconductor integrated circuit device in a normal mode. A power gating circuit(300) includes first and second transistors, a capacitor, and a substrate voltage control circuit. The first and second transistors are connected between external power(VDD) and a logic block(200) in series. The capacitor has one end connected to connection terminals of the first and second transistors and the other grounded end. The substrate voltage control circuit controls a substrate voltage of the second transistor according to an operation mode.

Description

Power gating circuit {POWER GATING CIRCUIT}

1 is a circuit diagram showing a general power gating circuit.

2 is a circuit diagram illustrating an embodiment of a power gating circuit according to the present invention.

3 is a circuit diagram showing another embodiment of a power gating circuit according to the present invention.

4 is a table showing operation in each mode of the power gating circuit according to the present invention.

5 is a graph showing improved performance of a power gating circuit according to the present invention.

Explanation of symbols on the main parts of the drawings

200: logic block 400: power gating circuit

410: controller 420: net bias generator

430: reverse bias generator

The present invention relates to a semiconductor integrated circuit device, and more particularly to a power gating circuit of a semiconductor integrated circuit device.

As the semiconductor manufacturing process enters a micro process (eg, several tens of nm), the leakage current of a semiconductor integrated circuit device increases exponentially. Various techniques have been proposed for reducing leakage current of semiconductor integrated circuit devices. Among them, power gating is a recently developed efficient leakage current reduction technology.

In a power gating circuit, a sleep transistor is used as a switch to cut off power supply to a logic block in a standby state. Therefore, leakage current is fundamentally blocked.

1 is a circuit diagram showing a general power gating circuit.

Referring to FIG. 1, a general power gating circuit 100 includes two PMOS transistors M1 and M2, a capacitor C, and a controller 110. Also shown is a logic block 200 that is supplied with an external power source VDD by the power gating circuit 100.

Two transistors M1 and M2 in the power gating circuit 100 are connected in series. The capacitor C is connected to the node Vx between the transistors M1 and M2. The capacitor C may be a general capacitor or a metal to metal (MTM) capacitor. This structure is called a header.

On the other hand, the structure in which the transistors are located between the logic block and the ground terminal is called a footer. In the power gating circuit of the footer structure, an NMOS transistor is used as the switch transistor to selectively connect the ground voltage to the logic block.

The power gating circuit may be composed of a header structure or a footer structure, or may be configured to simultaneously include a header structure and a footer structure.

In the case of the footer structure, an NMOS transistor is used instead of the PMOS transistor. The header structure selectively supplies an external power supply VDD to the logic block, whereas the footer structure selectively supplies a ground voltage GND to the logic block.

Since the basic principles of these two structures are the same, a detailed description of the footer structure is omitted for the sake of brevity. Hereinafter, a power gate circuit having a header structure will be described.

1, when a command CMD is input to cut off power supply to the logic block 200 from the outside, the controller 110 applies control signals WAKEUP_1 and WAKEUP_2 to transmit the transistors M1. , M2) is turned off. Specifically, the controller 110 applies control signals WAKEUP_1 and WAKEUP_2 having a logic low value to the transistors M1 and M2.

Since the transistors M1 and M2 are turned off, the voltage of the node Vx should not change. In practice, however, the voltage drops due to the current leaking into the logic block 200. On the other hand, since the substrate of the transistor M2 is connected to the external power source VDD, the substrate maintains a constant voltage VDD.

While the substrate voltage of the transistor M2 is constant at VDD, the source-to-source voltage increases because the source voltage decreases. This raises the threshold voltage of the transistor M2. This phenomenon is called the body effect.

The raised threshold voltage limits the current flowing through transistor M2 to reduce the current leaking into logic block 200.

Thus, the general power gating circuit 100 not only supplies power to the inoperative logic block 200 but also effectively reduces the current leaking into the logic block 200.

On the other hand, the above-mentioned body effect occurs even when the semiconductor integrated circuit device operates normally. When the semiconductor integrated circuit device is in the standby mode, the leakage current can be reduced by the body effect, but when the semiconductor integrated circuit device is operating in the normal mode, the semiconductor integrated circuit is caused by the body effect. The performance (specifically, reaction rate) of the apparatus is lowered.

Therefore, when the semiconductor integrated circuit device does not operate, a body effect is used to reduce leakage current, and when the semiconductor integrated circuit device operates in a normal mode, a body effect does not occur. Power gating circuitry is required.

It is an object of the present invention to provide a power gating circuit in which performance degradation due to a body effect does not occur when a semiconductor integrated circuit device operates in a normal mode.

Exemplary embodiments of the present invention provide a power gating circuit for selectively supplying external power to a logic block, comprising: first and second transistors connected in series between the external power source and the logic block; A capacitor having one end connected to a connection terminal of the first and second transistors and the other end grounded; And a substrate voltage control circuit for controlling the substrate voltage of the second transistor in accordance with an operation mode, wherein the substrate voltage control circuit supplies the substrate of the second transistor to the external power source when the logic block operates in a standby mode. And the substrate of the second transistor is connected to a source terminal when operating in the normal mode.

In an exemplary embodiment, the first and second transistors are PMOS transistors.

Another exemplary embodiment of the present invention provides a power gating circuit for selectively supplying a ground voltage to a logic block, comprising: first and second transistors connected in series between the ground voltage and the logic block; A capacitor having one end connected to a connection terminal of the first and second transistors and the other end grounded; And a substrate voltage control circuit configured to control the substrate voltage of the second transistor according to an operation mode, wherein the substrate voltage control circuit supplies the substrate of the first transistor to the ground voltage when the logic block operates in a standby mode. And the substrate of the first transistor is connected to the drain terminal when operating in the normal mode.

In an exemplary embodiment, the first and second transistors are NMOS transistors.

Still another exemplary embodiment of the present invention provides a power gating circuit for selectively supplying an external power source to a logic block, comprising: a first transistor coupled to the external power source; A second transistor coupled between the first transistor and the logic block; A capacitor having one end connected to a connection terminal of the first and second transistors and the other end grounded; A third transistor connected between the connection terminal of the first and second transistors and the substrate of the second transistor; A fourth transistor connected between the external power supply and the substrate of the second transistor; And a controller for controlling the first to fourth transistors in response to a command from the outside.

In an exemplary embodiment, when the command from the outside instructs the logic block to operate in the normal mode, the controller turns on the first to third transistors and turns off the fourth transistor. It is characterized by.

In an exemplary embodiment, the capacitor is a metal to metal (MTM) capacitor.

A first voltage generating circuit for generating a voltage lower than a connection terminal voltage of said first and second transistors; A second voltage generator circuit for generating a voltage higher than a connection terminal voltage of the first and second transistors; A fifth transistor connected between the substrate of the second transistor and the first voltage generation circuit and controlled by the controller; And a sixth transistor connected between the substrate of the second transistor and the second voltage generator circuit and controlled by the controller.

In an exemplary embodiment, when the command from the outside directs the logic block to operate in a high speed mode, the controller turns on the first transistor, the second transistor, and the fifth transistors, And turning off the third transistor, the fourth transistor, and the sixth transistor.

In an exemplary embodiment, when the command from the outside instructs the logic block to operate in a power saving mode, the controller turns on the first transistor, the second transistor, and the sixth transistors, And turning off the three transistors, the fourth transistor, and the fifth transistors.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and that additional explanations of the claimed invention are provided.

Reference numerals are shown in detail in preferred embodiments of the invention, examples of which are shown in the reference figures. In any case, like reference numerals are used in the description and the drawings to refer to the same or like parts.

In the following, a semiconductor integrated circuit device is used as an example for explaining the features and functions of the present invention. However, one of ordinary skill in the art will readily appreciate the other advantages and performances of the present invention in accordance with the teachings herein, and the present invention may also be implemented or applied through other embodiments. In addition, the detailed description may be modified or changed according to aspects and applications without departing from the scope, technical spirit and other objects of the present invention.

2, the power gating circuit 300 according to the present invention includes four PMOS transistors M1, M2, M3, and M4, a capacitor C, and a controller 310.

In the embodiment of the present invention, the two transistors M3 and M4 and the capacitor C constitute a substrate voltage generation circuit.

When a command CMD is input to block power supply to the logic block 200 from the outside, the power gating circuit 300 does not supply the external power VDD to the logic block 200.

In detail, the controller 310 turns off the transistors M1, M2, and M3 by applying control signals WAKEUP_1, WAKEUP_2, and ACTIVE having a logic high value. The transistor M4 is turned on by the control signal STANDBY having a logic low value.

Since the transistors M1 and M2 are turned off, the external power supply VDD is not supplied to the logic block 200. Since the transistor M4 is turned on, the substrate voltage of the transistor M2 becomes equal to the external power supply VDD.

As a result, the substrate voltage of the transistor M2 is constant at VDD, while the source voltage is lowered to increase the substrate-to-source voltage. This causes a body effect to increase the threshold voltage of the transistor M2, and reduce the current leaking through the transistor M2 into the logic block 200. FIG.

Therefore, a body effect may be used to effectively reduce the current leaking into the logic block 200.

When a command CMD is input to supply power to the logic block 200 from the outside, the power gating circuit 300 supplies the external power VDD to the logic block 200.

In detail, the controller 310 turns on the three transistors M1, M2, and M3 by applying control signals WAKEUP_1, WAKEUP_2, and ACTIVE having a logic low value. The transistor M4 is turned off by the control signal STANDBY having a logic high value.

Since the transistors M1 and M2 are turned on, the external power source VDD is supplied to the logic block 200. In addition, since the transistor M4 is turned off, the external power supply VDD is not supplied to the substrate of the transistor M2.

On the other hand, since the transistor M3 is turned on, the source of the transistor M2 is connected to the substrate. Therefore, since the substrate voltage and the source voltage are the same, a body effect does not occur. This means that the increase in the threshold voltage of the transistor M2 is suppressed.

As a result, when the semiconductor integrated circuit device operates in the normal mode, since the body effect does not occur, the semiconductor integrated circuit device may operate at a high speed.

Referring to FIG. 3, the power gating circuit 400 according to the present invention includes six PMOS transistors M1, M2, M3, M4, M5, and M6, a capacitor C, a controller 410, and a forward bias generation circuit. 420, and a reverse bias generation circuit 430.

This further includes two transistors M5 and M6 and two bias generation circuits 420 and 430 in the embodiment shown in FIG. 2. The two transistors M5 and M6 and two bias generation circuits 420 and 430 that are further included allow the power gating circuit 400 to operate at lower power or to operate faster.

When the semiconductor integrated circuit device operates in the standby mode, the power gating circuit 400 does not supply an external power supply VDD to the logic block 200.

In detail, the controller 410 turns off the transistors M1, M2, M3, M5, and M6 by applying control signals WAKEUP_1, WAKEUP_2, ACTIVE, FAST, and LOWPOWER having logic high values. The transistor M4 is turned on by the control signal STANDBY having a logic low value.

Since only transistor M4 is turned on, it is possible to reduce leakage current by using a body effect as in the standby mode in the embodiment shown in FIG.

When the semiconductor integrated circuit device operates in the normal mode, the power gating circuit 400 supplies an external power source VDD to the logic block 200.

In detail, the controller 410 turns on the transistors M1, M2, and M3 by applying control signals WAKEUP_1, WAKEUP_2, and ACTIVE having a logic low value. The transistors M4, M5, and M6 are turned off by the control signals STANDBY, FAST, and LOWPOWER having a logic high value.

Since the transistors M1, M2, M3 are turned on, a body effect does not occur as in the normal mode in the embodiment shown in FIG. Therefore, the performance degradation of the semiconductor integrated circuit device due to the body effect does not occur.

Technical features of the power gating circuit 400 shown in FIG. 3 are in a high speed mode and a power saving mode which will be described later. Here, the high speed mode refers to a mode in which the semiconductor integrated circuit device responds at high speed, and the power saving mode refers to a mode in which power consumed by the semiconductor integrated circuit device is reduced.

In order for the power gating circuit 400 to have a fast response speed, the threshold voltage of the transistor in the power gating circuit 400 is required to be low.

The threshold voltage is proportional to the substrate-to-source voltage of the transistor. For example, as the substrate-to-source voltage decreases, so does the threshold voltage.

The substrate voltage may be determined by connecting a separate voltage source 420 to the substrate of the transistor M2. Since the gate voltage is required for the power gating circuit 400 to have a fast response speed, a separate voltage source 420 may be set to output a voltage lower than the source voltage Vx of the transistor M2.

In detail, the controller 410 turns on the transistors M1, M2, and M5 by applying control signals WAKEUP_1, WAKEUP_2, and FAST having a logic low value. Transistors M3, M4, and M6 are turned off by control signals ACTIVE, STANDBY, and LOWPOWER having a logic high value.

Since the transistors M1 and M2 are turned on, the external power source VDD is supplied to the logic block 200. Since the transistor M5 is turned on, the output from the forward bias generator 420 is applied to the substrate of the transistor M2. In this case, the forward bias generator 420 will output a voltage lower than the source voltage Vx of the transistor M2.

As a result, the threshold voltage of the transistor M2 is lowered, thereby enabling the power gating circuit 400 to operate quickly.

When current flows through the power gating circuit 400, power consumption by the self-resistance of the power gating circuit 400 occurs. In addition, power consumption due to leakage current into the logic block 200 also occurs. Therefore, in order to reduce power consumed by the power gating circuit 400, the amount of current flowing through the power gating circuit 400 must be reduced.

As the threshold voltage of the transistor in the power gating circuit 400 increases, the amount of current flowing through the power gating circuit 400 may be reduced.

The threshold voltage is proportional to the substrate-to-source voltage of the transistor. For example, as the substrate-to-source voltage increases, the dress voltage also increases.

Therefore, a separate voltage source 430 may be connected to the substrate of the transistor M2 to determine the substrate voltage. In order to reduce the leakage current from the power gating circuit 400, the threshold voltage of the transistor is required to be high, so a separate voltage source 430 may be set to output a voltage higher than the source voltage Vx of the transistor M2. .

In detail, the controller 410 turns on the transistors M1, M2, and M6 by applying control signals WAKEUP_1, WAKEUP_2, and LOWPOWER having a logic low value. The transistors M3, M4, and M5 are turned off by the control signals ACTIVE, STANDBY, and FAST having a logic high value.

Since the transistors M1 and M2 are turned on, the external power source VDD is supplied to the logic block 200. Since the transistor M6 is turned on, the output from the reverse bias generator 430 is applied to the substrate of the transistor M2. In this case, the substrate voltage of the transistor M2 will have a higher value than the source voltage Vx.

As a result, the leakage voltage of the power gating circuit 400 is reduced by increasing the threshold voltage of the transistor M2.

Through the above-described method, the power gating circuit 400 may be operated at high speed or low power as needed.

When the semiconductor integrated circuit device is in the standby mode, only the transistor M4 is turned on. The remaining transistors M1, M2, M3, M5, and M6 are turned off.

When the semiconductor integrated circuit device is in the normal mode, the transistors M1, M2, M3 are turned on. The remaining transistors M4, M5 and M6 are turned off.

When the semiconductor integrated circuit device is in the high speed mode, the transistors M1, M2, M5 are turned on. The remaining transistors M3, M4 and M6 are turned off.

When the semiconductor integrated circuit device is in the power saving mode, the transistors M1, M2, and M6 are turned on. The remaining transistors M3, M4 and M5 are turned off.

Accordingly, the operation modes of the power gating circuit 400 may be determined by controlling the transistors M1, M2, M3, M4, M5, and M6 in the power gating circuit 400.

Referring to FIG. 5, it can be seen that when the external power source VDD is input, the output VVDD of the general power gating circuit 100 is slower than the output VVDD of the power gating circuit 400 according to the present invention. Can be.

The power gating circuit 400 according to the present invention operates at a higher speed than the normal power gating circuit 100 in the normal mode and the high speed mode.

It will be apparent to those skilled in the art that the structure of the present invention may be variously modified or changed without departing from the scope or technical spirit of the present invention. In view of the foregoing, it is believed that the present invention includes modifications and variations of this invention provided they come within the scope of the following claims and their equivalents.

As described above, it is possible to operate the semiconductor integrated circuit device at a high speed by suppressing the generation of a body effect when the semiconductor integrated circuit device operates in the normal mode.

Claims

In a power gating circuit that selectively supplies external power to a logic block:

First and second transistors connected in series between the external power supply and the logic block;

A capacitor having one end connected to a connection terminal of the first and second transistors and the other end grounded; And

A substrate voltage control circuit for controlling the substrate voltage of the second transistor according to an operation mode,

The substrate voltage control circuit connects the substrate of the second transistor to the external power source when the logic block is operated in a standby mode, and connects the substrate of the second transistor to a source terminal when the logic block is operated in a normal mode. Power gating circuit, characterized in that.

The method of claim 1,

And the first and second transistors are PMOS transistors.

In a power gating circuit that selectively supplies a ground voltage to a logic block:

First and second transistors connected in series between the ground voltage and the logic block;

The substrate voltage control circuit connects the substrate of the first transistor to the ground voltage when the logic block operates in a standby mode, and connects the substrate of the first transistor to a drain terminal when operating in a normal mode. Power gating circuit, characterized in that.

The method of claim 3, wherein

And the first and second transistors are NMOS transistors.

A first transistor connected to the external power source;

A second transistor coupled between the first transistor and the logic block;

A capacitor having one end connected to a connection terminal of the first and second transistors and the other end grounded;

A third transistor connected between the connection terminal of the first and second transistors and the substrate of the second transistor;

A fourth transistor connected between the external power supply and the substrate of the second transistor; And

And a controller for controlling the first to fourth transistors in response to a command from the outside.

The method of claim 5, wherein

If the instruction from the outside instructs the logical block to operate in a normal mode,

And the controller turns on the first to third transistors and turns off the fourth transistor.

The method of claim 5, wherein

And the capacitor is a metal to metal (MTM) capacitor.

The method of claim 5, wherein

A first voltage generator circuit for generating a voltage lower than a connection terminal voltage of the first and second transistors;

A second voltage generator circuit for generating a voltage higher than the connection terminal voltage of the first and second transistors;

A fifth transistor connected between the substrate of the second transistor and the first voltage generation circuit and controlled by the controller; And

And a sixth transistor coupled between the substrate of the second transistor and the second voltage generator circuit and controlled by the controller.

The method of claim 8,

If the instruction from the outside instructs the logical block to operate in a fast mode,

And the controller turns on the first transistor, the second transistor, and the fifth transistors, and turns off the third transistor, the fourth transistor, and the sixth transistors.

The method of claim 8,

If the instruction from the outside instructs the logical block to operate in a power saving mode,

And the controller turns on the first transistor, the second transistor, and the sixth transistors, and turns off the third transistor, the fourth transistor, and the fifth transistors.