KR20080080529A - Reverse coupling effect with timing information - Google Patents

Abstract

Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in neighboring floating gates (or other neighboring charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of a neighbor memory cell if the neighbor memory cell was programmed subsequent to the given memory cell. Techniques for determining whether the neighbor memory cell was programmed before or after the given memory cell are disclosed.

Description

REVERSE COUPLING EFFECT WITH TIMING INFORMATION}

The technology described herein relates to nonvolatile memory.

Semiconductor memories are increasingly used in various electronic devices. For example, nonvolatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants (PDAs), mobile computing devices, nonvolatile computing devices, and other devices. Electrically erasable programmable read only memory (EEPROM) and flash memory are one of the most widely used nonvolatile semiconductor memories.

EEPROMs and flash memories utilize floating gates disposed over and insulated from channel regions within a semiconductor substrate. The floating gate is located between the source and drain regions. The control gate is provided above and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge retained on the floating gate. That is, the amount of minimum voltage that must be applied to the control gate before the transistor is turned on to allow conduction between its source and drain is controlled by the level of charge on the floating gate.

When programming an EEPROM or flash memory device, such as a NAND flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate is negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in a programmed state. More information about programming can be found in U.S. Patent No. 6,859,397 and U.S. Patent Application No. 10 / 629,068, filed "Detecting Over Programmed Memory," filed Jul. 29, 2003, all of which are incorporated by reference in their entirety. Incorporated herein.

Some EEPROM and flash memory devices have floating gates that are used to store two ranges of charges, so that memory cells can be programmed / erased between two states (erasure state and programming state). Such flash memory devices are sometimes referred to as binary flash memory devices.

Multi-state flash memory devices are implemented by identifying a plurality of individual allowable / effective programming threshold voltage ranges separated by a forbidden range. Each individual threshold voltage range corresponds to a predetermined value for the set of encoded data bits in the memory device.

A shift in the apparent charge stored on the floating gate can occur due to the coupling of the electric field based on charge stored near or near the floating gate. This floating gate to floating gate coupling phenomenon is described in US Pat. No. 5,867,429, which is hereby incorporated by reference in its entirety. Floating gates that can cause coupling to the target floating gate can include floating gates on the same bit line, floating gates on the same word line, or floating gates traversing from the target floating gate, because they are another bit. It is on the line and another word line.

Floating gate to floating gate coupling occurs most reliably between sets of memory cells that are programmed at different times. For example, a first memory cell is programmed to add a level of charge to the floating gate corresponding to a set of data. Subsequently, one or more neighboring memory cells are programmed to add a level of charge to the floating gate corresponding to the second set of data. After one or more neighboring memory cells have been programmed, the charge level read from the first memory cell appears to be different from programming because of the effect of the charge on neighboring memory cells connected to the first memory cell. Coupling from neighboring memory cells can shift the apparent charge level read by a sufficient amount so that the stored data can be read out in bulk.

The effect of floating gate to floating gate coupling is very important for multi-state devices because the threshold voltage range and forbidden ranges allowed in multi-state devices are narrower than in binary devices.

As memory cells continue to shrink in size, the natural programming and erase distribution of the threshold voltage is expected to increase due to short channel effects, larger oxide thickness / coupling ratio changes, and larger channel dopant variations. Available separation between states is expected to be reduced. This effect is much more important for multi-state memory than just two states (binary memory). Moreover, the reduction between the space between word lines and the space between bit lines also increases the coupling between adjacent floating gates.

To compensate for coupling between adjacent floating gates, the read process for a given memory cell takes into account the programming state of the neighboring memory cell if the neighboring memory cell is programmed subsequent to the given memory cell. Techniques for determining whether a neighbor memory cell has been programmed before or after given memory cells are disclosed.

One embodiment includes accessing stored timing information customized for a data set stored in one or more non-volatile storage elements, and from one or more storage elements. Reading the data set. Reading of the data includes selectively compensating for one or more potential errors in the data set based on the timing information.

One exemplary embodiment includes a plurality of nonvolatile storage elements, a set of word lines coupled to the nonvolatile storage elements, and one or more management circuits in communication with the nonvolatile storage elements. One or more management circuits program data to nonvolatile storage elements in an undefined word line order. This programming includes storing timing information for the data. One or more management circuits read data from the nonvolatile storage system, which indicates that the stored timing information indicates that the neighboring nonvolatile storage elements are potentially programmed later in time than the nonvolatile storage elements storing the data. Compensating for coupling between non-volatile storage elements.

1 is a top view of a NAND string.

2 is an equivalent circuit diagram of a NAND string.

3 is a cross-sectional view of a NAND string.

4 is a block diagram of a nonvolatile memory system.

5 is a block diagram of a nonvolatile memory array.

6 illustrates an exemplary set of threshold voltage distributions.

7 illustrates an exemplary set of threshold voltage distributions.

8A-C illustrate various threshold voltage distributions and illustrate the process of programming the nonvolatile memory.

9 is a flow chart describing one embodiment of a process for programming a nonvolatile memory.

10 is a flow chart describing one embodiment of a process for reading a nonvolatile memory.

11 is a block diagram illustrating one page (or other unit) of data.

12 is a flow chart describing one embodiment of a process for programming a nonvolatile memory.

13 is a flow chart describing one embodiment of a process for reading a nonvolatile memory.

14 is a flowchart illustrating one embodiment of a process for reading memory cells on a word line without using an offset to compensate for coupling.

15A is a flow diagram illustrating one embodiment of a process for reading memory cells on a word line using an offset to compensate for coupling.

15B is a flow diagram illustrating one embodiment of a process for reading memory cells on a word line using an offset to compensate for coupling.

16 is a block diagram illustrating one page (or other unit) of data.

17 is a chart illustrating history data.

18 is a flow chart describing one embodiment of a process for programming a nonvolatile memory.

19 is a flow chart describing one embodiment of a process for determining historical data.

20 is a flow chart describing one embodiment of a process for reading a nonvolatile memory.

21 is a flow diagram illustrating one embodiment of a process for performing a read operation that takes into account coupling from neighboring memory cells.

FIG. 22 is a flow diagram illustrating one embodiment of a process for performing a read operation that takes into account coupling from neighboring memory cells. FIG.

0037]

One example of a nonvolatile memory system suitable for implementing the present invention is to use a NAND flash memory structure, which includes aligning a plurality of transistors in series between two select gates. The transistors in series and the select gates are referred to as a NAND string. 1 is a top view showing one NAND string. 2 is an equivalent circuit thereof. The NAND string shown in FIGS. 1 and 2 includes four transistors 100, 102, 104 and 106 in series, which are sandwiched between the first select gate 120 and the second select gate 122. FIG. . Select gate 120 connects the NAND string to bit line contact 126. Select gate 122 connects the NAND string to source line contact 128. The select gate 120 is controlled by applying an appropriate voltage to the control gate 120CG. The select gate 122 is controlled by applying an appropriate voltage to the control gate 122CG. Each of transistors 100, 102, 104, and 106 has a control gate and a floating gate. Transistor 100 has control gate 100CG and floating gate 100FG. Transistor 102 has control gate 102CG and floating gate 102FG. Transistor 104 has control gate 104CG and floating gate 104FG. Transistor 106 has control gate 106CG and floating gate 106FG. Control gate 100CG is connected to word line WL3, control gate 102CG is connected to word line WL2, control gate 104CG is connected to word line WL1, and control gate 106CG ) Is connected to the word line WL0. In one embodiment, transistors 100, 102, 104, and 106 are respective memory cells. In other embodiments, the memory cells may include a plurality of transistors or may differ from those shown in FIGS. 1 and 2. The select gate 120 is connected to the select line SGD. The select gate 122 is connected to the select line SGS.

3 shows a cross-sectional view of the NAND string described above. As shown in FIG. 3, transistors of the NAND string are formed in the p-well region 140. Each transistor includes a stacked gate structure consisting of control gates IOOCG, 102CG, 104CG and 106CG and floating gates 100FG, 102FG, 104FG and 106FG. Floating gates are formed on the surface of the p-well on top of an oxide or other dielectric film. The control gate is above the floating gate, and an inter-polysilicon dielectric layer separates the control gate and the floating gate. The control gates of the memory cells 100, 102, 104, and 106 form a word line. N + doped layers 130, 132, 134, 136 and 138 are shared between neighboring cells, whereby the cells are connected in series to each other to form a NAND string. This N + doped layer forms the source and drain of each of the cells. For example, N + doped layer 130 serves as a drain of transistor 122, serves as a source for transistor 106, and N + doped layer 132 serves as a drain for transistor 106. And act as a source for transistor 104, N + doped layer 134 as a drain for transistor 104, as a source for transistor 102, and an N + doped layer ( 136 serves as a drain for transistor 102, serves as a source for transistor 100, and N + doped layer 138 serves as a drain for transistor 100, and transistor 120 ) Acts as a source. N + doped layer 126 is connected to the bit line for the NAND string, while N + doped layer 128 is connected to the common source line for the plurality of NAND strings.

It should be noted that while FIGS. 1-3 show four memory cells in a NAND string, the use of these four transistors is provided only as an example. The NAND string used using the techniques described herein may have fewer than four memory cells or may have more than four memory cells. For example, some NAND strings may include eight memory cells, sixteen memory cells, thirty-two memory cells, sixty-four memory cells, and the like. The description herein is not limited to any particular number of memory cells in the NAND string.

Each memory cell can store data in analog or digital form. When storing one bit of digital data, the range of possible threshold voltages of a memory cell can be divided into two ranges, which are allocated to logical data "1" and "0". In one example of a NAND flash memory, the voltage threshold is negative after the memory cell is erased and defined as logic "1". The threshold voltage is positive after a program operation and defined as logic "0". When the threshold voltage is negative and a read is attempted by applying 0 volts to the control gate, the memory cell is turned on to indicate that the logic work has been stored. When the threshold voltage is positive and a read operation is attempted by applying 0 volts to the control gate, the memory cell is not turned on, indicating that logic zero is stored.

The memory cell can also store multiple states, thereby storing multiple bits of digital data. In the case of storing data of multiple states, the threshold voltage window is divided into many states. For example, if four states are used, there may be four threshold voltage ranges assigned to the data values "11", "10", "01" and "00". In one example of a NAND-type memory, the threshold voltage after the erase operation is negative and defined as "11". Positive threshold voltages are used for the states of "10", "01" and "00". In some embodiments, a data value (e.g., logical state) is assigned to a threshold range using gray code assignment so that only one bit, even if the threshold voltage of the floating gate shifts significantly to its neighboring physical state. get affected. The specific relationship between the data programmed into the memory cell and the threshold voltage range of the cell depends on the data encoding scheme employed by the memory cell. For example, US Patent No. 6,222,762 and US Patent Application No. 10 / 461,244, entitled "Tracking Cells For A Memory System", filed June 13, 2003, describe various data encoding schemes for multi-state flash memory cells. All of which are incorporated herein by reference in their entirety.

0042]

Relevant examples of NAND-type flash memories and their associated operations are provided in the following US patent / patent applications, all of which are incorporated herein by reference in their entirety, listing these, US Pat. No. 5,570,315, US Patent No. 5,774,397, US Patent No. 6,046,935, US Patent No. 5,386,422, US Patent No. 6,456,528, US Patent Application No. 09 / 893,277 (Publication US2003 / 0002348). Other types of nonvolatile memory in addition to NAND flash memory can also be used with the present invention.

Another type of memory cell usable in flash EEPROM systems uses nonconductive dielectric materials instead of conductive floating gates to store charge in a nonvolatile manner. Such cells are described in the paper "A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device" (Chen et al., IEEE Electron Device Letters, Vol. EDL-8, No. 3, March 1987, pp. 93-95). do. The triple layer formed of silicon oxide, silicon nitride, silicon oxide ("ONO") is sandwiched between the surface of the semi-conductive substrate over the memory cell channel and the conductive control gate. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a restricted region. The stored charge then changes the threshold voltage of a portion of the channel of the cell in a detectable manner. This cell is erased by injecting hot holes into the nitride. In addition, the article "A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application" (author: Nozaki et al., IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501) For reference, this paper describes a similar cell in a split-gate configuration, where the doped polysilicon gate extends beyond a portion of the memory cell channel to form individual select transistors. The previous two articles are incorporated herein by reference in their entirety. The programming techniques mentioned in section 1.2 of the article "Nonvolatile Semiconductor Memory Technology" (author: William D. Brown and Joe E. Brewer, IEEE Press, 1998) are also described in that section to be applicable to dielectric charge-trapping devices. This article is also incorporated herein by reference. In the memory cells described in this paragraph, there may also be coupling between neighboring memory cells. Thus, the techniques described herein also apply to coupling between dielectric regions of other memory cells.

Another approach for storing two bits in each cell is described in the paper "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell" by Eitan et al., IEEE Electron Device Letters, vol. 21, no. November 2000, pp. 543-545. The ONO dielectric layer extends across the channel between the source and drain diffusions. Charge for one data bit is localized to the dielectric layer adjacent to the drain, and charge for another data bit is localized to the dielectric layer adjacent to the source. Multi-state data storage is obtained by individually reading the binary states of the spatially separated charge storage regions in the dielectric. The memory cells described in this paragraph can also be used with the present invention.

4 is a block diagram of one embodiment of a flash memory system. The memory cell array 202 is connected to a column control circuit 204, a row control circuit 206, a c-source control circuit 210, and a p-well control circuit 208. Is controlled by The column control circuit 204 is connected to the bit lines of the memory cell array 202 to read data stored in the memory cells, determine the state of the memory cells during a programming operation, and to facilitate or inhibit programming. Controls the potential level of the bit line. The row control circuit 206 is connected to the word lines to select one of the word lines, apply a read voltage, apply a program voltage, and apply an erase voltage. For example, program voltage levels used in EPROM and flash memory circuits are higher than voltages normally used in memory circuits. They are often higher than the voltage supplied to the circuit. This higher voltage is preferably produced by a charge pump (or elsewhere) in the row control circuit 206, which for example dumps charge into essentially capacitive wordlines. to charge to a higher voltage. The charge bumps receive an input at voltage V _in and provide a higher voltage V _out by gradually boosting the input voltage in a series of voltage multiplier stages. The voltage output is supplied to a load, for example a word line of the EPROM memory circuit. In some embodiments, there is a feedback signal from the load to the charge bumps. Prior art bumps are turned off in response to a signal indicating that the load has reached a predetermined voltage. Alternatively, a shunt is used to prevent overcharging when the load reaches a predetermined voltage. However, this consumes more power and is not desirable in low power applications. More information about charge bumps is described in US Pat. No. 6,734,718, which is incorporated herein by reference in its entirety.

The C-source control circuit 210 controls a common source line (labeled "C-source" in FIG. 5) connected to the memory cell. P-well control circuit 208 controls the p-well voltage.

Data stored in the memory cell is read by the column control circuit 204 and output to the external I / O line through the data input / output buffer 212. Program data to be stored in the memory cell is input to the data input / output buffer 212 via an external I / O line, and transferred to the column control circuit 204. An external I / O line is connected to the controller 218.

Command data for controlling the flash memory device is input to the controller 218. Command data tells Flash memory what action is required. The input command is passed to the state machine 216, which is the column control circuit 204, the row control circuit 206, the c-source control 210, the p-well control circuit 208 and the data input / output buffer. Control 212. The state machine 216 may also output state data in flash memory, such as READY / BUSY or PASS / FAIL. In some embodiments, state machine 216 manages a programming process, a verification process, and a read process, including the processes described in the flowcharts described below.

The controller 218 may or may be connected to a host system such as a personal computer, digital camera, PDA, or the like. The controller 218 communicates with a host to receive commands from the host, to receive data from the host, to provide data to the host, and to provide status information to the host. The controller 218 converts a command from the host into a command signal, which can be interpreted and executed by the command circuit 214, which communicates with the state machine 216. do. Controller 218 typically includes buffer memory for user data written to or read from the memory array. In some embodiments, the programming process may be managed by a controller.

One example memory system includes one integrated circuit that includes a controller 218, and one or more integrated circuits each including a memory array and its associated circuits, input / output and state machine circuits. Includes a chip. BACKGROUND OF THE INVENTION In recent years, the integration of controller circuits of memory arrays and systems into one or more integrated circuit chips is a recent trend. The memory system may be embedded as part of the host system or may be included in a memory card (or other package) removably inserted into the host system. Such a removable card may include an entire memory system (eg, including a controller) or may simply include a memory array (s) and its associated peripheral circuitry (controller is embedded in the host). Thus, the controller (or control capability) can be embedded in the host or included in a removable memory system.

In some embodiments, some of the components of FIG. 4 may be combined. In various designs, one or more components of FIG. 4, other than memory cell array 202, may be considered as management circuitry (alone or in combination). For example, the one or more management circuits may include any one or combination of command circuits, state machines, row control circuits, column control circuits, well control circuits, source control circuits, or data I / O circuits. have.

5, an exemplary structure of the memory cell array 202 is described. For example, a NAND flash EEPROM is described that is divided into 1,024 blocks. Data stored in each block is erased at the same time. In one embodiment, a block is the smallest unit of cells that are simultaneously erased. In this example, each block has 8,512 columns divided into even columns and odd columns. The bit line is also divided into even bit lines (BLe) and odd bit lines (BLo). 5 shows four memory cells connected in series to form a NAND string. Although four cells are shown to be included in each NAND string, more or fewer memory cells than four memory cells may be used. One terminal of the NAND string is connected to the corresponding bit line through the select transistor SGD, and the other terminal is connected to the c-source through the second select transistor SGS.

During one embodiment of the read and program operations, 4,256 memory cells are selected at the same time. The selected memory cells have the same word line and the same kind of bit line (eg, even bit lines or odd bit lines). Thus, 532 bytes of data can be read or programmed simultaneously. Simultaneously read or programmed 532 bytes of data form a logical page. Thus, one block can store at least eight logical pages (four word lines, each with odd pages and even pages). When each memory cell stores two bits of data (eg, a multi-state memory cell), where each of these two bits is stored in a different page, one block stores 16 logical pages. Other sized blocks and pages may also be used with the present invention. In addition, other architectures than FIGS. 4 and 5 may also be used to implement the present invention. For example, in one embodiment, the bit lines are not divided into odd bit lines and even bit lines so that all bit lines are programmed and read at the same time (or not simultaneously programmed and read).

Memory cells are erased by raising the p-well to an erase voltage (eg, 20 volts) and grounding the word line of the selected block. The source and bit lines are plotted. Erasing the entire memory array, individual blocks, or cells on another unit may be performed. Electrons are transferred from the floating gate to the p-well region, and the threshold voltage becomes negative (in one embodiment).

In read and verify operations, the select gates SGD and SGS and the unselected word lines (e.g., WLO, WL2, and WL3) are raised to a read pass voltage (e.g., 4.5 volts) such that the transistor operates as a pass gate. Do it. The select word line (eg, WL1) is connected to a constant voltage, and the level of this voltage is applied to each read and verify operation to determine whether the threshold voltage of the corresponding memory cell is above or below this level. Is specified. For example, in a read operation on two levels of memory cells, the selected word line WL1 may be grounded, so it is detected whether the threshold voltage is higher than 0V. In the verify operation for two levels of memory cells, the select word line WL1 is connected to 0.8V, for example, so that it is verified whether or not the threshold voltage has reached at least 0.8V. The source and p-well are at zero volts. The selected bit line BLe is precharged to a certain level, for example 0.7V. If the threshold voltage is higher than the read or verify level on the word line, the potential level of the bit line BLe associated with that cell remains high because of the non-conductive memory cell. On the other hand, if the threshold voltage is lower than the read or verify level, the potential level of the corresponding bit line BLe decreases to a lower level, for example less than 0.5V, which causes the conductive memory cell to discharge the bit line. Because it is. As a result, the state of the memory cell is detected by a voltage comparator sense amplifier connected to the bit line.

The erase, read, and verify operations described above are performed in accordance with known techniques. Accordingly, many of the described things can be variously modified by those skilled in the art. Other erase, read and verify techniques known in the art may also be used.

As described above, each block can be divided into several pages. In one embodiment, a page is a unit of programming. In some embodiments, individual pages may be divided into segments, which may include the smallest number of cells written at a time in a basic programming operation. One or more pages of data are typically stored in one row of memory cells. A page can store one or more sectors. A sector includes user data and overhead data. Overhead data typically includes an Error Correction Code (ECC), which is calculated from the user data of the sector. Some of the controllers calculate the ECC to be programmed into the array and also check this when the data is read from the array. Alternatively, ECC and / or other overhead data is stored on a different page, or even on a different block than the user data to which they belong. In other embodiments, other portions of the memory device (eg, state machine) may calculate the ECC.

A sector of user data is typically 512 bytes, which corresponds to the size of a sector in a magnetic disk drive. Overhead data is typically an additional 16-20 bytes. Many pages form blocks, which in some cases can be from eight pages, for example up to 32 or 64 or more pages.

Figure 6 shows the threshold voltage distribution for a memory cell array when each memory cell stores two bits of data. 6 shows a first threshold voltage distribution for an erased memory cell. Three threshold voltage distributions A, B, and C for programmed memory cells are also shown. In one embodiment, the threshold voltages in the E distribution are negative, and the threshold voltages in the A, B, and C distributions are positive.

Each distinct threshold voltage range of FIG. 6 corresponds to a predetermined value for the set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage level of the cell depends on the data encoding scheme adopted for the cell. One example assigns "11" to threshold voltage range E (state E), assigns "10" to threshold voltage range A (state A), and assigns "00" to threshold voltage range B (state B). And assign "01" to the threshold voltage range C (state C). However, in other embodiments, other approaches are used.

6 also shows three read reference voltages Vra, Vrb and Vrc for reading data from a memory cell. By testing whether the threshold voltages of a given memory cell are above or below Vra, Vrb and Vrc, the system can determine what state the memory cell is in. 6 also shows three verification reference voltages Vva, Vvb and Vvc. When programming the memory cells to state A, the system tests whether these memory cells have a threshold voltage greater than Vva or the same threshold voltage as Vva. When programming the memory cells to state B, the system tests whether the memory cells have a threshold voltage greater than Vvb or the same threshold voltage as Vvb. When programming the memory cells to state C, the system determines whether the memory cells have a threshold voltage greater than Vvc or a threshold voltage equal to Vvc.

In one embodiment, known as full sequence programming, a memory cell can be programmed directly from erased state E to any of programmed states A, B or C (indicated by the curved arrows). For example, the group of memory cells to be programmed is first erased, so all memory cells in the group are in the erased state E. Some memory cells are also programmed from state E to state A, and other memory cells are programmed from state E to state B and / or from state E to state C.

7 shows an example of a two-pass technique for programming a multi-state memory cell that stores data for two different pages (lower page and upper page). Four states are shown. State E (11), State A (10), State B (00), and State C (01). For state E, both pages store "1". For state A, the lower page stores "0" and the upper page stores "1". For state B, both pages store a "0". For state C, the lower page stores "1" and the upper page stores "0". Note that although a specific bit pattern is assigned to each state, different bit patterns may also be assigned. In the first programming pass, the threshold voltage level of the cell is set in accordance with the bit to be programmed into the lower logical page. If this bit is a logic "1", the threshold voltage is not changed because it is in the proper state as a result of the initial erase. However, if the bit to be programmed is a logic "0", then the threshold level of the cell increases to state A, as shown by arrow 230. This ends the first programming with a pass.

In the second programming pass, the threshold voltage level of the cell is set according to the bit programmed into the upper logical page. If the upper logical page bit has to store logic "1", no programming takes place because the cell is in either state E or A, which depends on the programming of the lower page bit, all of which are "1". With the upper page bit of ". If the upper page bit should be a logic "0", the threshold voltage is shifted. If the cell stays in the erased state E as a result of the first pass, then in the second step the cell is programmed so that the threshold voltage increases to be in state C as shown by arrow 234. If the cell is programmed to state A as a result of the first programming pass, the memory cell is further programmed into the second pass so that the threshold voltage is increased to be in state B as shown by arrow 232. The result of the second pass is to program the cell in the specified state to store logic "0" for the upper page without changing the data for the lower page.

In one embodiment, if enough data is written to fill the entire page, the system may be configured to perform full sequence writing. If insufficient data is not written for the entire page, the programming process can program the lower page with the received data. When subsequent data is received, the system programs the upper page. In another embodiment, if enough data is subsequently received to fill the memory cells of the entire (or most) word line, the system will begin writing to the mode of programming the lower page to convert to full sequence programming mode. Can be. More details of this embodiment are disclosed in US patent application Ser. No. 11 / 013,125, entitled "Pipelined Programming of Non-Volatile Memories Using Early Data", Dec. 14, 2004, filed by Inventor Sergy Anatolievich Gorobets and Yan Li. Which is hereby incorporated by reference in its entirety.

8A-8C reduce floating gate to floating gate coupling for any particular memory cell by writing to that particular memory cell for a particular page after writing to adjacent memory cells for the previous page. Another process for programming nonvolatile memory is disclosed. In one example of the embodiment of the process described in FIGS. 8A-8C, nonvolatile memory cells store four bits of data per memory cell using four data states. For example, assume that state E is an erased state and states A, B, and C are programmed states. State E stores data 11. State A stores data 01. State B stores data 10. State C stores data 00. This is an example of non-gray coding, since both bits change between adjacent states A and B. Other encodings of the data into the physical data state can also be used. Each memory cell stores two data pages. For reference purposes, these data pages are referred to as top page and bottom page. However, they may have other names. Referring to state A for the process of Figure 8, the upper page stores bit 0, and the lower page stores bit 1. Referring to state B, the upper page stores bit 1, and the lower page stores bit 0. Referring to state C, both pages store bit data 0.

The programming process of FIGS. 8A-8C is a two step process. In the first step, the lower page is programmed. If the lower page must hold data 1, the memory cell state remains in state E. If the data must be programmed to zero, the threshold of the voltage of the memory cell is raised so that the memory cell is programmed to state B '. 8A shows the programming of a memory cell from state E to state B '. State B 'shown in Figure 8A is an interim state B. Therefore, the verification point is shown as Vvb 'lower than Vvb.

In one embodiment, after a memory cell is programmed from state E to state B1, its neighboring memory cells on an adjacent word line are programmed for the lower page. After programming of the neighboring memory cells, the floating gate to floating gate coupling effect raises the apparent threshold voltage of the corresponding memory cell in state B '. This has the effect of widening the width of the threshold voltage distribution for state B 'for what is shown as threshold voltage distribution 250 of FIG. 8B. This apparent widening of the threshold voltage distribution is healed when programming the upper page.

8C shows a process for programming the upper page. If the memory cell is in the erased state E, and the upper page should remain at 1, the memory cell remains in the state E. If the memory cell is in state E and its upper page data must be programmed to zero, the threshold voltage of the memory cell is raised so that the memory cell is in state A. If the memory cell is in the middle threshold voltage distribution 250 and the upper page data should stay at 1, then the memory cell is programmed to the final state B. If the memory cell is in the intermediate threshold voltage distribution 250 and the upper page data should be zero, the threshold voltage of the memory cell is raised so that the memory cell is in state C.

The process shown in FIGS. 8A-8C reduces the coupling effect of floating gate to floating gate because only upper page programming of neighboring memory cells affects the apparent threshold voltage of a given memory cell. An example of an alternative state coding is to move from distribution 250 to state C when the upper page data is 1 and to move to state B when the upper page data is zero. Although FIGS. 9A-9C provide examples for four data states and two data pages, the concepts illustrated in FIGS. 8A-8C are more or less than four states and a different number than two pages. It can be applied to other embodiments having. More details on the various programmatic and floating gate to floating gate couplings can be found in US patent application Ser. No. 11 / 099,133, entitled "Compensating For Coupling During Read Operations Of Non-Volatile Memory," filed Apr. 05, 2005. US Pat. No. 6,657,891 issued December 12, 2003, inventor: Shibata et al., All of which are incorporated herein by reference in their entirety.

As described above, neighboring memory cells can cause coupling that can affect the apparent threshold voltage of the memory cell. Neighboring memory cells can be on adjacent word lines, adjacent bit lines, non-adjacent but adjacent bit lines, or non-adjacent but adjacent word lines. The system determines neighboring floating memory cells by first determining whether there is a potential for coupling because the memory cell (or floating gate) being read is programmed before the neighboring memory cell (or floating gate) being programmed. Selectively compensates for coupling of the liver. If the memory cell to be read is programmed before the neighboring memory cell, a process that compensates for the coupling based on the level of programming of the neighboring memory cell can be used.

9 is a flow diagram illustrating one embodiment of a high level process for programming that includes using timing information. 10 is a flow diagram illustrating one embodiment of a process for reading using timing information programmed to determine whether there is potential for coupling and to selectively compensate based on it.

In step 300 of FIG. 9, a data write request is received. This request may be received at the controller, state machine, or another device. In response to this request, data (one or more information bits) is written to the flash memory array at step 302. In addition, timing information is stored at 304. Timing information is customized for the data written in step 302. In one embodiment, timing information is stored with the data stored at step 302. In another embodiment, the timing information is stored separately. Steps 302 and 304 may be performed simultaneously or separately (in any order). It should be noted that, in all of the flowcharts included herein, the order of the steps shown in the flowcharts is not necessarily fixed, and in many cases may be performed in other suitable orders.

There are many examples of timing information that can be used. In one embodiment, a time stamp is used. This time stamp may be an absolute time stamp read from the system clock for the host device. In yet another embodiment, the memory system may include an internal battery and may store its own clock. In another embodiment, a relative time stamp can be used. For example, the system can maintain a cycle count. The cycle count counts each programming cycle. This cycle count can be maintained by a state machine, a controller or another device. The cycle count may be stored as timing information at step 304. If the first set of data has a larger cycle count than the second set of data, the first set of data is programmed after the second set of data. Another embodiment of timing information may include an indication indicating whether data has been programmed before or after a neighboring memory cell.

10 provides a flow diagram illustrating a process for reading data. In step 340, a data read request is received by a controller, state machine, or other device. In step 342, timing information for the data is accessed. This is the timing information stored in step 304. In step 344, it is determined whether there is a potential for coupling based on the timing information accessed. In one embodiment, the system determines whether the timing information indicates that the memory cells that store data associated with the read request are programmed before neighboring memory cells. If so, there is a potential for coupling between memory cells. If the memory cells storing the data associated with the read request were programmed after programming neighboring cells, there would be no potential for coupling. If step 344 determines that there is a potential for coupling, then no actual coupling will be present if the level of programming of neighboring cells is not sufficient to produce the required coupling. If there is no potential for coupling (step 346), then in step 348 a read process is performed without consideration of the coupling. Note that the read process includes determining information stored in non-volatile memory and reporting this information. If it is determined that there is a potential for coupling (step 346), then in step 350 a read process is performed without consideration of potential coupling. In one embodiment, step 350 includes compensating the coupling if necessary. There are many other ways to compensate for coupling between memory cells. Any suitable manner can be used with the techniques described herein.

11 is a block diagram illustrating an embodiment of a data page. This data page includes a header 380, timing information 382, user data 384, and an error correction code (ECC) 386. Header information 380 may include any set of data known in the art to be used in the header. Some examples of header information may include address information, bit and / or sector mapping related information, a count of the number of writes to a sector, and the like. Other information may be stored in the header. Timing information 382 is the timing information stored in step 304. User data 384 includes the data written in step 302. ECC 366 includes error correction codes known in the art. Note that some write requests may require writing to multiple pages. In this case, one or more sets of timing information may be used.

12 is a flow diagram illustrating one embodiment of a process for writing data. The process of FIG. 12 is one embodiment for performing steps 302 and 304 of FIG. In step 402 of FIG. 12, the system selects an appropriate portion of memory for programming in response to receiving a data write request. This may include selecting blocks and / or pages and / or sectors for writing. In one embodiment, the process of FIG. 12 writes data to a page, which includes writing data to a memory cell connected to a common word line. In step 404, the selected portion of the memory is preprogrammed, which is provided for wear of the flash memory. All memory cells in a selected sector or page are programmed to the same threshold voltage range. Depending on the selection, step 404 may be selected. In step 406, the memory cells to be programmed are erased. For example, step 406 may include moving old memory cells to state E (see FIGS. 6-8). In some embodiments, step 406 also includes performing a soft programming process. During the erase process, it is also possible that some of the memory cells have a threshold voltage lowered to a value below distribution E (see FIGS. 6-8). The soft programming process applies a program voltage pulse to the memory cells, increasing them so that their threshold voltages are within the threshold voltage distribution E.

In step 408, the system requires a time stamp. This time stamp may be absolute time. For example, the memory system may request a date / time from the host through a controller. Alternatively, the memory system can include a battery and an internal clock so that the memory system can provide its time stamp. In yet another embodiment, the memory system may maintain a cycle count. Each time the system programs the page, the cycle count is incremented. The type stamp obtained in step 408 may be the current cycle count. While cycle counts do not provide absolute time, they provide relative time. Using the cycle counter, it is possible to determine which of the two or more pages has been programmed first.

In step 410, the data to be programmed is stored in appropriate latches / registers. In one embodiment, the process of FIG. 12 may be used to program one page of data. All of the memory cells being programmed are on the same word line. Each memory cell has its own bit line and a set of latches associated with that bit line. These latches store an indication of the data to be programmed for the associated memory cell. Step 410 also includes storing time stamp data in latches associated with the bit lines for the memory cell that stores the time stamp. In step 412, the magnitude of the first program pulse is set. In some embodiments, the voltage applied to the word line is a set of program pulses, the magnitude of each pulse increasing by a step size (eg, 2v-4v) from the previous pulse. In step 414, the Program Count (PC) is initially set to zero.

In step 416, program pulses are applied to the appropriate word line (s). In step 418, the memory cells on the word line (s) are verified to see if they have reached the target threshold voltage level. If all memory cells have reached the target threshold voltage level (step 420), the programming process completes successfully at step 422 (state = pass). If not all the memory cells have been verified, it is determined in step 424 whether the program count PC is less than 20 (or other appropriate value). If the program count is not less than 20, the programming process fails (step 426). If the program counter is less than 20, in step 428, the magnitude of the program voltage signal Vpgm increases by the step magnitude (e.g., 3v) during the next pulse, and the program counter PC increases. Note that these memory cells that have reached the target threshold voltage are locked from programming during the remainder of the current programming cycle. After step 428, the process of FIG. 12 continues at step 416, and the next program pulse is applied.

FIG. 13 provides an example of a process for reading data written in accordance with the process of FIG. 12 or another process. 13 is an embodiment of the process of FIG. 10. In step 500 of FIG. 13, a data read request is received. In step 502, a read process is performed for the requested page. In one embodiment, this includes reading data from a set of memory cells connected to the same word line. In some embodiments, each word line is two adjacent word lines (e.g., one word line above and one word line below, or one word line on the left and one word line on the right). Can have In step 504, one of the adjacent word lines is read. In step 506, another adjacent word line is read. In embodiments where the word line that stores the data contains only one adjacent word line, step 506 may be omitted. Note that steps 502, 504, and 506 include reading relevant timing information added to the user data. That is, the entire page shown in FIG. 11 is read out, and the page includes timing information 382. In the embodiment of FIG. 13, the timing information is some type of time stamp, such as absolute time or relative time (eg, cycle count). In step 508, it is determined whether there is a potential for coupling based on the comparison of the various time stamps. For example, if the time stamp for the word line being read is later than the time stamp of two adjacent word lines, the word line being read is considered to be programmed after two adjacent word lines and is also floating gate to floating. It is considered that there is no potential for gate coupling. If the time stamp of the word line being read is earlier than the time stamp for either of the two adjacent word lines, there is a potential for coupling. If there is no potential for coupling (step 510), the data read in step 502 is stored and reported to the user without considering any compensation for the coupling. If it is determined that there is a potential for coupling (step 510), an additional read process is performed in step 514 to compensate for the coupling.

14 is a flowchart illustrating one embodiment of a process for performing a read operation (see step 502 of FIG. 13) for a data page. The embodiment of FIG. 14 relates to reading a data page from a set of memory cells connected to a common word line. The particular embodiment of FIG. 14 relates to a multi-state memory that includes four states, such as states E, A, B, and C of FIGS. The technique of FIG. 14 is also applicable to other configurations. In step 540, a read reference voltage Vra is applied to the appropriate word line associated with the page. In step 542, the bit lines associated with the page are sensed to determine whether the addressed memory cells are conductive or not, depending on the Vra applied to their control gate. The bit line in the conductive state indicates that the memory cells are turned on. Thus, the threshold voltages of these memory cells are below Vra (eg, in state E). In step 544, the sensing result for the bit line is stored in the appropriate latch for the bit line. In step 546, a read reference voltage Vrb is applied to the word line associated with the page being read. In step 548, the bit line is sensed as described above, in step 550, the result is stored in an appropriate latch for the bit line, and in step 552, the read reference voltage Vrc is paged. Is applied to the word line associated with. In step 554, as described above, the bit line is sensed to determine which memory cell is in the conductive state. In step 556, the results from the sensing step are stored in the appropriate latch for the bit line. In step 558, a data value for each bit line is determined. For example, if the memory cell is in the conducting state at Vra, the memory cell is in state E. If the memory cell is in the conductive state in Vrb and Vrc but not in the conductive state in Vra, the memory cell is in state A. If the memory cell is in the conduction state at Vrc but not in the conduction state at Vra and Vrb, the memory cell is in state B. If the memory cell is not in a conductive state at Vra, Vrb or Vrc, the memory cell is in state C. In one embodiment, the data value is determined by the processing unit associated with the sense amplifier. In step 560, the determined data value is stored in an appropriate latch for each bit line, or otherwise used by a state machine, controller or other device. In other embodiments, sensing the various levels Vra, Vrb, and Vrc may occur in a different order.

15A provides a flow diagram describing one embodiment of a process for performing an additional read process that compensates for potential coupling. Thus, FIG. 15A provides one embodiment of step 514 of FIG. 13. The embodiment of FIG. 15A assumes that there is potential coupling from two neighboring word lines. In step 600, the system determines offsets based on each of the neighbors. There are many other types of offsets and there are many values for offsets that can be used. In one embodiment, if the neighbor memory cell is programmed to state A (see FIG. 6), the offset is 0.1 volts, if the neighbor memory cell is programmed to state B, the offset is 0.2 volts, and if the neighbor memory cell is If programmed in state C, the offset is 0.3 volts. In other embodiments, other values or schemes may be used. The system may read the values stored in the neighboring word lines at steps 504 and 506 and thus determine which offset to use. The system can determine a set of offsets for each of the neighboring word lines and then add the two offsets together. In this way there are six possible offsets.

For example, suppose a given memory cell has two neighbors. The first neighbor is programmed to state B. The second neighbor is programmed to state C. The offset from the first neighbor is then 0.2 volts, and the offset from the second neighbor is 0.3 volts. The total offset for a particular memory cell is 0.5 volts.

In other embodiments, there may be more or less than six potential offsets. In some embodiments, the offsets may include a zero volt offset. For example, a zero volt offset can be used when neighboring memory cells stay in state E.

In step 602 of FIG. 15A, these memory cells that do not receive any offsets store previous read data from step 502. For example, if the memory cell has neighbors in state E, no offset is used (or an Ov offset is used). In step 604 the read process is performed using a first offset with a read point. For example, the process of FIG. 14 may be performed. However, instead of using Vra, Vrb, and Vrc as read comparison points, the read process uses Vra + first offset, Vrb + first offset, and Vrc + first offset. In step 606, data for the bit line associated with the first offset is stored. That is, these memory cells having one neighbor in state E and another neighbor in state A have data stored from step 604. In step 608, a read process is performed using a second set of offsets with read compare points. For example, the process of FIG. 14 can be used with Vra + second offset, Vrb + second offset, and Vrc + second offset for read comparison points. In step 610, the bit lines associated with the second offset store the data from step 608. For example, such memory cells having one neighbor in state E and another neighbor in state B or both neighbors in state A store data from step 608. In step 612, a read process is performed using a third offset with a read compare point. In step 614, data is stored for these bit lines associated with the third offset. In step 616, a read process is performed using a fourth offset with a read compare point. In step 618, data from step 616 is stored for these bit lines associated with the fourth offset. In step 620, a read process is performed using a fifth offset with read compare points. In step 622, data is stored for these bit lines associated with the fifth offset. In step 624, a read process is performed using a sixth offset with read compare points. At step 626, data from step 624 is stored for these bit lines associated with the sixth offset. In one example, the first offset is 0.1 volts, the second offset is 0.2 volts, the third offset is 0.3 volts, the fourth offset is 0.4 volts, the fifth offset is 0.5 volts, and the sixth offset is 0.6 Bolts. More information on compensating coupling is described in US patent application Ser. No. 11 / 099,133, entitled "Compensating for Coupling During Read Operations On Non-Volatile Memory", Apr. 5, 2005, filed by Jian Chen. Which is hereby incorporated by reference in its entirety.

The process of FIG. 15A is performed when there is potential coupling from two neighbors. If at step 508 it is determined that there is potential coupling from only one neighbor, then at step 514 the process of FIG. 15B is performed. In step 630, the system determines offsets based on one neighbor. In step 632, previous read data for these bit lines that are not associated with any offset is stored in step 632. In step 634, a read process is performed using a first offset with read compare points. At step 636, data for these bit lines associated with the first offset is stored. In step 638, a read process is performed using a second offset with read compare points. In step 640, data for these bit lines associated with the second offset is stored. In step 642, a read process is performed using a third offset with read compare points. In step 644, data for these bit lines associated with the third offset is stored.

In another embodiment, rather than storing a time stamp, timing information is stored as an indication as to whether a particular page was programmed after, or potentially before, data on neighboring word lines (or other neighbors). . The only reason for this information is to know whether the page was potentially previously written because it is possible that the page is written while the neighbor is erased and the neighbor is never written.

16 provides another example of a data page. The page shown includes a header 650, timing information 652, user data 654, timing information 656, and ECC 658. The timing information 652 provides a history (HWL) for the previous word line. Timing information 656 provides a history (HNWL) for the next word line. With respect to timing information 652 and 656, with respect to timing information 652 and 656, it is not intended to describe the temporal or sequential meaning through use of the terms before and after. Rather, the previous or next is used to identify two different neighbors. For example, referring back to FIG. 5, the word line WL2 has at least two neighbors WL3 and WL1. For purposes of naming only, the neighboring word line closest to the source is referred to as the previous word line, and the neighboring word line closest to the drain is referred to as the next word line. Thus, for WL1, the previous word line is WL1 and the next word line is WL2. The techniques described herein that determine and compensate for the potential for coupling can be suitably used in conjunction with many other programming approaches, including those that program data in an undefined order. That is, in some embodiments, word lines are programmed from WL0 to WL3. In another embodiment, the system can randomly select word lines and program the word lines in any order. The techniques described herein can work with any embodiment.

17 is a chart illustrating data values that may be stored in HPWL 652 and HNWL 656. In one embodiment, the stored data includes two bits, namely 11, 10, and 00. If the HPWL 652 and the HNWL 656 store 11, the page, sector or word line that stores the history is erased. If HPWL 652 and HNWL 656 store 10, the word line that stores its history value is programmed before each neighboring word line. If HPWL 652 or HNWL 656 stores 00, each neighboring word line is programmed before the word line that stores history.

18 is a flow chart describing one embodiment of a process for programming the page shown in FIG. Steps 402-406 of FIG. 18 are the same as in FIG. 12. Step 680 includes reading the history for the previous word line and determining the HPWL. For example, if the word line WL2 of FIG. 5 is being programmed, the previous word line is WL1. Step 680 includes observing HNWL 656 for WL1 to see whether WLl has been erased (HNWL = 11) or programmed (eg, HNWL = 1O). Based on the HNWL for WL1, the system determines the HPWL 652 for WL2. In step 682, the system reads the history for the next line and determines the HNWL. For example, upon writing to WL2 in FIG. 5, the system first reads the HPWL of word line WL3 and based on it determines which value should be stored in HNWL for word line WL2. Data for programming the header 650, HPWL 652, user data 654, HNWL 656, and ECC 658 is stored in an appropriate latch for each of the bit lines in step 684. Steps 412-428 of FIG. 17 are the same as in FIG. 12.

19 is a flowchart illustrating one embodiment of a process for reading historical information from the next or previous word line and determining an appropriate HPWL or HNWL. For example, FIG. 19 provides one embodiment of step 680 or 682. In step 700, a read process is performed by applying the voltage Vra to the appropriate word line. In step 702, a bit line is detected to determine whether or not the memory cell is turned on. Step 702 only needs to be performed on these memory cells that store a history value (HPWL or HNWL). In another embodiment, step 702 is performed on all memory cells (or many other memory cell sets) connected to a word line. Note that if the history value is 11 (state E), the memory cell is turned on. If not, the memory cell storing the history is not turned on in response to Vra. If the memory cells storing the history are turned on, the memory cells connected to the neighboring word line are considered erased. Thus, current memory cells are potentially programmed before the neighboring word lines are being programmed. If the memory cells that store history are not turned on, the memory cells on the neighboring word line are considered to be already programmed, and the current word line is considered to be subsequently programmed to the neighboring word line to be programmed. The results from step 702 are stored in step 704. Based on whether the memory cells storing history information are turned on or turned off (step 706), an appropriate value is stored in history for the current word line. If the neighbor's history is 11, then at step 710 the value 10 is stored in the appropriate history value for the current word line, indicating that the current word line is programmed before the neighbor. If the history value for the neighbor is 10, 00 is stored for history on the current word line, indicating that the current word line is programmed after the neighbor.

20 is a flow chart describing one embodiment of a read process for reading data programmed in accordance with the process of FIG. Note that FIG. 20 is another embodiment of the process of FIG. 10. In step 800 of FIG. 20, a data read request is received. In step 802, a read process is performed on the word line without using any offset. For example, the process of FIG. 14 is performed. In step 804, history is accessed for the word line to be read. Note that in one embodiment, historical data is read as part of the read process of the entire page at step 802. This data is then accessed in step 804 by the processor, state machine, or the like. In other embodiments, historical data may be accessed before or after step 802. If HNWL or HPWL is 11 (step 806, if the page has erased data, then the erased data is reported in step 808. If both HNWL and HPWL are 00, the current page being read is both neighbors). It is considered to be programmed later, therefore, in step 810, the data is reported without coupling compensation, if HNWL = 00 and HPWL = 10 (step 812, couple from previous neighbor in step 814). An additional read operation is performed to compensate the ring, if HNWL = 10 and HPWL = 10, an additional read operation is performed to compensate for coupling from both neighbors at step 818. If HNWL = 10 and HPWL = 00 If yes, in step 816 an additional read operation is performed to compensate for the coupling from the next neighbor.

21 is a flow chart illustrating an example of a process for performing an additional read operation that compensates for coupling from one neighbor. For example, the process of FIG. 21 may be performed as part of step 814 or step 816 of FIG. 20. In step 904, data is read from a neighboring word line using the read comparison point Vra provided at the control gate or word line. In step 906, it is determined whether the entire word line or page has been erased. If all of the memory cells are in state E, all of the memory cells are turned on in response to Vra. If all memory cells are erased (step 906), then data is reported without performing any compensation of the coupling from the neighboring word lines in step 908. If the neighboring word lines are not erased (step 906), the read process continues with the read operation using the read compare point Vrb and the read operation using the compare point Vrc (step). (910)). Based on the three read operations, the data stored in the neighbor can be determined (see the description of FIG. 14). After step 910, an additional read process is performed to compensate for potential coupling in accordance with the data stored in the neighborhood. For example, the process of FIG. 15B can be performed.

22 is a flow diagram illustrating one embodiment of a process for performing an additional read operation that takes into account coupling from two neighbors. For example, the process of FIG. 22 may be performed as part of step 818 of FIG. 20. In step 930, both neighboring word lines are read using the read comparison point Vra. If both neighbors are determined to be erased (step 932), then at step 934, data is reported without coupling compensation. If one neighbor is determined to be erased (e.g. one neighbor word line or page has all of the memory cells turned on, while the other neighbor does not have all of the memory cells turned on in response to Vra) In step 950, one neighbor is subject to a read process performed using the read comparison points of Vrb and Vrc (similar to step 910 of FIG. 21). In step 952, an additional read process is performed to compensate for the potential coupling in step 952 (similar to step 912 of FIG. 21). If at step 932 it is determined that no neighbors have been erased, then at step 936 both neighbors have a read process performed using the read comparison points of Vrb and Vrc. In step 938, an additional read process is performed to compensate for potential coupling from both word lines, and the data is reported. In one embodiment, step 938 includes performing the process of FIG. 15A.

Techniques for detecting the potential for the coupling described herein and compensating for that coupling are applicable to detecting the potential for other types of errors and (optionally) compensating for these errors.

The foregoing detailed description serves the purpose of illustration and description. It is also not intended to be exhaustive or to limit the invention to such disclosed forms, and such disclosed forms do not imply all of the invention. Many modifications and variations are possible in light of the above description. The described embodiments are chosen to best explain the principles of the invention and its practical application, thereby enabling those skilled in the art to best utilize the invention in its various embodiments and as appropriate to the specific parts they desire to use. This is for use. The scope of the invention is defined by the appended claims.

Claims (37)

A method of operating nonvolatile storage, Accessing stored timing information, wherein the stored timing information is customized for a data set, the data set being stored in one or more non-volatile storage elements; And And reading the data set from the one or more nonvolatile storage elements, wherein the reading selectively compensates for one or more potential errors in the data set based on the timing information. A method of operating a non-volatile storage, characterized in that it comprises. The method of claim 1, Wherein the one or more potential errors are due to potential coupling between the one or more nonvolatile storage elements and one or more neighboring nonvolatile storage elements. The method of claim 1, The accessing step and the reading step, Reading first time data for a word line associated with the one or more nonvolatile storage elements, and wherein the stored timing information includes the first time data; Reading second time data for a word line associated with neighboring nonvolatile storage elements; Comparing the first time data to the second time data; And Determining whether there is a potential for errors based on the comparison. The method of claim 1, Selectively compensating for the one or more potential errors, Sensing neighboring nonvolatile storage elements for the one or more nonvolatile storage elements; Determining read voltage offsets based on the one or more nonvolatile storage elements based on information sensed from the neighboring nonvolatile storage elements; And Reading the one or more storage elements using the offsets. The method of claim 1, The step of accessing and reading, Reading data from memory elements coupled to a first word line, wherein the memory elements comprise the one or more nonvolatile storage elements and additional nonvolatile storage elements for storing the timing information, the timing information Includes a first value and a second value, wherein the first value indicates a timing for programming the one or more nonvolatile storage elements for a first set of neighbors, and the second value is for a second set of neighbors Indicate timing of programming the one or more nonvolatile storage elements; If the first value indicates that the one or more nonvolatile storage elements have been programmed after the first neighbor set, the second value is that the one or more nonvolatile storage elements have been programmed after the second neighbor set. If the value indicates, reporting the data without compensating for one or more potential errors; And If the first value indicates that the one or more nonvolatile storage elements are potentially programmed prior to the first neighbor set, or the one or more nonvolatile storage elements are potentially located before the second neighbor set If the second value indicates that it has been programmed, then reporting the data after compensating for one or more potential errors. The method of claim 1, Programming the data to the one or more non-volatile storage elements, wherein programming the data comprises programming the timing information. The method of claim 6, The programming step, Reading neighbor timing information associated with a set of neighboring nonvolatile storage elements; And Determining the customized timing information for the data set based on the neighbor timing information. The method of claim 7, wherein The one or more nonvolatile storage elements are multi-state nonvolatile storage elements; Reading the neighbor timing information includes performing a read operation at one reference voltage level; And Determining the timing information is based entirely on the read operation at one reference voltage level. The method of claim 6, The programming step, Reading first neighbor timing information associated with a first set of neighboring nonvolatile storage elements; Determining a first timing value based on the first neighbor timing information; Reading second neighbor timing information associated with a second set of neighboring nonvolatile storage elements; And Determining a second timing value based on the second neighbor timing information, wherein the timing information associated with the set of neighboring nonvolatile storage elements includes the first timing value and the second timing value. Characterized in that it operates a non-volatile storage. The method of claim 9, The first set of neighboring nonvolatile storage elements is coupled to a first word line; The one or more nonvolatile storage elements are coupled to a second word line adjacent to the first word line; The second set of neighboring nonvolatile storage elements is coupled to a third word line adjacent to the second word line; And The one or more potential errors are coupled to the first set of neighboring nonvolatile storage elements and the one or more nonvolatile storage elements and the second set of neighboring nonvolatile storage elements and the one or more. A method for operating nonvolatile storage, characterized in that it is based on coupling of nonvolatile storage elements. The method of claim 1, Compensating the selectively, If the timing information indicates that the one or more nonvolatile storage elements were programmed prior to programming one or more neighboring nonvolatile storage elements, the one or more nonvolatile elements and the one or more Performing a first compensation process for coupling between neighboring nonvolatile storage elements, and If the timing information indicates that the one or more nonvolatile storage elements were not programmed prior to programming the one or more neighboring nonvolatile storage elements, then reading without performing a first compensation process; And operating non-volatile storage. The method of claim 1, And wherein said selectively compensating includes selecting whether or not to use a voltage offset based on said timing information. The method of claim 1, And the timing information comprises an absolute time. The method of claim 1, And the timing information includes a cycle count time. The method of claim 1, Wherein the timing information includes an indication of the order of programming between the one or more nonvolatile storage elements and neighboring nonvolatile storage elements. The method of claim 1, The timing information includes a two bit code indicating whether the data set is erased data, data programmed after programming of neighboring word lines, or potentially programmed data prior to programming of neighboring word lines. Operating non-volatile storage. The method of claim 1, The data set comprises a data page; The one or more nonvolatile storage elements are coupled to a first word line; And The one or more potential errors may include one or more nonvolatile storage elements connected to word lines adjacent to the first word line and one or more of the one or more nonvolatile storage elements. And a coupling between the storage elements. The method of claim 1, Wherein the stored timing information is accessed while reading the data set. The method of claim 1, Wherein the timing information is accessed prior to reading the data set. The method of claim 1, Receiving a read request for the data set. The method of claim 1, Wherein said one or more non-volatile storage elements are NAND flash memory elements. The method of claim 1, And the one or more nonvolatile storage elements are multi-state flash memory elements. Non-volatile storage system, A plurality of nonvolatile storage elements; And One or more management circuits in communication with the nonvolatile storage elements, wherein the one or more management circuits access stored timing information, and the stored timing information is stored in the plurality of nonvolatile storage elements. Customized to a stored data set, and wherein the one or more management circuits read the data set from the plurality of nonvolatile storage elements, the readout being one or more in the data set based on the timing information. And selectively compensating for further potential errors. The method of claim 23, wherein And the one or more potential errors are due to potential coupling between the one or more nonvolatile storage elements and one or more neighboring nonvolatile storage elements. The method of claim 23, wherein The data set is stored in a subset of the plurality of nonvolatile storage elements, the subset having neighboring nonvolatile storage elements; The one or more management circuits read first time data for a word line associated with the subset and read second time data for a word line associated with the neighboring nonvolatile storage elements. ; And The one or more management circuits compare the first time data to the second time data and determine whether there is a potential for errors based on the comparison. The method of claim 23, wherein Compensating the selectively includes selecting whether or not to use a voltage offset and selecting how much to use the voltage offset during a read process based on the neighboring nonvolatile storage elements. Non-volatile storage system. The method of claim 23, wherein The data set is stored in a subset of the plurality of nonvolatile storage elements, the subset having a first set of neighbors and a second set of neighbors; The one or more management circuits read data from memory elements connected to a first word line, the memory elements including additional non-volatile storage elements for storing the subset and the timing information, the timing information being A first value and a second value, wherein the first value indicates timing of programming the subset for a first set of neighbors, and the second value indicates programming of the subset for a second set of neighbors. Indicate timing; The one or more management circuits indicate that the first value indicates that the subset has been programmed after the first set of neighbors and the second value indicates that the subset has been programmed after the second set of neighbors. Report the data without compensating for one or more potential errors; And The one or more management circuits, if the first value indicates that the subset was potentially programmed before the first set of neighbors or the second value is the subset before the second set of neighbors And if it is potentially programmed, reporting the data after compensating for one or more potential errors. The method of claim 23, wherein The one or more management circuits program the data set to a subset of the plurality of nonvolatile storage elements, and programming the data set to the subset includes programming the timing information; And Programming the data set comprises reading neighbor timing information and determining the customized timing information for the data set based on the neighbor timing information. The method of claim 28, The one or more nonvolatile storage elements are multi-state nonvolatile storage elements; Reading the neighbor timing information includes performing a read operation at one reference voltage level; And Determining the timing information is based on the read operation at one reference voltage level. The method of claim 23, wherein The data set is stored in a subset of the plurality of nonvolatile storage elements, the subset having neighboring nonvolatile storage elements; And The selectively compensating means for coupling between the subset and the neighboring nonvolatile storage elements if the timing information indicates that the subset was programmed prior to programming the neighboring nonvolatile storage elements. Performing a first compensation process, and if the timing information indicates that the subset was not programmed prior to programming the neighboring nonvolatile storage elements, reading without performing the first compensation process. Non-volatile storage system comprising a. The method of claim 23, wherein And the timing information may comprise an indication of absolute time, relative time, or order of programming. The method of claim 23, wherein The data set comprises a data page; The data set is stored in a subset of the plurality of nonvolatile storage elements coupled to a first word line; And Wherein said one or more potential errors are due to coupling between said subset and one or more nonvolatile storage elements coupled to word lines adjacent to said first word line. system. The method of claim 23, wherein And said stored timing information is accessed simultaneously while reading said data set. The method of claim 23, wherein And the one or more management circuits comprise one or more of a state machine, a decoder, a sense circuit and a controller. The method of claim 23, wherein And the plurality of nonvolatile storage elements are NAND flash memory devices. The method of claim 23, wherein And the plurality of nonvolatile storage elements are multi-state flash memory devices. The method of claim 23, wherein And the plurality of nonvolatile storage elements comprises floating gates.

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