KR20080051273A - Electrophoretic display and method for manufacturing thereof - Google Patents

Abstract

An electrophoretic display device and a method of manufacturing the electrophoretic display device are provided to form a gate line and a data line such that the gate line and the data line include an upper layer made of an opaque metal and a lower layer made of an oxide of the opaque metal and adjust the thickness of the lower layer appropriately to minimize reflective light to thereby improve the contrast ratio and picture quality of the electrophoretic display device. An electrophoretic display device includes a substrate(110), a first signal line, a second signal line, a switching element, and a pixel electrode(191). The first signal line is formed on the substrate. The second signal line intersects the first signal line. The switching element has a first terminal(124), a second terminal(173) and a third terminal. The first and second terminals of the switching element are respectively connected to the first and second signal lines. The pixel electrode is connected to the third terminal of the switching element. The first and second signal lines respectively include upper layers(124q,173q) formed of an opaque metal and lower layers(124p,173p) formed of an oxide of the opaque metal.

Description

Electrophoretic display and its manufacturing method {ELECTROPHORETIC DISPLAY AND METHOD FOR MANUFACTURING THEREOF}

1 is a layout view of a thin film transistor array panel and a common electrode panel for an electrophoretic display device according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II-II ′ of FIG. 1 of an electrophoretic display device including the thin film transistor array panel and the common electrode display panel illustrated in FIG. 1;

FIG. 3 is a cross-sectional view of the electrophoretic display device including the thin film transistor array panel and the common electrode panel illustrated in FIG. 1 taken along lines III-III 'and III'-III' 'of FIG. 1,

4 and 5 are cross-sectional views in an intermediate step of manufacturing the thin film transistor array panel of FIGS. 7 and 8, respectively.

6 is a layout view of a thin film transistor array panel at an intermediate stage of manufacturing the thin film transistor array panel illustrated in FIG. 1 according to an exemplary embodiment of the present disclosure;

FIG. 7 is a cross-sectional view of the thin film transistor array panel of FIG. 6 taken along the line VII-VII ′. FIG.

FIG. 8 is a cross-sectional view of the thin film transistor array panel of FIG. 6 taken along lines VIII-VIII 'and VIII'-VIII' '.

FIG. 9 is a layout view of a thin film transistor array panel in the next step of FIG. 6.

FIG. 10 is a cross-sectional view of the thin film transistor array panel of FIG. 9 taken along the line X-X ',

FIG. 11 is a cross-sectional view of the thin film transistor array panel of FIG. 9 taken along lines XI-XI ′ and XI′-XI ″.

12 and 13 are cross-sectional views at intermediate stages of manufacturing the thin film transistor array panel of FIGS. 15 and 16, respectively.

FIG. 14 is a layout view of a thin film transistor array panel in the next step of FIG. 10;

FIG. 15 is a cross-sectional view of the thin film transistor array panel of FIG. 14 taken along the line XV-XV ′. FIG.

FIG. 16 is a cross-sectional view of the thin film transistor array panel of FIG. 14 taken along lines XVI-XVI 'and XVI'-XVI',

FIG. 17 is a layout view of a thin film transistor array panel in the next step of FIG. 14;

FIG. 18 is a cross-sectional view of the thin film transistor array panel of FIG. 17 taken along the line XIII-XIII ′,

19 is a cross-sectional view of the thin film transistor array panel of FIG. 17 taken along lines XIX-XIX 'and XIX'-XIX' '.

<Explanation of symbols for the main parts of the drawings>

100: thin film transistor display panel

110: insulating substrate 121: gate line

124: gate electrode 129: end of gate line

140: gate insulating film 151: linear semiconductor layer

161: linear ohmic contact 171: data line

173: source electrode 175: drain electrode

179: end of the data line 180: protective film

181, 182, and 185: contact hole 191: pixel electrode

200: common electrode display panel 210: insulating substrate

270: common electrode 300: electrophoretic film

310: hardener 320: capsule

323, 326: electrophoretic particles 328: dispersion medium

330: electrophoretic member

The present invention relates to an electrophoretic display device and a manufacturing method thereof.

In general, a flat panel display device replaces a conventional CRT and is a flat panel display device such as an organic light emitting diode display (OLED) and an electrophoretic display (EPD). Is used a lot.

Among them, an electrophoretic display includes a thin film transistor connected to a pixel electrode, a lower substrate on which a plurality of pixel electrodes arranged in a row form, and a plurality of signal lines for transmitting a signal are formed, and light-shielded facing the lower substrate. And an upper substrate on which the member and the common electrode are formed. And an electrophoretic film that exists between two substrates and has a positive (+) or negative (-) charge and includes electrophoretic particles having color.

Such an electrophoretic display device displays a desired color in such a manner that electrophoretic particles rotate or move closer to electrodes having different polarities according to voltages applied to two electrodes. The electrophoretic film includes an electrophoretic member including a microcapsule containing a dispersion medium in which electrophoretic particles are dispersed, and a binder for fixing the electrophoretic member to either electrode.

When the pixel electrode is opaque and the common electrode is transparent, the electrophoretic display displays an image in an upward direction of the substrate by applying a top emission method. On the other hand, when the pixel electrode is transparent and the common electrode is opaque, a bottom meission method is applied to display the influence on the downward direction of the substrate.

However, in the electrophoretic display device using the conventional bottom emission method, as the external light is reflected from the plurality of signal lines and light leaks, the brightness of the electrophoretic display device may be reduced.

Therefore, the technical problem to be achieved by the present invention is to improve the brightness of the electrophoretic display device.

An electrophoretic display device according to the present invention has a substrate, a first signal line formed on the substrate, a second signal line intersecting the first signal line, first to third terminals, and the first signal line and the second signal line. And a pixel electrode connected to the third terminal of the switching element, wherein the first signal line and the second signal line are each formed of an opaque metal and And a bottom film made of an opaque metal oxide.

The opaque metal may include chromium (Cr), chromium alloys, molybdenum (Mo), and molybdenum alloys.

The electrophoretic film may be further formed on the pixel electrode, wherein the electrophoretic film may contain a plurality of electrophoretic particles having a color, a dispersion medium in which the electrophoretic particles are dispersed, the electrophoretic particles, and the dispersion medium. It may include an electrophoretic member comprising a capsule, and a curing agent for attaching the electrophoretic member on the substrate.

The lower layer may have a thickness within 1,000 μs.

Performing a sputtering process targeting an opaque metal on a substrate in an oxygen atmosphere for a predetermined time to form a first opaque metal oxide layer, interrupting the oxygen supply and proceeding the sputtering process to form the first opaque metal oxide layer Forming a first signal line by photo-etching the first opaque metal oxide layer and the first opaque metal layer, forming an insulating film on the first signal line, and forming a semiconductor on the insulating film And sequentially forming an ohmic contact member, and performing a sputtering process of targeting an opaque metal on the insulating layer and the ohmic contact member in an oxygen atmosphere for a predetermined time to form a second opaque metal oxide layer. Block the phase and proceed with the sputtering process Forming a second opaque metal layer on the second opaque metal oxide layer, and photo-etching the second opaque metal oxide layer and the second opaque metal layer to form a second signal line crossing the first signal line. .

The first opaque metal layer and the second opaque metal layer may be made of chromium (Cr), chromium alloy, molybdenum (Mo), or molybdenum alloy.

The first opaque metal oxide layer and the second opaque metal oxide layer may be formed of chromium oxide (CrOx) or molybdenum oxide (MoOx).

The method may further include forming a passivation layer on the second signal line, forming a pixel electrode on the passivation layer, and forming an electrophoretic film on the pixel electrode.

The first opaque metal oxide layer and the second opaque metal oxide layer may be formed to a thickness within 1,000 kPa.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is said to be "on" another part, this includes not only the other part "directly" but also another part in the middle. On the contrary, when a part is “just above” another part, there is no other part in the middle.

Next, an electrophoretic display device and a manufacturing method thereof according to various embodiments of the present invention will be described with reference to the accompanying drawings.

First, an electrophoretic display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3.

1 is a layout view of a thin film transistor array panel and a common electrode panel for an electrophoretic display device according to an exemplary embodiment of the present invention, and FIG. 2 is an electrophoretic display device including the thin film transistor array panel and the common electrode panel illustrated in FIG. 1. 1 is a cross-sectional view taken along the line II-II 'of FIG. 1, and FIG. 3 is an electrophoretic display device including the thin film transistor array panel and the common electrode display panel illustrated in FIG. 1. '' A cross section along the line.

1 to 3, the electrophoretic display device according to the present exemplary embodiment includes a thin film transistor array panel 100, a common electrode display panel 200, and an electrophoretic film 300 interposed therebetween.

First, the common electrode display panel 200 will be described.

As shown in FIG. 2, a common electrode 270 made of an opaque metal is formed on the upper substrate 210 made of transparent glass or plastic.

Next, the thin film transistor array panel 100 will be described.

As shown in FIGS. 1 to 3, a plurality of gate lines 121 and a plurality of storage electrode lines are provided on the lower substrate 110 made of transparent glass or plastic. 131 is formed. Here, the gate line 121 includes a plurality of gate electrodes 124 and a wide end portion 129 for connecting to another layer or an external circuit.

The gate line 121 transmits a gate signal and mainly extends in a horizontal direction. Each gate line 121 includes a plurality of gate electrodes 124 protruding downward and an end portion 129 having a large area for connection with another layer or an external driving circuit. A gate driving circuit (not shown) for generating a gate signal is mounted on a flexible printed circuit film (FPC) (not shown) attached to the lower substrate 110 or on the lower substrate 110. It may be directly mounted or integrated in the lower substrate 110. When the gate driving circuit is integrated on the lower substrate 110, the gate line 121 may be extended to be directly connected thereto.

The storage electrode line 131 receives a predetermined voltage, and includes a stem line extending substantially in parallel with the gate line 121 and a plurality of pairs of storage electrodes 133a and 133b separated therefrom. Each of the storage electrode lines 131 is positioned between two adjacent gate lines 121, and the stem line is closer to the lower side of the two gate lines 121. Each of the sustain electrodes 133a and 133b has a fixed end connected to the stem line and a free end opposite thereto. The fixed end of one sustain electrode 133b has a large area, and its free end is divided into two parts, a straight part and a bent part. However, the shape and arrangement of the storage electrode line 131 may be modified in various ways.

The gate line 121 and the storage electrode line 131 include two conductive layers having different physical properties, that is, lower layers 124p and 131p and upper layers 124q and 131q. The top films 124q and 131q are particularly materials having excellent physical, chemical and electrical contact properties with indium tin oxide (ITO) or indium zinc oxide (IZO), opaque metals, or alloys thereof, such as molybdenum (Mo) or molybdenum It is made of molybdenum-based metals such as alloys and nitrides thereof, chromium (Cr), tantalum (Ta) and titanium (Ti). The lower layers 124p and 131p are made of an opaque metal oxide constituting the upper layers 121q and 131q such as molybdenum oxide (MoOx) and chromium oxide (CrOx).

As such, when the gate line 121 and the storage electrode line 131 are formed of the double layer of the metal oxide and the metal, and the thicknesses of the metal oxide layers that are the lower layers 124p and 131p are properly adjusted, the lower layers 124p and 131p and The light reflected at the interface of the upper layers 121q and 131q and the light reflected at the surfaces of the lower layers 124p and 131p cause a destructive interference, so that external light entering through the bottom surface of the substrate 110 is gate line 121. And reflection by the storage electrode line 131 can be minimized. Here, the lower layers 124p and 131p of the gate line 121 and the storage electrode line 131 preferably have a thickness of less than 1,000 GPa, and the upper films 121q and 131q have a thickness of 1,000 GPa or more.

However, the gate line 121 and the storage electrode line 131 may be made of various metals and metal oxides.

1 through 3, the lower layer of the gate electrode 124 and the storage electrode line 131 is denoted by the alphabet letter p and the upper layer by the letter q.

Side surfaces of the gate line 121 and the storage electrode line 131 are inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30 ° to about 80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate line 121 and the storage electrode line 131.

A plurality of linear semiconductors 151 made of polysilicon are formed on the gate insulating layer 140. The linear semiconductor 151 mainly extends in the longitudinal direction and includes a plurality of projections 154 extending toward the gate electrode 124.

Linear and island ohmic contacts 161 and 165 are sequentially formed on the semiconductor 151.

The ohmic contacts 161 and 165 may be made of a material such as amorphous silicon and polycrystalline silicon doped with a high concentration of n-type impurities such as phosphorus or p-type impurities such as boron (B), or may be made of silicide. . The linear ohmic contact 161 has a plurality of protrusions 163, and the protrusion 163 and the ohmic contact 165 are paired and disposed on the protrusion 154 of the semiconductor 151.

Side surfaces of the semiconductors 151 and 154 and the ohmic contacts 161 and 165 are also inclined with respect to the surface of the substrate 110 and the inclination angle is about 30 ° to 80 °.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 161 and 165 and the gate insulating layer 140.

The data line 171 transmits a data signal and mainly extends in the vertical direction to cross the gate line 121. Each data line 171 also crosses the storage electrode line 131 and is present between adjacent sets of storage electrodes 133a and 133b. Each data line 171 includes a plurality of source electrodes 173 extending toward the gate electrode 124 and an end portion 179 having a large area for connection with another layer or an external driving circuit. A data driving circuit (not shown) for generating a data signal is mounted on a flexible printed circuit film (not shown) attached to the substrate 110, directly mounted on the substrate 110, or integrated in the substrate 110. Can be. When the data driving circuit is integrated on the substrate 110, the data line 171 may be extended to be directly connected to the data driving circuit.

The drain electrode 175 is separated from the data line 171 and faces the source electrode 173 with respect to the gate electrode 124.

Each drain electrode 175 has one wide end portion and the other end having a rod shape, and the rod end portion is partially surrounded by the bent source electrode 173.

One gate electrode 124, one source electrode 173, and one drain electrode 175 together with the protrusion 154 of the semiconductor 151 form one thin film transistor (TFT). A channel of the transistor is formed in the protrusion 154 between the source electrode 173 and the drain electrode 175.

The data line 171 and the drain electrode 175 include two conductive layers having different physical properties, that is, lower layers 173p and 175p and upper layers 173q and 175q thereon. The upper layers 173q and 175q of the data line 171 may be formed of an opaque metal made of a material having excellent physical, chemical, and electrical contact properties, or an alloy thereof, such as molybdenum (Mo) or a molybdenum alloy, and chromium ( Cr), tantalum (Ta), titanium (Ti) and the like. The lower layers 173p and 175p of the data line 171 are made of an opaque metal oxide forming the upper layers 173q and 175q such as molybdenum oxide (MoOx) and chromium oxide (CrOx).

As such, when the data line 171 and the drain electrode 175 are formed of the double layer of the metal oxide and the metal, and the thicknesses of the metal oxide layers which are the lower layers 173p and 175p are properly adjusted, the lower layers 173p and 175p and The light reflected at the interface of the upper layers 173q and 175q and the light reflected at the surfaces of the lower layers 173p and 175p cause a destructive interference, so that external light entering through the lower surface of the substrate 110 is transmitted through the data line 171. And reflection by the drain electrode 175 may be minimized.

Here, it is preferable that the lower layers 173p and 175p of the data line 171 and the drain electrode 175 have a thickness of 1,000 μs or less, and the upper films 173q and 175q have a thickness of 1,000 μs or more.

However, the data line 171 and the drain electrode 175 may be made of various other metals and metal oxides.

The side of the data line 171 and the drain electrode 175 may also be inclined at an inclination angle of about 30 ° to about 80 ° with respect to the surface of the substrate 110.

The ohmic contacts 161 and 165 exist only between the semiconductor 151 below and the data line 171 and the drain electrode 175 thereon, and lower the contact resistance therebetween.

The semiconductor 151 has a portion exposed between the source electrode 173 and the drain electrode 175 and not covered by the data line 171 and the drain electrode 175. In most places, the width of the linear semiconductor 151 is smaller than the width of the data line 171. However, as described above, the width of the linear semiconductor 151 is widened at the portion where it meets the gate line 121 to smooth the profile of the surface. Prevents disconnection.

A passivation layer 180 is formed on the data line 171, the drain electrode 175, and the exposed semiconductor 151.

On the data line 171 and the drain electrode 175, a passivation layer 180 made of an organic insulator having excellent planarization characteristics and photosensitivity is formed. Here, the organic insulator constituting the passivation layer 180 may have photosensitivity, and the dielectric constant thereof is preferably about 4.0 or less.

Meanwhile, the passivation layer 180 may be formed of an inorganic insulator such as silicon nitride (SiNx) and silicon oxide (SiOx), or may include a lower passivation layer made of an inorganic insulator and an upper passivation layer made of an organic insulator.

In the passivation layer 180, a plurality of contact holes 181, 182, and 185 exposing the end portion 179 and the drain electrode 175 of the data line 171 and the end portion of the gate line 121 ( A plurality of contact holes 181 exposing the 129, a plurality of contact holes 183a exposing a part of the sustain electrode line 131 near the fixed end of the sustain electrode 133b, and a straight portion of the free end of the sustain electrode 133a. A plurality of contact holes 183b are formed.

A plurality of pixel electrodes 191, a plurality of overpasses 83, and a plurality of contact assistants 81 and 82 are formed on the passivation layer 180. They may be made of a transparent conductive material such as ITO or IZO or a reflective metal such as aluminum, silver, chromium or an alloy thereof.

The pixel electrode 191 is physically and electrically connected to the drain electrode 175 through the contact hole 185 and receives a data voltage from the drain electrode 175.

The contact auxiliary members 81 and 82 are connected to the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 compensate for and protect the adhesion between the end portions 179 and 129 of the data line 171 and the gate line 121 and the external device.

The connecting leg 83 crosses the gate line 121 and exposes the exposed portion of the storage electrode line 131 and the storage electrode through contact holes 183a and 183b positioned on opposite sides with the gate line 121 interposed therebetween. 133b) is connected to the exposed end of the free end. The storage electrode lines 131 including the storage electrodes 133a and 133b may be used together with the connecting legs 83 to repair defects in the gate line 121, the data line 171, or the thin film transistor.

An electrophoretic film 300 is formed on the pixel electrode 191 and the passivation layer 180.

The electrophoretic film 300 includes an electrophoretic member 330 and a curing agent 310 for fixing the electrophoretic member 330 on the lower substrate 110.

Electrophoretic member 330 is dispersed and fixed in the electrophoretic film 300, electrophoretic particles (323, 326) and electrophoretic particles (323, 326) having a negative (+) charge and a positive (+) charge ) Is a dispersion medium 328 is dispersed, and the capsule (320) containing them (323, 326, 328). Here, the negatively charged electrophoretic particles 323 have a black color, and the positively-charged electrophoretic particles 326 have a white color. However, the electrophoretic particles 323 and 326 may have colors such as red, blue, and green.

In the electrophoretic display device, the pixel electrode 191 to which the data voltage of the thin film transistor array panel 100 is applied generates an electric field together with the common electrode 270 of the common electrode display panel 200 to which a common voltage is applied. do. The generated electric field changes the positions of the electrophoretic particles 323 and 326 of the plurality of electrophoretic members 330 which are dispersed and fixed in the electrophoretic film 300, thereby displaying a desired image. Here, the electrophoretic particles 323 and 326 may display a black and white image. When the white electrophoretic particles 326 move in a direction in which the common electrode 270 is located, a white image is displayed and black electrophoresis is performed. When the particles 323 move in the direction in which the common electrode 270 is located, a black image is displayed.

Next, a method of manufacturing the thin film transistor array panel for the electrophoretic display device illustrated in FIGS. 1 to 3 will be described in detail with reference to FIGS. 4 to 19.

4 and 5 are cross-sectional views in an intermediate step of manufacturing the thin film transistor array panels of FIGS. 7 and 8, respectively, and FIG. 6 is an intermediate fabrication of the thin film transistor array panel illustrated in FIG. 1 according to an embodiment of the present invention. FIG. 7 is a cross-sectional view of the thin film transistor array panel of FIG. 6 taken along the line VII-VII ′, and FIG. 8 is a line VIII-VIII ′ and VIII of the thin film transistor array panel of FIG. 6. 9 is a cross-sectional view taken along the line '-VIII', and FIG. 9 is a layout view of the TFT panel in the next step of FIG. 6, and FIG. 10 is a diagram illustrating the TFT panel shown in FIG. 9 along the line X-X '. 11 is a cross-sectional view of the thin film transistor array panel of FIG. 9 taken along lines XI-XI ′ and XI′-XI ″, and FIGS. 12 and 13 are thin film transistors of FIGS. 15 and 16, respectively. During manufacture of the display panel FIG. 14 is a layout view of the thin film transistor array panel of the next step of FIG. 10, FIG. 15 is a cross-sectional view of the thin film transistor array panel of FIG. 14 taken along the line XV-XV ′, and FIG. 14 is a cross-sectional view taken along line XVI-XVI 'and XVI'-XVI' ', and FIG. 17 is a layout view of the thin film transistor array panel in the next step of FIG. 14, and FIG. FIG. 19 is a cross-sectional view of the thin film transistor array panel cut along the line XIII-XIII ', and FIG. 19 is a cross-sectional view of the thin film transistor array panel of FIG. 17 taken along the line XIX-XIX' and XIX'-XIX '.

First, as shown in FIGS. 4 and 5, sputtering targets an opaque metal such as chromium (Cr) or molybdenum (Mo) on a lower substrate 110 made of glass or plastic. The process is performed in an oxygen (O 2) atmosphere for a predetermined time to form a first opaque metal oxide layer 20 made of an opaque metal oxide such as chromium oxide (CrOx) and phybdenum oxide (MoOx).

Subsequently, after a predetermined time, supply of oxygen (O 2) is stopped and a sputtering process is performed to form a first opaque metal layer 40 made of chromium (Cr) or molybdenum (Mo) on the first metal oxide layer 20. .

Next, as shown in FIGS. 6 to 8, the first opaque metal layer 40 and the first opaque metal oxide layer 20 are sequentially etched to include a gate including the gate electrode 124 and the end portion 129. The storage electrode line 131 including the line 121 and the storage electrodes 133a and 133b is formed.

In FIGS. 7 and 8, the gate electrode 124, the end portion 129, and the storage electrode line 131 of the gate line 121 are denoted by the letter p and the letter q as the upper layer.

Then, as illustrated in FIGS. 9 to 11, a gate insulating layer 140 is formed on the gate line 121 and the storage electrode line 131. In this case, the gate insulating layer 140 is made of silicon nitride (SiNx) or silicon oxide (SiOx).

Next, an impurity doped intrinsic amorphous silicon and an impurity doped amorphous silicon layer (extrinsic amorphous silicon) on the gate insulating layer 140 by a plasma enhanced chemical vapor deposition (PECVD) method The layers are sequentially stacked and the two layers are sequentially patterned to form a plurality of linear impurity semiconductors 164 and a plurality of linear intrinsic semiconductors 151.

12 and 13, sputtering targets an opaque metal such as chromium (Cr) or molybdenum (Mo) on the gate insulating layer 140 and the linear impurity semiconductor 164. ) Is performed in an oxygen (O 2) atmosphere for a predetermined time to form a second opaque metal oxide layer 60 made of an opaque metal oxide such as chromium oxide (CrOx) and molybdenum oxide (MoOx).

Subsequently, after a predetermined time, the supply of oxygen (O 2) is stopped and a sputtering process is performed to form a second opaque metal layer 80 made of chromium (Cr) or molybdenum (Mo) on the second metal oxide layer 60. .

Next, as shown in FIGS. 14 to 16, the second opaque metal layer 80 and the second opaque metal oxide layer 60 are sequentially etched using a mask to sequentially source source 173 and end portion 179. The data line 171, the drain electrode 175, the ohmic contact 161, and the semiconductor 151 may be formed.

Subsequently, the portions of the linear impurity semiconductor 164 that are not covered by the data line 171 and the drain electrode 175 are removed to remove the portions of the linear ohmic contacts 161 including the protrusions 163 and the islands of the plurality of island types. While completing the contact member 165, the portion of the intrinsic semiconductor 151 beneath it is exposed.

In FIG. 15 and FIG. 16, the lower layer of the data line 171 and the drain electrode 175 including the source electrode 173 and the end portion 179 are denoted by the letter p and the upper layer by the letter q. .

In the present invention, the gate line 121, the storage electrode line 131, the data line 171, and the drain electrode 175 serve as a light blocking member to prevent leakage of light in the electrophoretic display device.

As described above, the gate line 121, the storage electrode line 131, the data line 171, and the drain electrode 175 are formed of the upper layers 124q, 129q, 131q, 173q, and 175q formed of an opaque metal. The lower films 124p, 129p, 131p, 173p, and 175p made of an opaque metal oxide forming the films 124q, 129q, 131q, 173q, and 175q. Accordingly, the gate line 121, the storage electrode line 131, the data line 171, and the drain electrode 175 have refractive indices of the external light incident on the upper layers 124q, 129q, 131q, 173q, and 175q and the lower layer 124p. , 129p, 131p, 173p, and 175p have different refractive indices. In this case, when the lower layers 124p, 129p, 131p, 173p, and 175p are formed to an appropriate thickness, an interface between the upper layers 124q, 129q, 131q, 173q, and 175q and the lower layers 124p, 129p, 131p, 173p, and 175p The light reflected from the light and the light reflected from the surfaces of the lower layers 124p, 129p, 131p, 173p, and 175p cancel each other and cause external light to pass through the gate line 121, the storage electrode line 131, the data line 171, and It is possible to prevent the black from being increased by being reflected by the drain electrode 175. Therefore, the contrast ratio and the image quality of the electrophoretic display device can be improved. Here, the lower layers 124p, 129p, 131p, 173p, and 175p of the gate line 121, the storage electrode line 131, the data line 171, and the drain electrode 175 have a thickness of 1,000 μm or less, and the upper layer (173q, 175q) preferably has a thickness of 1,000 GPa or more.

17 to 19, a passivation layer 180 is formed on the gate insulating layer 140, the data line 171, and the drain electrode 175. In this case, the passivation layer 180 is made of an organic insulator. Here, the organic insulator may have photosensitivity and the dielectric constant thereof is preferably about 4.0 or less.

However, the passivation layer 180 may include a lower passivation layer made of an inorganic insulator such as silicon nitride (SiNx) and silicon oxide (SiOx), and an upper passivation layer made of an organic insulator, or may be made of only an inorganic insulator.

Next, the passivation layer 180 is etched to expose the end portion 129 of the gate line 121, the end portion 179 of the data line 171, and a portion of the storage electrode line 131 near the fixed end of the storage electrode 133b. A plurality of contact holes 183a, a plurality of contact holes 183b exposing a straight portion of the free end of the sustain electrode 133a, and contact holes 181, 182, 183a, 183b, and 185 exposing the drain electrode 175 are disposed. Form.

Next, as shown in FIGS. 2 and 3, transparent electrodes such as ITO or IZO are sputtered on the contact holes 181, 182, 183a, 183b, and 185 and the passivation layer 180. The pixel electrode 191, the connection legs 83, and the contact members 81 and 82 are formed.

Then, the electrophoretic film 300 is formed on the passivation layer 180 and the pixel electrode 191.

The electrophoretic film 300 includes an electrophoretic member 330 and a curing agent 310 for fixing the electrophoretic member 330 on the lower substrate 110.

Electrophoretic member 330 is dispersed and fixed in the electrophoretic film 300, electrophoretic particles (323, 326) and electrophoretic particles (323, 326) having a negative (+) charge and a positive (+) charge ) Is a dispersion medium 328 is dispersed, and the capsule (320) containing them (323, 326, 328). Here, the negatively charged electrophoretic particles 323 have a black color, and the positively-charged electrophoretic particles 326 have a white color. However, the electrophoretic particles 323 and 326 may have colors such as red, blue, and green.

Next, as illustrated in FIG. 1, the common electrode display panel 200 is coupled to the thin film transistor array panel 100. The common electrode display panel 200 is manufactured by forming a common electrode 270 made of an opaque metal by using a method such as sputtering on the upper substrate 210, and is formed of a thin film transistor array panel by a sealing material (not shown). 100).

In the present invention, the gate wiring and the data wiring are formed to include an upper film made of an opaque metal and a lower film made of an oxide of a metal constituting the upper film. At this time, the refractive index of the lower film which is a metal oxide film and the upper film which is a metal film differs. Therefore, when the thickness of the lower layer is properly adjusted, the light reflected from the interface between the upper layer and the lower layer and the light reflected from the surface of the lower layer may cause mutual interference to minimize the reflected light. Through this, the contrast ratio and the image quality of the electrophoretic display device can be improved.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (10)

Board, A first signal line formed on the substrate, A second signal line crossing the first signal line, A switching element having first to third terminals and having a first terminal and a second terminal connected to the first signal line and the second signal line, respectively; A pixel electrode connected to the third terminal of the switching element Including; And the first signal line and the second signal line include an upper layer made of an opaque metal and a lower layer made of an oxide of the opaque metal. In claim 1, The opaque metal may include chromium (Cr), chromium alloys, molybdenum (Mo), and molybdenum alloys. In claim 1, An electrophoretic display device further comprising an electrophoretic film formed on the pixel electrode. In claim 3, The electrophoretic film, An electrophoretic member comprising a plurality of electrophoretic particles having a color, a dispersion medium in which the electrophoretic particles are dispersed, the electrophoretic particles and a capsule containing the dispersion medium, and Curing agent for attaching the electrophoretic member on the substrate Electrophoretic display device comprising a. In claim 1, And the lower layer has a thickness within 1,000 mW. Performing a sputtering process targeting the opaque metal on the substrate in an oxygen atmosphere for a predetermined time to form a first opaque metal oxide layer, Interrupting the oxygen supply and performing the sputtering process to form a first opaque metal layer on the first opaque metal oxide layer; Photo-etching the first opaque metal oxide layer and the first opaque metal layer to form a first signal line; Forming an insulating film on the first signal line; Sequentially forming a semiconductor and an ohmic contact on the insulating film, Forming a second opaque metal oxide layer on the insulating film and the ohmic contact by performing a sputtering process of targeting an opaque metal in an oxygen atmosphere for a predetermined time; Blocking the oxygen supply and performing the sputtering process to form a second opaque metal layer on the second opaque metal oxide layer, and Photo-etching the second opaque metal oxide layer and the second opaque metal layer to form a second signal line crossing the first signal line Method of manufacturing an electrophoretic display device comprising a. In claim 6, And the first opaque metal layer and the second opaque metal layer are made of chromium (Cr), chromium alloy, molybdenum (Mo), or molybdenum alloy. In claim 7, And the first opaque metal oxide layer and the second opaque metal oxide layer are formed of chromium oxide (CrOx) or molybdenum oxide (MoOx). In claim 6, Forming a passivation layer on the second signal line; Forming a pixel electrode on the passivation layer; And forming an electrophoretic film on the pixel electrode. In claim 6, The first opaque metal oxide layer and the second opaque metal oxide layer are formed in a thickness of less than 1,000 GPa.

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